CN104157680A - 一种半导体模板及其制作方式及具有其的led或fet组件 - Google Patents

一种半导体模板及其制作方式及具有其的led或fet组件 Download PDF

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CN104157680A
CN104157680A CN201410380142.5A CN201410380142A CN104157680A CN 104157680 A CN104157680 A CN 104157680A CN 201410380142 A CN201410380142 A CN 201410380142A CN 104157680 A CN104157680 A CN 104157680A
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semiconductor film
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程志青
张家宏
卓昌正
林兓兓
谢翔麟
徐志波
黎国昌
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Anhui Sanan Optoelectronics Co Ltd
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Abstract

本发明公开了一种半导体模板及其制作方式及具有其的LED或FET组件，包括AlN基板，并设有氮化物半导体膜层形成于AlN基板上，制作过程中采用过渡基板，能够得到大面积、较厚、高质量且无翘曲的氮化物半导体模板，并且制作过程方便，成本低。

Description

一种半导体模板及其制作方式及具有其的LED或FET组件
技术领域
本发明属于半导体材料技术领域，尤其涉及一种半导体模板及其制作方式及具有其的LED或FET组件。
背景技术
目前AlGaInN(氮化铝镓铟)系LED or FET组件大多使用sapphire substrate(蓝宝石基板)，或SiC或free stand GaN substrate(独立式氮化镓基板)，
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：这几种基板价格较高，且不易制作大尺寸基板，而近年来有人改使用价格低廉的Si基板当LED基板，但因热膨胀系数与晶格常数差异较大，所以当AlGaInN膜厚>3um时，容易有裂纹和翘曲的问题，仍无法达到很好的良率大量生产。
发明内容
本发明所要解决的技术问题是提供一种氮化物半导体膜层较厚时不易发生裂纹和翘曲、能够制作大尺寸基板、成本低、制作方便的半导体模板及其制作方式及具有其的LED或FET组件。
为了解决上述技术问题，本发明所采用的技术方案是：一种半导体模板，包括AlN基板，并设有氮化物半导体膜层形成于所述AlN基板上。
所述氮化物半导体膜层为Al(x)Ga(1-x)N系材料，0<＝x<＝1。
一种上述的半导体模板的制作方式，包括以下步骤：
1)在过渡基板上成长小于临近厚度的氮化物半导体膜层；
2)在氮化物半导体膜层表面镀AlN基板；
3)消除过渡基板，暴露出氮化物半导体膜层的表面；
4)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层。
所述过渡基板为硅、蓝宝石或碳化硅基板。
所述AlN基板厚度在80um以上。
所述过渡基板为Si基板，消除Si基板分为两步：将Si基板研磨减薄到100um，再使用Si蚀刻液以化学蚀刻方式移除。
一种上述的半导体模板的制作方式，包括以下步骤：
1)在第一过渡基板上成长小于临近厚度的氮化物半导体膜层；
2)将氮化物半导体膜层固定在第二过渡基板上；
3)消除第一过渡基板，暴露出氮化物半导体膜层的表面；
4)在暴露出的氮化物半导体膜层的表面镀AlN基板；
5)消除第二过渡基板，暴露出氮化物半导体膜层的表面；
6)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层。
所述第一过渡基板为硅、蓝宝石或碳化硅基板，所述第二过渡基板为硅基板或电镀基板。
所述AlN基板厚度在80um以上。
一种LED或FET组件，具有上述的半导体模板。
上述技术方案中的一个技术方案具有如下优点或有益效果，在大尺寸的Si基板上成长大面积、高质量氮化物半导体膜层，再将氮化物半导体膜层转移到与氮化物半导体膜层晶格常数与热膨胀系数都较接近的氮化铝基板上，后续再使用此模板二次长晶时由于氮化铝基板热膨胀系数与氮化物半导体膜层差异较原Si基板小，故最终能得到大面积、较厚、高质量且无翘曲的氮化物半导体模板，并且制作过程方便，成本低。加上使用此技术亦能简单得到一高质量的N-face的氮化物半导体模板，N-face的氮化物半导体模板可应用到N-face的氮化镓(氮化铝镓)HEMT组件上，N-face的氮化镓(氮化铝镓)HEMT组件相较于传统的G-Face氮化镓(氮化铝镓)HEMT组件理论上有更高的电子迁移率、更好的2DEG限域性、更低的奥姆电极接触，并更容易实现增强型的HEMT。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将对本发明实施方式作进一步地详细描述。
实施例一
一种半导体模板，包括AlN基板，并设有氮化物半导体膜层形成于所述AlN基板上。氮化物半导体膜层为GaN或Al(x)Ga(1-x)N系材料，0<＝x<＝1，AlN基板与氮化物半导体膜层晶格常数与热膨胀系数都较接近，不易发生裂纹和翘曲。
实施例二
一种上述的半导体模板的制作方式，包括以下步骤：
1)利用MOCVD方式在第一Si基板上成长小于临近厚度(如3um)高质量表面无裂纹的氮化物半导体膜层；临界厚度是指氮化物半导体膜在基板上成长时容易有裂纹和翘曲的问题产生时的厚度，根据基板类型和尺寸会有所不同。其包含以下步骤：
a、将第一Si基板在H2的气氛下加热到1100度5min以去除Si基板上的氧化物。
b、降低温度到1080度并控制反应室压力在100torr，通入TMA(三甲基铝)和NH3，成长氮化铝缓冲层100nm。
c、再通入TMG(三甲基镓)成长氮化铝镓应力控制层。
d、关掉TMA和TMG，改变成长温度到1050度并控制反应室压力在200torr，后打开TMG成长氮化镓3um。
e、关掉TMA和TMG维持现有NH3的状况下降温并得到无裂纹的高质量G-Face氮化镓半导体薄膜。
2)将氮化物半导体膜层利用晶圆接合(wafer bonding)技术固定在第二Si基板上；例如使用常见的Au-Au bonding技术(金线键合技术)将氮化物半导体膜层固定在第二Si基板。
3)消除第一Si基板，暴露出氮化物半导体膜层的表面；将第一Si基板研磨减薄到100um，再使用常见的Si蚀刻液以化学蚀刻方式移除第一Si基板，化学蚀刻前第二Si基板表面需以蒸镀金属或贴上蓝膜保护。采用两步主要是为了加速移除Si基板过程，并减少长时间的化学蚀刻同时对第二Si基板造成的损害。
4)利用PVD(物理气相沉积)方式在芯片表面温度500度以下的温度沉积氮化铝基板在氮化物半导体膜层表面上，具体地，在暴露出的氮化物半导体膜层的表面利用sputter(溅镀)的方式蒸镀AlN，并控制sputter的蒸镀制程温度(<500度)，避免造成基板翘曲与和过渡基板剥离的问题；蒸镀的AlN基板厚度需在80um以上(较佳为100um以上)，厚度越高，最终产品的强度越高，翘曲越低。
5)消除第二Si基板，暴露出氮化物半导体膜层的表面；先将第二Si基板研磨减薄到100um，再使用常见的Si蚀刻液以化学蚀刻方式移除第二Si基板。采用两步主要是为了加速移除Si基板过程，并减少长时间的化学蚀刻同时对模板其他部分造成的损害。
6)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层，由于此时衬底是氮化铝，其与氮化物半导体薄膜间的热膨胀系数差异远比Si小故，即可得到较厚无裂纹的高质量且翘曲较小的氮化物半导体膜层。
采用Si基板作为初始的长晶基板，Si基板成本低，且相对sapphire(蓝宝石)与SiC其较容易取得大尺寸的基板，故能成长大面积与低成本的高质量氮化物半导体膜层，最终得到以AlN基板为衬底的高质量氮化物半导体膜层，使用此模板成长LED外延结构或FET外延结构可以避免传统上使用Si基板成长高质量氮化物半导体膜层容易发生裂纹和翘曲的问题。且使用此模板可以得到较厚的无裂纹外延层，对氮化物LED来说可以减少向上延伸的穿隧式差排数目并增加N型半导体层的厚度以得到更低的操作电压、更好的电流扩散、更高的发光效率与更佳的可靠度。对FET组件来说可以增加底部缓冲层的厚度与降低漏电流的发生并达到更高的崩溃电压。
使用两个过镀基板目的是为了最终能得到Ga面的氮化物半导体膜层，Ga面的半导体膜层较利于LED制程中N-type的奥姆接触，能得到较低的电阻与较佳的热稳定性。
实施例三
一种上述的半导体模板的制作方式，包括以下步骤：
1)利用MOCVD方式在Si基板上成长小于临近厚度(如3um)高质量表面无裂纹的氮化物半导体膜层；临界厚度是指氮化物半导体膜在基板上成长时容易有裂纹和翘曲的问题产生时的厚度，根据基板类型和尺寸会有所不同。其包含以下步骤：
a、将Si基板在H2的气氛下加热到1100度5min以去除Si基板上的氧化物。
b、降低温度到1080度并控制反应室压力在100torr，通入TMA(三甲基铝)和NH3，成长氮化铝缓冲层100nm。
c、再通入TMG(三甲基镓)成长氮化铝镓应力控制层。
d、关掉TMA和TMG，改变成长温度到1050度并控制反应室压力在200torr，后打开TMG成长氮化镓3um。
e、关掉TMA和TMG维持现有NH3的状况下降温并得到无裂纹的高质量氮化镓半导体薄膜。
2)利用PVD(物理气相沉积)方式在芯片表面温度500度以下的温度沉积氮化铝基板在氮化物半导体膜层表面上，具体地，利用sputter(溅镀)的方式蒸镀AlN，并控制sputter的蒸镀制程温度(<500度)，避免造成基板翘曲与和过渡基板剥离的问题。AlN基板厚度需在80um以上(较佳为100um以上)，厚度越高，最终产品的强度越高，翘曲越低。AlN基板作为最终承载基板。
3)消除Si基板，暴露出氮化物半导体膜层的表面；消除Si基板分为两步：将Si基板研磨减薄到100um，再使用Si蚀刻液以化学蚀刻方式移除。采用两步主要是为了加速移除Si基板过程，并减少长时间的化学蚀刻同时对模板其他部分造成的损害。
4)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层，由于此时衬底是氮化铝，其与氮化物半导体薄膜间的热膨胀系数差异远比Si小故，即可得到较厚无裂纹的高质量且翘曲较小的N-Face氮化物半导体膜层。
采用Si基板作为过渡基板，Si基板成本低，并能成长大面积的高质量氮化物半导体膜层，最终得到以AlN基板为衬底的高质量氮化物半导体膜层，解决了Si基板成长高质量氮化物半导体膜层容易发生裂纹和翘曲的问题。
本实施例与实施例二的区别是只使用一个过渡基板，省略使用第二Si基板来将氮化物半导体膜层翻回Ga面的过程，最终会得到的是N面的氮化物半导体膜层在氮化铝基板上，可使用此模版来制作N面GaN(AlGaN)FET组件或是N面氮化物LED。N-face的氮化镓(氮化铝镓)HEMT组件相较于传统的G-Face氮化镓(氮化铝镓)HEMT组件理论上有更高的电子迁移率、更好的2DEG限域性、更低的奥姆电极接触，并更容易实现增强型的HEMT。
实施例二和实施例三最终得到的是高质量氮化物半导体膜层的两面，氮化物半导体膜层的两面是Ga面和N面，因此能得到两种表面的氮化物半导体膜层，以满足不同的使用需求。
实施例四
一种LED或FET组件，采用上述的半导体模板制作而成。
采用上述的方案后，能够得到大面积、较厚、高质量且无翘曲的氮化物半导体模板，并且制作过程方便，成本低。
上面对本发明进行了示例性描述，显然本发明具体实现并不受上述方式的限制，只要采用了本发明的方法构思和技术方案进行的各种非实质性的改进，或未经改进将本发明的构思和技术方案直接应用于其它场合的，均在本发明的保护范围之内。

Claims (10)

1.一种半导体模板，其特征在于，包括AlN基板，并设有氮化物半导体膜层形成于所述AlN基板上。
2.如权利要求1所述的半导体模板，其特征在于，所述氮化物半导体膜层为Al(x)Ga(1-x)N系材料，0<＝x<＝1。
3.一种如权利要求1或2所述的半导体模板的制作方式，其特征在于，包括以下步骤：
1)在过渡基板上成长小于临近厚度的氮化物半导体膜层；
2)在氮化物半导体膜层表面镀AlN基板；
3)消除过渡基板，暴露出氮化物半导体膜层的表面；
4)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层。
4.如权利要求3所述的半导体模板的制作方式，其特征在于，所述过渡基板为硅、蓝宝石或碳化硅基板。
5.如权利要求3所述的半导体模板的制作方式，其特征在于，所述AlN基板厚度在80um以上。
6.如权利要求3所述的半导体模板的制作方式，其特征在于，所述过渡基板为Si基板，消除Si基板分为两步：将Si基板研磨减薄到100um，再使用Si蚀刻液以化学蚀刻方式移除。
7.一种如权利要求1或2所述的半导体模板的制作方式，其特征在于，包括以下步骤：
1)在第一过渡基板上成长小于临近厚度的氮化物半导体膜层；
2)将氮化物半导体膜层固定在第二过渡基板上；
3)消除第一过渡基板，暴露出氮化物半导体膜层的表面；
4)在暴露出的氮化物半导体膜层的表面镀AlN基板；
5)消除第二过渡基板，暴露出氮化物半导体膜层的表面；
6)在暴露出的氮化物半导体膜层的表面进行二次成长氮化物半导体膜层。
8.如权利要求7所述的半导体模板的制作方式，其特征在于，所述第一过渡基板为硅、蓝宝石或碳化硅基板，第二过渡基板Si基板或电镀基板。
9.如权利要求7所述的半导体模板的制作方式，其特征在于，所述AlN基板厚度在80um以上。
10.一种LED或FET组件，其特征在于，具有如权利要求1-9任一所述的半导体模板。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131701A (ja) * 1997-07-11 1999-02-02 Sumitomo Electric Ind Ltd 化合物半導体装置の形成方法
US20070020788A1 (en) * 2005-07-12 2007-01-25 Jin-Hsiang Liu Fabrication method of high-brightness light emitting diode having reflective layer
CN101918624A (zh) * 2008-01-16 2010-12-15 国立大学法人东京农工大学 具有a1系ⅲ族氮化物单晶层的层叠体的制造方法、通过该制法制得的层叠体、使用该层叠体的a1系ⅲ族氮化物单晶基板的制造方法及氮化铝单晶基板
CN102592999A (zh) * 2012-03-19 2012-07-18 中国科学院上海技术物理研究所 一种优化量子阱hemt器件沟道层厚度的方法
US20120211801A1 (en) * 2009-08-28 2012-08-23 Sumitomo Electric Industries, Ltd. Group iii nitride laminated semiconductor wafer and group iii nitride semiconductor device
CN102916044A (zh) * 2011-08-01 2013-02-06 三星电子株式会社 高电子迁移率晶体管及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131701A (ja) * 1997-07-11 1999-02-02 Sumitomo Electric Ind Ltd 化合物半導体装置の形成方法
US20070020788A1 (en) * 2005-07-12 2007-01-25 Jin-Hsiang Liu Fabrication method of high-brightness light emitting diode having reflective layer
CN101918624A (zh) * 2008-01-16 2010-12-15 国立大学法人东京农工大学 具有a1系ⅲ族氮化物单晶层的层叠体的制造方法、通过该制法制得的层叠体、使用该层叠体的a1系ⅲ族氮化物单晶基板的制造方法及氮化铝单晶基板
US20120211801A1 (en) * 2009-08-28 2012-08-23 Sumitomo Electric Industries, Ltd. Group iii nitride laminated semiconductor wafer and group iii nitride semiconductor device
CN102916044A (zh) * 2011-08-01 2013-02-06 三星电子株式会社 高电子迁移率晶体管及其制造方法
CN102592999A (zh) * 2012-03-19 2012-07-18 中国科学院上海技术物理研究所 一种优化量子阱hemt器件沟道层厚度的方法

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