CN104157656A - Array substrate and preparation method thereof, and display device - Google Patents
Array substrate and preparation method thereof, and display device Download PDFInfo
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- CN104157656A CN104157656A CN201410367104.6A CN201410367104A CN104157656A CN 104157656 A CN104157656 A CN 104157656A CN 201410367104 A CN201410367104 A CN 201410367104A CN 104157656 A CN104157656 A CN 104157656A
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- electrode layer
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- pixel electrode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
The invention relates to the technical field of display devices and discloses an array substrate and a preparation method thereof, and a display device, wherein the array substrate is used for increasing the utilization ratio of a backlight source in the display device and simplifying preparation processes, and comprises a gate insulating layer, and an active layer, a pixel electrode layer, a plurality of solar cells distributed in the direction of a data line at intervals and connecting lines arranged between adjacent solar cells, which are positioned on the gate insulating layer, an insulating layer positioned on the pixel electrode layer, a source and drain electrode layer positioned on the insulating layer, a passivation layer positioned on the source and drain electrode layer and an electrode layer positioned on the passivation layer, wherein the connecting lines are used for connecting solar cells in series; the pixel electrode layer, connecting lines and the P-type semiconductors and N-type semiconductors of all solar cells are positioned on the same layer.
Description
Technical field
The present invention relates to display device technology field, particularly relate to preparation method and the display unit of a kind of array base palte, array base palte.
Background technology
Backlight is the chief component of display unit, and still, due to the impact of the factors such as display floater aperture opening ratio, raw material transmitance, the light that backlight sends only has small part energy transmission display panel, and a part will be sheltered from by black matrix".
In order effectively to utilize this part light being covered by black matrix", available technology adopting is integrated in the method on display floater by solar cell, so that this part power conversion is become to electric energy, but, in prior art, when solar cell is integrated on display floater, formed solar cell is the PN junction solar cell of upper and lower eclipsed form, although this structure also can effectively improve the utilance of backlight, structure and technique are all more complicated.
Summary of the invention
The invention provides a kind of array base palte and preparation method thereof, in order to improve the utilance of backlight in display unit, and simplified preparation technology.
In addition, the present invention also provides a kind of display unit, has higher backlight utilance.
For achieving the above object, the invention provides following technical scheme:
The invention provides a kind of array base palte, comprising:
Gate insulation layer;
Active layer on described gate insulation layer, pixel electrode layer, along data wire direction a plurality of solar cells spaced apart and be arranged at the connecting line between adjacent two solar cells, a plurality of described connecting lines are for described a plurality of solar cells are connected, and P type semiconductor, the N type semiconductor of described pixel electrode layer, a plurality of described connecting lines and each solar cell are positioned at same layer;
Be positioned at the insulating barrier on described pixel electrode layer;
Be positioned at source, drain electrode layer on described insulating barrier;
Be positioned at the passivation layer on described source, drain electrode layer;
And be positioned at the electrode layer on described passivation layer.
Array base palte provided by the invention, is combined solar cell with array base palte, the light that can effectively utilize backlight to be sheltered from by black matrix", and solar cell changes into electric energy by this part light; Simultaneously, because the P type semiconductor in solar cell and N type semiconductor are to arrange with layer, can save preparation technology.
So array base palte provided by the invention, can improve the efficiency of light energy utilization of backlight in display unit, and preparation technology is simple.
In some optional execution modes, described electrode layer is common electrode layer.
In some optional execution modes, the material of preparing of described active layer is amorphous silicon.
In some optional execution modes, the material of described pixel electrode layer is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
The present invention also provides a kind of preparation method of array base palte, comprising:
On gate insulation layer, form active layer;
A plurality of P type semiconductors and a plurality of N type semiconductor that formation distributes along data wire direction, and described a plurality of P type semiconductor and described a plurality of N type semiconductor be positioned at same layer, and a P type semiconductor and a N type semiconductor form solar cell;
By deposition and composition technique, form corresponding pattern and pattern corresponding to connecting line of pixel electrode, described connecting line is for connecting a plurality of solar cells;
On described pixel electrode, form insulating barrier;
Formation source, drain electrode layer on described insulating barrier;
On described source, drain electrode layer, form passivation layer;
On described passivation layer, form electrode layer.
In some optional execution modes, described step: form a plurality of P type semiconductors and a plurality of N type semiconductor that distribute along data wire direction, specifically comprise: form P shape semiconductor and N type semiconductor by semiconductor doping technique.
In some optional execution modes, the material of preparing of described active layer is amorphous silicon.
In some optional execution modes, the material of described pixel electrode is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
The present invention also provides a kind of display unit, comprising: backlight, also comprises: the array base palte described in above-mentioned any one.
Accompanying drawing explanation
The array base-plate structure schematic diagram that Fig. 1 provides for the embodiment of the present invention;
The array base palte preparation method flow chart that Fig. 2 provides for the embodiment of the present invention.
Accompanying drawing explanation
1-gate insulation layer 2-P type semiconductor
3-N type semiconductor 4-connecting line
5-insulating barrier 6-source, drain electrode layer
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only a part of embodiment of the present invention, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of patent protection of the present invention.
Embodiment mono-
As shown in Figure 1, Fig. 1, for the array base-plate structure schematic diagram that the embodiment of the present invention provides, the invention provides a kind of array base palte, comprising:
Gate insulation layer 1;
Active layer on gate insulation layer 1, pixel electrode layer, along data wire direction a plurality of solar cells spaced apart and be arranged at the connecting line 4 between adjacent two solar cells, a plurality of connecting lines 4 are for by the series connection of a plurality of solar cells, and the P type semiconductor 2 of pixel electrode layer, a plurality of connecting line 4 and each solar cell, N type semiconductor 3 are positioned at same layer;
Be positioned at the insulating barrier 5 on pixel electrode layer;
Be positioned at source, drain electrode layer 6 on insulating barrier;
Be positioned at the passivation layer on source, drain electrode layer 6;
And be positioned at the electrode layer on passivation layer.
Array base palte provided by the invention, is combined solar cell with array base palte, the light that can effectively utilize backlight to be sheltered from by black matrix", and solar cell changes into electric energy by this part light; Simultaneously, because the P type semiconductor in solar cell and N type semiconductor are to arrange with layer, can save preparation technology.
So array base palte provided by the invention, can improve the efficiency of light energy utilization of backlight in display unit, and preparation technology is simple.
Above-mentioned electrode layer is common electrode layer.The array base palte forming is mainly used in the display unit of ADS pattern.
For the ease of preparation, preferred, the material of preparing of active layer is amorphous silicon.
The material of pixel electrodes layer is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
Embodiment bis-
As shown in Figure 2, the array base palte preparation method flow chart that Fig. 2 provides for the embodiment of the present invention, the embodiment of the present invention provides a kind of preparation method of array base palte, comprising:
Step S101: form active layer on gate insulation layer;
Step S102: form a plurality of P type semiconductors and a plurality of N type semiconductor that distribute along data wire direction, and a plurality of P type semiconductor and a plurality of N type semiconductor be positioned at same layer, a P type semiconductor and a N type semiconductor form solar cell;
Step S103: form corresponding pattern and pattern corresponding to connecting line of pixel electrode by deposition and composition technique, connecting line is for connecting a plurality of solar cells; The material of connecting line forming is identical with the material of pixel electrode layer.
Step S104: form insulating barrier on pixel electrode;
Step S105: formation source, drain electrode layer on insulating barrier;
Step S106: form passivation layer on source, drain electrode layer;
Step S107: form electrode layer on passivation layer.
In above-mentioned preparation method, P type semiconductor and N type semiconductor are prepared in to same layer, have saved the step of preparing insulating barrier between P type semiconductor and N type semiconductor.Therefore simplified preparation technology.
In a kind of concrete execution mode, electrode layer is common electrode layer.
Further, in above-mentioned steps S102: form a plurality of P type semiconductors and a plurality of N type semiconductor that distribute along data wire direction, specifically comprise: form P shape semiconductor and N type semiconductor by semiconductor doping technique.Directly in active layer, by doping process, form P shape semiconductor and N type semiconductor.
In a kind of embodiment, the material of preparing of active layer is amorphous silicon.
The material of pixel electrodes is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
Embodiment tri-
The embodiment of the present invention provides a kind of display unit, comprising: backlight, also comprises: the array base palte as described in embodiment mono-.Due to the array base palte that the embodiment of the present invention one provides, improved the utilance of backlight in display unit, and simplified preparation technology.So the display unit that the embodiment of the present invention three provides, has higher backlight utilance.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte, is characterized in that, comprising:
Gate insulation layer;
Active layer on described gate insulation layer, pixel electrode layer, along data wire direction a plurality of solar cells spaced apart and be arranged at the connecting line between adjacent two solar cells, a plurality of described connecting lines are for described a plurality of solar cells are connected, and P type semiconductor, the N type semiconductor of described pixel electrode layer, a plurality of described connecting lines and each solar cell are positioned at same layer;
Be positioned at the insulating barrier on described pixel electrode layer;
Be positioned at source, drain electrode layer on described insulating barrier;
Be positioned at the passivation layer on described source, drain electrode layer;
And be positioned at the electrode layer on described passivation layer.
2. array base palte as claimed in claim 1, is characterized in that, described electrode layer is common electrode layer.
3. array base palte as claimed in claim 1, is characterized in that, the material of preparing of described active layer is amorphous silicon.
4. the array base palte as described in claim 1～3 any one, is characterized in that, the material of described pixel electrode layer is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
5. a preparation method for array base palte, is characterized in that, comprising:
On gate insulation layer, form active layer;
A plurality of P type semiconductors and a plurality of N type semiconductor that formation distributes along data wire direction, and described a plurality of P type semiconductor and described a plurality of N type semiconductor be positioned at same layer, and a P type semiconductor and a N type semiconductor form solar cell;
By deposition and composition technique, form corresponding pattern and pattern corresponding to connecting line of pixel electrode, described connecting line is for connecting a plurality of solar cells;
On described pixel electrode, form insulating barrier;
Formation source, drain electrode layer on described insulating barrier;
On described source, drain electrode layer, form passivation layer;
On described passivation layer, form electrode layer.
6. method as claimed in claim 5, is characterized in that, described electrode layer is common electrode layer.
7. method as claimed in claim 5, is characterized in that, described step: form a plurality of P type semiconductors and a plurality of N type semiconductor that along data wire direction, distribute, specifically comprise: by semiconductor doping technique, form P shape semiconductor and N type semiconductor.
8. method as claimed in claim 5, is characterized in that, the material of preparing of described active layer is amorphous silicon.
9. the method as described in claim 5～8 any one, is characterized in that, the material of described pixel electrode is the monofilm of ITO, IZO, or is the composite membrane that ITO, IZO form.
10. a display unit, comprising: backlight, it is characterized in that, and also comprise: the array base palte as described in claim 1～4 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410367104.6A CN104157656A (en) | 2014-07-29 | 2014-07-29 | Array substrate and preparation method thereof, and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410367104.6A CN104157656A (en) | 2014-07-29 | 2014-07-29 | Array substrate and preparation method thereof, and display device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886688A (en) * | 1995-06-02 | 1999-03-23 | National Semiconductor Corporation | Integrated solar panel and liquid crystal display for portable computer or the like |
| CN102723344A (en) * | 2012-06-12 | 2012-10-10 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, manufacture method of array substrate and liquid crystal display |
| CN102738080A (en) * | 2012-07-20 | 2012-10-17 | 深圳市华星光电技术有限公司 | Method for manufacturing array substrate with embedded photovoltaic cell |
| CN103018974A (en) * | 2012-11-30 | 2013-04-03 | 京东方科技集团股份有限公司 | Liquid crystal display device, polysilicon array substrate and manufacturing method |
-
2014
- 2014-07-29 CN CN201410367104.6A patent/CN104157656A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886688A (en) * | 1995-06-02 | 1999-03-23 | National Semiconductor Corporation | Integrated solar panel and liquid crystal display for portable computer or the like |
| CN102723344A (en) * | 2012-06-12 | 2012-10-10 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, manufacture method of array substrate and liquid crystal display |
| CN102738080A (en) * | 2012-07-20 | 2012-10-17 | 深圳市华星光电技术有限公司 | Method for manufacturing array substrate with embedded photovoltaic cell |
| CN103018974A (en) * | 2012-11-30 | 2013-04-03 | 京东方科技集团股份有限公司 | Liquid crystal display device, polysilicon array substrate and manufacturing method |
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Application publication date: 20141119 |