CN104156196B - Renaming preprocess method - Google Patents

Renaming preprocess method Download PDF

Info

Publication number
CN104156196B
CN104156196B CN201410419560.0A CN201410419560A CN104156196B CN 104156196 B CN104156196 B CN 104156196B CN 201410419560 A CN201410419560 A CN 201410419560A CN 104156196 B CN104156196 B CN 104156196B
Authority
CN
China
Prior art keywords
renaming
instruction
register
program
address code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410419560.0A
Other languages
Chinese (zh)
Other versions
CN104156196A (en
Inventor
龚伟峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Jubei Machinery Design Co ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201410419560.0A priority Critical patent/CN104156196B/en
Publication of CN104156196A publication Critical patent/CN104156196A/en
Application granted granted Critical
Publication of CN104156196B publication Critical patent/CN104156196B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Advance Control (AREA)

Abstract

One renaming preprocess method, comprises the following steps：First, another possible correct procedure in a branch point is determined.Then, another possible correct program, and one group of instruction for setting a temporal cache to supply storage decoding another possible correct procedure to be obtained are decoded.Then, carry out life again to group instruction to operate, then prefetched instruction caching is set for the instruction after storage again life operation.Then, one group of unit caches is set, and each unit caching corresponds to each execution unit respectively, for storing the corresponding instruction performed by the execution unit, wherein, instructing to the unit caches corresponding to the corresponding execution unit of the instruction of renaming for renaming stores for distribution.

Description

Renaming preprocess method
Technical field
The present invention relates to branch prediction method, more particularly to a kind of renaming preprocess method, by using the renaming Preprocess method, in advance may correctly cache another, to reduce instruction flow line line series, so that at raising in program deposit Manage device performance.
Background technology
In the prior art, processor is designed with caching (Cache).The purpose for setting caching is to allow data access The processing speed of velocity adaptive processor.The capacity of caching be much smaller than internal memory, but speed can close to processor frequency.When When processor sends memory access request, first check in caching whether there is request data.If there is request data (life in caching In), then directly obtain data from caching；, be first corresponding in internal memory if request data (failure) is not present in caching Data are loaded into caching, then return it into processor.
Register renaming be also improve processor performance a kind of technology, its object is to avoid machine instruction or The unnecessary ordered execution of microoperation, so as to improve processor disposal ability.Processor preserves instruction using register Operand and result.Different instructions can have the different execution times.For example, during the execution of the instruction of a rdma read Between, hundreds of other instructions are performed enough.Therefore, in the case where allowing a plurality of executing instructions, those IAes are suitable The instruction of sequence rearward, completes, is different from it in a program which forms instruction execution sequence earlier than reading internal memory instruction Sequentially.This Out-of-order execution is one of crucial method that high-performance processor improves arithmetic speed.But, processor can be used The quantity of register name be limited., can be in processing but many high-performance processors have many physical registers These register mappings it is different physical registers when device instruction pipeline is performed, so as to be provided in hardware level extra Parallel ability.
But, if a plurality of instruction has used same storage location, if these instructions are not held by program address order Row may result in 3 kinds of data hazards (data hazard)：Write-then-read (Read-after-write, RAW):From register Or the data read in internal memory, necessarily it is stored in before herein.Such case is that real data dependence is instructed in other words Stream is relied on.Must successively it be performed according to program order.First write after write
(Write-after-write, WAW)：It is continuously written into specific register or internal memory, then the storage location is final Only comprising the data write for the second time.This can cancel or abolish first time write operation.WAW correlations are also said to be " output It is related " (output dependencies).Write-after-read (Write-after-read, WAR)：Read operation obtain data be Write before this, rather than the hereafter result of write operation.Therefore this is a kind of spurious correlation (false dependency), Ke Yitong Renaming is crossed to solve.It need not wait and perform write operation again after the completion of all read operations, the two of this storage location can be kept Part copy：Old value and new value.Reading the operation that is worth always can proceed, after considering that those write new value or even write newly value Read the operation being newly worth.This spurious correlation is removed, and generates extra Out-of-order execution chance.When all old Value Operations of reading are satisfied Afterwards, register used in old value can both discharge.This is the essence of register renaming.
Branch predictor is also a technology for improving processor performance.It is using the purpose of branch predictor in branch Instruction execution guesses which branch will be performed before terminating, to improve instruction pipelining flow, so as to improve processing The performance of device.
Conditional branch instructions generally have two-way subsequent execution branch.(not taken) is not taken to redirect, continuation order Perform；And take (taken) to jump to the instruction that another piece of program internal memory goes to execution there.Whether conditional jump, only exist The branch instruction has passed through the execution stage (execution stage) in instruction pipeline can just decide.If no Branch predictor, processor will wait branch instruction to pass through the execution stage of instruction pipeline, and just next instruction is sent Enter first stage-instruction fetch phase (fetch stage) of streamline.This technology is called pipeline stall (stream stalled).This is the method for the streamline execution for the reply branch instruction that early stage processor is used.
Which is most likely to occur in branch predictor conjecture two-way branch, then speculates to perform this instruction all the way, comes The time for avoiding pipeline stall from causing wastes.If finding branch misprediction later, then speculate what is performed in streamline Those intermediate results are all abandoned, and are re-fetched the instruction on correct branch's route and are started execution, are held so as to cause program Capable delay.The time wasted when branch prediction fails is from instruction fetch to having performed instruction (but without write-back result) The series of streamline.Modern processors tend to using very long streamline, therefore branch prediction failure may pay very big Cost, if wherein.Longer streamline is accomplished by better branch prediction.Branch prediction techniques mainly have static prediction technology and The major class of dynamic prediction technology two.No matter static prediction technology or dynamic prediction technology are all to speculate to perform to instruct all the way, and to another Instruction needs just to perform after confirming the road instruction errors being carrying out all the way.But perform the instruction of another road may be related to from The operation for evidence of being fetched in internal memory.Once occur needing evidence of fetching from internal memory.If the instruction of another road is previously charged into caching, when After the confirmation command mistake being carrying out, another road instruction is performed.But, in existing branch prediction techniques and in the absence of such Technology.
The content of the invention
For defect of the prior art, it is an object of the invention to provide a kind of renaming preprocess method.
A kind of renaming preprocess method provided according to the present invention, comprises the following steps：
(A) another possible correct program in a branch point is determined；
(B) decode it is described another may correct program, and set a temporal cache for storage decoding it is described another One group of instruction that possible correct program is obtained；
(C) register renaming operation is carried out, sets a prefetched instruction to cache for the instruction after storage again life operation； Wherein, the step (C) further comprises the steps：(C.1)：Operation note position is true in selected source operand address code Recognize position；
(C.2)：Judge that the branch point whether there is into the program for not including selected instruction between selected instruction to select The related destination operand address code in operation note position；
If there is the operation deposit selected in the branch point to the program for not including selected instruction between selected instruction The related destination operand address code in device position, then exist in the branch point to the program for not including selected instruction between selected instruction The related destination operand address code in each operation note selected position in arrange that last operation select and deposit The related destination operand address code in device position is known as operation note position and confirms destination operand address code, into step (C.3),
If the operation selected is not present in the branch point to the program for not including selected instruction between selected instruction to post The related destination operand address code in storage position, into step (C.4)；
(C.3)：Destination operand address code, which carries out renaming, i.e. destination register weight, to be confirmed to operation note position Operation note position is named to confirm that institute is more in renaming for the operation note contained among destination operand address code position Positive operation, the operation just corrected as operation note position, into step (C.7)；
(C.4)：Judge in the program before the branch point with the presence or absence of the related purpose operation in operation note position selected Number address code,
If there is the related destination operand address code in operation note position selected in the program before the branch point, Arranged most in the related destination operand address code in operation note position that each is selected present in program before the branch point The related destination operand address code in operation note position that afterwards that is selected is referred to as operation note position and confirms purpose operation Number address code, into step (C.5),
If the related destination operand address code in operation note position selected is not present in the program before the branch point, Into step (C.6)；
(C.5)：Destination operand address code, which carries out renaming, i.e. destination register weight, to be confirmed to operation note position Name, operation note position confirms that institute is more in renaming for the operation note contained among destination operand address code position Positive operation, the operation just corrected as operation note position, into step (C.7)；
(C.6)：The behaviour of selected operation note position in the source operand address code of a selected non-renaming Make, with regard to carrying out reservation origin operation；
(C.7)：The register operated after the operation note bit manipulation corrigendum in selected source operand address code Operation is corrected name corresponding to operated register as selected source operand address Code memory name renaming institute more The register name for the renaming for being just；
(D) one group of execution unit is set to cache, each execution unit caching corresponds to each execution unit respectively, so that storage is described Corresponding instruction performed by execution unit, wherein, instructing to corresponding with the instruction of renaming for renaming is held for distribution Execution unit buffer memory corresponding to row unit, to improve the execution efficiency of execution unit；
(E) fetching is carried out to the instruction through renaming.
Further, the step (E) further comprises the steps：
(E.1) a correct branched program of the branch point to be processed is confirmed；
(E.2) judge the correct branched program whether the branched program with the configuration processor of the branch point to be processed It is identical, if the correct branched program and the branch of the configuration processor of the branch point to be processed are identicals, it is determined that The branched program removed from the branch point to be processed is correct, step (E.3) is then performed, if correct branch's journey Sequence is different from the configuration processor branch of the branch point to be processed, it is determined that removed from the branch point to be processed Branched program is wrong, then performs step (E.5.)；
(E.3) judge whether stored to be processed described in prefetched instruction caching and execution unit caching The branch instruction that branch point is removed, if being stored in prefetched instruction caching and execution unit caching from handling The branch instruction removed of the branch point, then perform step (E.4)；
(E.4) branch instruction removed from the branch point to be processed is deleted；
(E.5) judge whether stored to be processed described in prefetched instruction caching and execution unit caching The branch instruction that branch point is removed, if being stored in prefetched instruction caching and execution unit caching from handling The branch instruction removed of the branch point, then step (E.6) is performed, if in prefetched instruction caching and described performing list The branch instruction removed from the branch point to be processed is not stored in member caching, step (E.7) is performed；
(E.6) the corresponding branched program removed from the branch point to be processed of the branch instruction is removed to make From the branched program that the branch point to be performed is removed is determined, after the branched program to be performed is removed, to incite somebody to action described Prefetched instruction is cached and the branch removed from the branch point to be processed having in execution unit caching Instruction is deleted；With
(E.7) without operation.
Further, the step (A) further comprises the steps：
(A.1) Branch Processing Unit and an at least recording unit are set；
(A.2) an at least subrecord unit is distributed in the recording unit, for recording the use under the branch point Branched program state；
(A.3) by handling the subrecord cell data, judge conventional branched program, the branched program being of little use and The branched program that pole is of little use, if branched program is conventional branched program, performs step (A.4), if branched program is not Conventional branched program, then perform step (A.5), if branched program is the branched program that pole is of little use, performs step (A.6)；
(A.4) the conventional branched program deposit caching that will be judged by performing in step (A.3)；
(A.5) branched program that is of little use judged by performing in step (A.3) is removed；With
(A.6) remove and be of little use branched program by performing the pole judged in step (A.3), and cancel corresponding The subrecord unit.
Further, the operation of the register in destination operand address code corresponding to the register name of non-renaming is posted Storage position is the register name of non-renaming in the non-renaming register-bit of destination operand address code, destination operand address code Corresponding register is the non-renaming register of destination operand address code, wherein, the non-renaming of destination operand address code Register mappings among register section occupied by register-bit to the non-renaming register of destination operand address code The operation note position the same position sequence number of position serial number destination operand address code renaming register-bit occupied by Among register among register section.
Preferably, when the address code that the branch point removes the instruction of another possible correct program is that source is grasped Make number address code or destination operand address code, then the register of the corresponding non-renaming register name of the address code instructed exists Instruct the Register renaming map table quoted to map out the name corresponding to the register come, be used as the address code of instruction The register name for the renaming that register name renaming is corrected as.
Preferably, the branch point removes first instruction correspondence register of another possible correct program Renaming mapping table is used for the branch point in the corresponding Register renaming map table of first instruction of configuration processor Hold the corresponding Register renaming map table for first instruction that another possible correct program is removed as the branch point Content, i.e., described branch point remove another may correct program first instruction corresponding Register renaming map Table just completes reference.
Preferably, when the address code in the configuration processor for being not applied to be not carried out in the register name of renaming In, then the register name of selected part among the register name of renaming is cancelled to the configuration processor distributed to and be not carried out, then Distributing to another correctly program may use, and carry out another possible correct program renaming, and among renaming The destination operand address code of each non-renaming distributes the register name for the renaming that a possible correct program is used,
Wherein, each the register name of the renaming of the destination operand address code distribution of non-renaming is different.
Preferably, when another possibility, correctly program is conditional branching program, then will be in the conditional branching The address information that program is added in the corresponding prefetched instruction caching come out according to the address computation of the condition；
After condition is performed, the location of instruction found according to the address information in corresponding prefetched instruction caching carries out pre- Take.
Compared with prior art, the present invention has following beneficial effect：
, in advance may to another while most possible correct branched program is performed in branch prediction is carried out Correct program is handled.And result is stored in caching, and the guide to result is provided, so that ought be most When being possible to correct branched program and being identified mistake, according to guide help to find another may correct program processing knot Really.And then the energy of the loss that is caused due to branch misprediction of microprocessor and waste is reduced, improve the place of microprocessor Efficiency is managed, energy is saved in help.Renaming preprocess method of the present invention is cached there is provided one group of execution unit, and the execution unit delays Deposit each execution unit to correspond, reduce the addressing time of each execution unit, improve the efficiency of execution unit.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, further feature of the invention, Objects and advantages will become more apparent upon：
Fig. 1 is the flow chart of the preferred embodiment according to renaming preprocess method of the present invention；
Fig. 2 is the flow chart operated according to the renaming of a preferred embodiment of renaming preprocess method of the present invention；
Fig. 3 is the stream of a renaming instruction fetch method of the preferred embodiment according to renaming preprocess method of the present invention Cheng Tu；
Fig. 4 is to be changed according to the Register renaming map table of a preferred embodiment of renaming preprocess method of the present invention Schematic diagram.
Embodiment
According to the claim and specification disclosure of that of the present invention, technical scheme literary institute specific as follows State.
As shown in figure 1, renaming preprocess method of the present invention includes step 1001：Determine that another may correct journey Sequence.Multiple branched programs are taken in a branch point of a program.Through branch prediction, will most possibly correct branched program at this Instruction fetch on branch point, and load execution.Then when the correct branch of the branch point does not confirm, possible branch's journey is determined Sequence.Specifically, when the correct branch of the branch point does not confirm, it is responsible for indicating that this branch clicks by analyzing the branch point With the branched program indicated by branched program, or by analyzing making recorded in the branched program usage record of branch instruction Used branched program, so that it is determined that the possibility branched program that the branch point has.It is noted that due to most possibly just True branched program is used to carry out, so the possible branched program does not include the most possible branched program.Then, Instruction fetch is carried out to one of them possible branched program or multiple possible branched programs in the branch point, and by fetched instruction Branched program deposit caching.It is worth mentioning, each possible branched program can be analyzed, predicts each possible branch's journey Sequence takes possibility.Possibility is taken according to possible branched program, it is determined that than the branched program that may be performed, so Instruction fetch is carried out to the more possible branched program afterwards, then the branched program of fetched instruction is stored in caching.Finally, take and work as In it is multiple may but the uncertain programs performed, will be removed from branch point and be stored in the application definition of caching may be just for another True program.If another may correct program from branch point remove and be stored in after caching again from branch point remove after by with In execution, be also defined as another may correct program it is noted that access highest branched program, and compare and have Possible branched program is all suitable for renaming preprocess method of the present invention.It is noted that setting a decoded instruction to cache For storing decoded instruction.The instruction fetch of another possible correct program may be derived from one of caching in processor, Decoded instruction caching can also be derived from.
It is noted that renaming preprocess method of the present invention is available for setting a Branch Processing Unit and an at least record Unit, with the state according to each branched program, conventional branched program is stored in and cached.The Branch Processing Unit can be according to branch The state of program sets the corresponding recording unit, and the Branch Processing Unit distributes an at least subrecord in the recording unit Unit.The subrecord unit supplies the used branched program of record same case, and subrecord unit correspondence is mutually being sympathized with The next used branched program of condition.One, the data of the branched program were used so that record is corresponding.The Branch Processing Unit The data of each subrecord unit of the corresponding recording unit of the branched program are read respectively, and are handled, to determine in phase The most frequently used with the case of and/or recently the most frequently used branched program, conventional and/or conventional recently branched program, it is of little use And/or the branched program that the branched program being of little use recently and pole are of little use and/or most proximal pole is of little use.Will be conventional and/or most Closely conventional branched program deposit caching, or the deposit caching when taking the conventional branched program.Decoded instruction is cached In this be of little use and/or branched program for being of little use recently is removed.Pole is of little use and/or branch's journey that most proximal pole is of little use The corresponding subrecord unit of branched program that pole is of little use and/or most proximal pole is of little use is removed and cancelled to sequence.
The cache algorithm invented is given tacit consent in social existing invention in the world for example to be had " LRU " (LRU), " least conventional page replacement algorithm recently " (LFU), fifo algorithm (FIFO).
For example, the operation to correcting branched program, a recording unit, which can be set, is used to record what refitting in an execution loaded First used branched program.Specifically, the Branch Processing Unit is first that refitting loads in the recording unit Used branched program distributes corresponding subrecord unit respectively in branch, for recording making for the corresponding branched program Use situation data.Preferably, the access times of the subrecord unit record branched program corresponding with the subrecord unit and/ Or frequency of use and/or nearest service condition and recently when service condition.When predicted in execution it is wrong after, the branch process Whether first branched program taken that element analysis refitting loads is assigned with what is taken with this first in the recording unit The corresponding subrecord unit of branched program.If the subrecord unit is the allocated, the data in the subrecord unit are entered Row modification.Preferably, the number of times data modification in the subrecord unit it used and/or nearest service condition and/or Recently when service condition.If the subrecord unit is not distributed, distribute a subrecord unit and taken for recording this first The data of branched program, and the data of the subrecord unit are modified.Preferably, by the data of the subrecord unit It is modified to the record for having used once and/or having increased when nearest usage record and/or increase use recently.The processing unit is read The data of the corresponding subrecord unit of each branched program are taken, are then given tacit consent to by social existing invention in the world The cache algorithm invented is (for example：LRU) data to the respectively subrecord unit are handled, to determine respectively should for refitting loading Commonly used in branched program and/or branched program conventional recently.Specifically, the Branch Processing Unit by analyzing, compare and Each subelement recorded data of computing, it is determined that in the respectively branched program being fitted into commonly use the branched program, be of little use And/or the branched program that the branched program being of little use recently and pole are of little use and/or most proximal pole is of little use.Then this is commonly used And/or decoded after the first instruction fetch of correction branched program conventional recently, then the conventional and/or conventional recently correction branch In the decoded instruction deposit decoded instruction caching of program.Or taken in the conventional and/or correction branched program conventional recently Used time, the conventional and/or correction branched program conventional recently obtains the conventional and/or conventional recently correction point after being decoded After Zhi Chengxu decoded instruction, the decoded instruction deposit of the conventional and/or conventional recently correction branched program has been solved In code instruction caching.And will be of little use and/or the correction branch that is of little use recently removes from caching, and pole is of little use and/or most Proximal pole be of little use correction branch then from caching remove and its corresponding subrecord unit is also cancelled into distribution.
Another recording unit, which can be set, to be used to record the Article 2 branched program for resetting loading in an execution.Specifically Say, the Article 2 branched program used branched program point that the Branch Processing Unit loads in another recording unit for refitting With corresponding subrecord unit for the data of the branched program corresponding to record.Preferably, the subrecord unit record with The access times and/or frequency of use of the corresponding branched program of subrecord unit and/or nearest service condition and recently what When service condition.When predicted in execution it is wrong after, the branch that takes of Article 2 that Branch Processing Unit analysis refitting loads Program is in the corresponding subrecord unit of the branched program that whether recording unit is assigned with the Article 2 is taken.If the son Recording unit is the allocated, then the data in the subrecord unit is modified.Preferably, by the number in the subrecord unit According to be revised as it using number of times and/or nearest service condition and/or recently when service condition.If the subrecord unit does not have Distribution, then distribute a subrecord unit to record the data for the branched program that the Article 2 is taken, and by the subrecord unit Data be modified.Preferably, the data correction of the subrecord unit is used into note recently to have used once and/or having increased The record when record and/or increase use recently.The processing unit reads the corresponding subrecord unit of each branched program Data, then with cache algorithm of the prior art (for example：LRU) data to the respectively subrecord unit are handled, with true Commonly used in fixed respectively branched program being fitted into and/or branched program conventional recently.Specifically, the Branch Processing Unit By analyzing, comparing and each subelement recorded data of computing, it is determined that commonly used in the respectively branched program being fitted into and/or The conventional recently branched program, the branched program for being of little use and/or being of little use recently and pole be of little use and/or most proximal pole seldom Branched program.Then it will be decoded after the first instruction fetch of conventional and/or conventional recently correction branched program, it is then that this is normal With and/or the decoded instruction deposit decoded instruction caching of conventional recently correction branched program in, or this it is conventional and/or After conventional correction branched program is decoded after taking recently at that time, by the conventional and/or conventional recently correction branch journey In the decoded instruction deposit decoded instruction caching of sequence.And will be of little use and/or be of little use correction branch recently from caching Remove, and pole is of little use and/or most proximal pole is of little use corrects branch and then removed and by its corresponding subrecord list from caching Member also cancels distribution.The Branch Processing Unit can be used for the branched program prefetched to non-executing record to operate.
A settable recording unit prefetches branched program for recording the non-executing, and the Branch Processing Unit is in the record Branched program is prefetched to each non-executing in unit and distributes corresponding subrecord unit respectively, for recording the corresponding non-executing Prefetch the data of branched program.Preferably, record the non-executing prefetch branched program access times and/or frequency of use and/ Or recently service condition and recently when the data of service condition.When prefetching a branched program in non-executing mode, the bifurcation Whether the reason element analysis recording unit is that the non-executing mode prefetches the corresponding subrecord unit of branched program distribution.If, The corresponding subrecord unit has been distributed, then the data of the corresponding subrecord unit be modified the number of times that it uses and/ Or recently service condition and/or recently when service condition.If the corresponding subrecord unit is not distributed, then the processing list Corresponding subrecord unit of branch's distribution that member is prefetched in the recording unit for the non-executing.Then by the subrecord unit Recorded data is modified.Preferably, the subrecord unit recorded data is modified to and has used once and/or increased Plus usage record and/or the record that when uses recently recently.The Branch Processing Unit reads each non-executing and prefetches branched program Corresponding respectively subrecord unit, is then handled, with determine those be non-executing prefetch conventional in branched program and/or Branch is commonly used recently.Specifically, the Branch Processing Unit gives tacit consent to what is invented by social existing invention in the world Cache algorithm is (for example：LRU) data to the respectively subrecord unit are analyzed, compared and computing, are determined the most frequently used and/or most Nearly the most frequently used non-executing prefetches branched program, conventional and/or non-executing conventional recently prefetches branched program, be of little use and/ Or the non-executing that is of little use recently prefetches branched program and pole is of little use and/or the most proximal pole non-executing that is of little use prefetches branched program. Decoded after the non-executing that is conventional and/or commonly using recently is prefetched into the first instruction fetch of branched program, then conventional and/or normal recently The non-executing prefetches the decoded instruction deposit decoded instruction caching of branched program, or one of them delays within a processor Deposit and take conventional and/or non-executing conventional recently and prefetch after being decoded after branched program at that time, will be conventional and/or most Closely the conventional non-executing prefetches the decoded instruction deposit decoded instruction caching of branched program.It will be of little use and/or recently The non-executing being of little use prefetches branched program and removed from caching.Pole is of little use and/or most proximal pole is of little use that this non-is held The non-executing that the capable instruction for prefetching branched program is then removed from caching and cancellation pole is of little use and/or most proximal pole is of little use is pre- Take the corresponding subrecord unit of branched program.
If it is noted that this another may have branched program in correct program, can be by using manufacture weight The same branch records and predicts instruction come true with same branch prediction method when another possible correct program is performed after dress Recognize the branched program having for another the possible correct program for needing instruction fetch, then by its instruction fetch, finally entered Row renaming preprocess method of the present invention.Or this another may correct program the branched program having refer to it is many using taking Individual possible branched program, is then carried out renaming preprocess method of the present invention.
Renaming preprocess method of the present invention further comprises step 1002：First decoding this, another may correct journey Sequence, obtains decoded instruction before one group of instruction, but instruction fetch and uses the decoding for keeping former instruction, and set temporal cache confession Store group instruction.It is worth mentioning, group instruction includes not solving code instruction and decoded instruction, and decoded instruction need not be entered Row decoding operate.It is noted that group instruction is stored into this according to the position of instruction input, sequence and time after refitting The corresponding position in temporal cache.Renaming preprocess method of the present invention further comprises step 1003：Group instruction is posted Storage renaming is operated.Then, then step 1005 is performed：Set a prefetched instruction to cache, register renaming will have been carried out Instruction is stored in prefetched instruction caching.Renaming preprocess method of the present invention further comprises step 1006：One group is set to hold Row unit caches, execution unit caching one execution unit of correspondence.Each execution unit performs corresponding instruction type.First Judge each instruction of renaming instruction type, then by the instruction of renaming send to described in renaming The execution unit corresponding to the corresponding execution unit is instructed to be stored in caching, to improve the execution efficiency of the execution unit. It is noted that in step 1005, can be to having performed the instruction after renaming operation after renaming operation has been performed Reordered, then be stored in prefetched instruction caching.Further judge the instruction of each renamed instructions reordered Type, the renamed instructions that then will reorder send corresponding to the instruction reordered with renaming Stored in execution unit caching corresponding to the execution unit.
As shown in Fig. 2 the register renaming operation mentioned by step 1003, is specifically included：
Step 2001：Operation note position acknowledgement bit (bit addressing) in selected source operand address code.Grasped in address code Make register operation (register addressing) be divided into do not operate only a position and also between the position that operates be different each The operation (bit addressing) of operation note position.
It may select an instruction in correct program this another, and one is selected not in a formerly fixed instruction The source operand address code of renaming, and the behaviour of operation note in the source operand address code of a selected non-renaming Make (register addressing) be divided into do not operate only a position and also between the position that operates be different each operation note positions Operate (bit addressing), and the operation (bit addressing) of central operation note position is referred to as the operation of operation note position, and in choosing Selected in the operation (bit addressing) for each operation note position being divided into the source operand address code of a fixed non-renaming The operation of the operation (bit addressing), referred to as selected operation note of fixed operation note position.The selected operation is posted Position operated by the operation of storage position, is referred to as the acknowledgement bit of the selected operation note position.
If occurring the confirmation for operating the selected operation note position in the destination operand address code of non-renaming Position (bit addressing), then this destination operand address code be referred to as select operation note position correlation destination operand address Code.If the acknowledgement bit for operating selected operation note position occurs in the operation of operation note position, it is referred to as selecting The associative operation register-bit operation of operation note position.
The arrangement of address code is sequential, order of the instruction in its corresponding programme where address code, just as address code Order.The arrangement of address code is to be arranged by the order of its address code after arriving first in a program.
Step 2002：Judge the branch point into the program for not including selected instruction between selected instruction with the presence or absence of selected The fixed related destination operand address code in operation note position.
If there is the operation deposit selected in the branch point to the program for not including selected instruction between selected instruction The related destination operand address code in device position, then exist in the branch point to the program for not including selected instruction between selected instruction The related destination operand address code in each operation note selected position in arrange that last operation select and deposit The related destination operand address code in device position is known as operation note position and confirms destination operand address code, into step 2003.
If the operation selected is not present in the branch point to the program for not including selected instruction between selected instruction to post The related destination operand address code in storage position, into step 2004.
Step 2003：Confirm that destination operand address code carries out renaming, i.e. purpose and deposited to operation note position Think highly of name.Inquiry operation register-bit confirms the operation (register addressing) of operation note among destination operand address code Be divided into do not operate only a position and also between the position that operates be different each operation note positions operation (bit addressing), Position operated by the operation of the operated position of its central operation operation note selected with this is that identical that operation is posted The operation of storage position, the operation of operated position is confirmed in operation note position after being corrected in the renaming of destination address code The operated position (bit addressing) for being, being just corrected the rear operated position for being as the operation of the selected operation note position, (position is sought Location).
Step 2004：Judge in the program before the branch point with the presence or absence of the related purpose behaviour in operation note position selected Make number address code.
If there is the related destination operand address code in operation note position selected in the program before the branch point, Arranged most in the related destination operand address code in operation note position that each is selected present in program before the branch point The related destination operand address code in operation note position that afterwards that is selected is known as destination address code and is referred to as operation deposit Device position confirms destination operand address code, into step 2005.
If the related destination operand address code in operation note position selected is not present in the program before the branch point, Into step 2006.
Step 2005：Confirm that destination operand address code carries out renaming, i.e. purpose and deposited to operation note position Think highly of name.Inquiry operation register-bit confirms that the operation (register addressing) of operation note among destination address code is divided into Do not operate only a position and also between the position that operates be different each operation note positions operation (bit addressing), it is central its Position operated by the operation of the operated position of the operation operation note position selected with this is that operation note of identical position Operation (bit addressing), the operation of operated position confirms to be corrected in the renaming of destination address code in operation note position The operated position (bit addressing) for being, is just corrected the rear operated position for being as the operation of the selected operation note position afterwards (bit addressing).
Step 2006：Selected operation note position in the source operand address code of a selected non-renaming Operation, with regard to carrying out reservation origin operation.
It is noted that the operation of the register operated in source operand address code is divided into each operation note By above-mentioned corrigendum step 2001, step 2002 or step 2003 or step 2004 or step 2005 or step after the operation of position After 2006 corrigendums, the operation of the register operated in source operand address code is corrected corresponding to the rear operated register for being Name, the register name for the renaming being just corrected as source operand address Code memory renaming.
It is noted that the register name of the revised address code of the register name of address code is to be incorporated into address code deposit Among device name.Program point is exactly the program corresponding points of some location of instruction in program.
Refer to invent it is noted that the renaming algorithm invented is given tacit consent in social existing invention in the world For the various algorithms of the renaming applied to program.
It is worth mentioning that：The determination method of the name of renaming described in step 1003 is：First analyze those renamings Being not applied to those that those have been not carried out among name is used among the address code in the program of execution, if the name of renaming It is central to be not applied to those that those have been not carried out and be used among the address code in the program that performs, just by these renamings The name that a fraction is chosen among name first cancel in the program for being reserved as performing distributed to and be not carried out, then It is reallocated to and is used by another central possible correct program, and carries out another possible correct program renaming, and The life again that the destination operand address code of each non-renaming is used with another possible correct program among renaming The name of name, but the name of the renaming of the destination operand address code distribution of each non-renaming is different.And distribute that Ke Cai Give tacit consent to the renaming algorithm invented with social existing invention in the world to be allocated, or by randomly choosing distribution weight The name of name, but the destination operand address code of some non-renamings can also use social existing invention in the world write from memory The renaming algorithm invented is recognized to having between destination operand address code that is multiple different or not being same non-renaming Change the name of same renaming in the case of special relationship.
It is noted that the register carried out among the register renaming operation mentioned by step 1003 can be according to one The corresponding register mappings information that Register renaming map table is recorded is modified.
It is noted that configuration processor is also to use the Register renaming map table, mathematically, mapping is then individual Term, refers to the relation of element mutually " correspondence " between the collection of two elements, is noun；Also referring to " formation corresponding relation ", this is moved Make, verb.And hereafter map, refer to correspondence, or finger-type into correspondingly.
Register renaming map table is illustrated with one embodiment below.
The corresponding Register renaming map table of the instruction is just to that should instruct in setting.
The central destination operand address code refers to some address code in some instruction in program.
The position among register in the destination operand address code corresponding to the register name of renaming, is known as the mesh Operand address code renaming register-bit.Deposit in the destination operand address code corresponding to the register name of renaming Device, is known as the destination operand address code renaming register.The register of non-renaming in the destination operand address code The position among register corresponding to name, is known as the non-renaming register-bit of the destination operand address code.The purpose is operated Register in number address code corresponding to the register name of non-renaming, is known as the non-renaming of destination operand address code and posts Storage.The mapping set in destination operand address code is referred to as the mapping of destination operand address code,
Explanation：The non-renaming position of the destination operand address code is the non-renaming register of the destination operand address code Register section, is also a register.The destination operand address code renaming position is that the destination operand address code is ordered again The register section of name register, is also a register.The part of register, is also a register in a word.
The destination operand address code sets mapping：The register name institute of non-renaming is right in the destination operand address code The mapping for the position among register answered is mapped by the example of mapping hereafter.And with the purpose in example hereafter Filial generation table purpose behaviour exemplified by a position among register in operand address code corresponding to the register name of non-renaming Make each the example among the register in number address code corresponding to the register name of non-renaming, and hereafter one should A position among register in destination operand address code corresponding to the register name of non-renaming, is referred to as purpose operation Non- renaming in the position of register in number address code corresponding to the register name of non-renaming, the destination operand address code Register name corresponding to this of register be in the destination operand address code corresponding to the register name of non-renaming Register each one of position.Non- renaming posts in each destination operand address code hereafter occurred This of the register corresponding to storage name in that hereafter the mentioned for the first time destination operand address code all referring to not weighing The position of register corresponding to the register name of name.
Step：Mapping relations illustrate, because central purpose behaviour among the mapping that the destination operand address code is set Each position for making the register in number address code corresponding to the register name of non-renaming is that have a sequence number, and the destination operand Also there is a sequence number each position of address code renaming register, so non-renaming is posted in the central destination operand address code Storage name corresponding to register this occupied by register section be then be mapped to in the destination operand address code The position sequence number of this of the register corresponding to the register name of non-renaming is the destination operand address of same position sequence number Among register section occupied by code renaming register-bit.Do not ordered again in the central destination operand address code alternatively The register among register section occupied by this of the register corresponding to the register name of name is mapped to being somebody's turn to do The position sequence number of this of the register in destination operand address code corresponding to the register name of non-renaming is same position sequence number The destination operand address code renaming register-bit occupied by register section among register among.
And each position of the register in the destination operand address code corresponding to the register name of non-renaming is all entered The mapping gone out produced by after row step, then as the mapping set in the destination operand address code, and the destination operand The mapping set in the code of location also includes：Register in the destination operand address code corresponding to the register name of non-renaming The register of non-renaming in the destination operand address code among each mapping all gone out produced by after carry out step Register mappings corresponding to name are into the destination operand address code renaming register, this mapping.
The Register renaming map table of a upper instruction is completed after quoting, the Register renaming map of next instruction Table is just quoted.Each Register renaming map table is to complete what is quoted one by one by the order of its corresponding instruction.
The reference of table in instruction, so that one instructs as an example, an instruction hereafter is referred to as the instruction.And the instruction The example of the Register renaming map table of the example exactly instruction.
Register corresponding to the register name of the non-renaming of destination operand address code of the upper instruction of the instruction exists Mapping in the Register renaming map table of the upper instruction of the instruction, then claim upper one of the instruction to instruct its destination operand The non-renaming register of address code is related to mapping.The deposit of the non-renaming of destination operand address code of the upper instruction of the instruction Reflecting in each register Register renaming map table that one instructs in the instruction in the register corresponding to device name Penetrate, be then referred to as upper one of the instruction and instruct the small register of the non-renaming of its destination operand address code to be related to mapping.If this refers to The mapping in the Register renaming map table of an instruction is made, neither upper one of the instruction is with instructing its destination operand The location non-renaming register of code is related to mapping, nor upper one of the instruction instructs its non-renaming of destination operand address code small Register is related to mapping, then such mapping is referred to as non-upper command mappings.
It is referred to as non-upper finger in the table of a upper instruction for the corresponding Register renaming map table reference of the instruction instruction Make the mapping of mapping, and quote the destination operand of setting in institute in each destination operand address code of a upper instruction Location code mapping.Claim if the corresponding Register renaming map table completion of the instruction is quoted in the table of a upper instruction for the instruction For the mapping of non-upper command mappings, and complete to quote setting in institute in each destination operand address code of a upper instruction Destination operand address code maps, then the corresponding Register renaming map table of the instruction just completes reference.Pair of the instruction The completion of Register renaming map table is answered to quote the mapping for being referred to as non-upper command mappings in the table of a upper instruction for the instruction, with And complete quote it is upper one instruction each destination operand address code on institute in set destination operand address code map after, The corresponding Register renaming map table of the instruction is known as the Register renaming map table quoted
The branch point removes the corresponding Register renaming map table of first instruction of another possible correct program, The branch point can also be removed the corresponding register renaming quoted of first instruction of the program for execution Life is thought highly of in the corresponding deposit that the content of mapping table removes first instruction of another possible correct program as the branch point The content of name mapping table.The branch point removes the corresponding register renaming of first instruction of another possible correct program Mapping table removes the branch point content of the corresponding Register renaming map table of first instruction of the program for execution In the corresponding Register renaming map table for first instruction that another possible correct program is removed as the branch point Hold the corresponding Register renaming map table that the branch point after finishing removes first instruction of another possible correct program Just complete reference.The corresponding register renaming that the branch point removes first instruction of another possible correct program is reflected The content that firing table removes the branch point in the corresponding Register renaming map table of first instruction of the program for execution is made The content of the corresponding Register renaming map table of first instruction of another possible correct program is removed for the branch point The branch point after finishing removes the corresponding Register renaming map table of first instruction of another possible correct program Just it is referred to as the Register renaming map table quoted.
By taking an address code in an instruction as an example, and the instruction in example is referred to as the instruction, and the address in example Code is referred to as the address code.
The non-renaming of the address code of the instruction if the address code of the instruction is a source operand address code The corresponding register of register name reflected under the mapping of the corresponding Register renaming map table quoted of the instruction The register shot out name corresponding in setting, is just corrected as the address code register name renaming of the instruction Renaming register name.
The address code of the instruction does not order again if the address code of the instruction is a destination operand address code The corresponding register of register name of name institute under the mapping of the corresponding Register renaming map table quoted of the instruction The register come name corresponding in setting is mapped out, is just corrected as the address code register name renaming of the instruction For renaming register name, in addition can also be new to the address code register name one of the instruction through renaming algorithm Renaming name.
It is noted that in data movement instruction or exchange instruction, if certain form of data command or exchange refer to The register name of source operand address code of the non-renaming in order and posting for the destination operand address code of the non-renaming Storage name is different, then the register name correspondence of the non-renaming of the source operand address code of the non-renaming in the data command Register mapped out under the mapping of the corresponding Register renaming map table quoted of the instruction come register The corresponding name in setting, just as posting that the source operand address Code memory name renaming of its instruction is corrected as The register name use of the register name of storage renaming, then the destination operand address code of the data command non-renaming The register name for the register renaming that revised data command source operand address code is corrected as is not weighed as this The register name for the renaming that the destination operand address code register name renaming of name is corrected as, so that, amendment The destination operand address of the register name and the renaming of the source operand address code of the renaming of the data command afterwards The register name of code is identical.If destination operand address code in certain form of data movement instruction or exchange instruction is posted Storage name is identical with the register name of source operand address code, then the deposit of the destination operand address code of the non-renaming of the instruction Device name amendment is corresponding in the instruction using the corresponding register of register name of the destination operand address code of its instruction The lower name for mapping out the register come corresponding in setting of mapping in the Register renaming map table quoted, makees The name for the register renaming being corrected as the destination operand address code register name renaming of its instruction is repaiied Just or the instruction is translated into do-nothing instruction, but the corresponding Register renaming map table of the instruction is without amendment.
The example for one group of Register renaming map table of application shown in Fig. 4.Table 1 is the register corresponding to instruction 1 Renaming mapping table, and the corresponding instruction 1 of table 1.Table 2 correspondingly refers to for the Register renaming map table corresponding to instruction 2, and table 2 Make 2.Table 3 is to instruct the Register renaming map table corresponding to 3, and the corresponding instruction 3 of table 3.Table 4 is posting corresponding to instruction 4 Storage renaming mapping table.A, A1, B, B2 represent register respectively.Table 1 record map information be：A is mapped as A1, B mappings For B2.If there is the name A of the address code of operand in the instruction 1 corresponding to table 1, and instruct the address code of 1 destination operand Name A is modified to A2.Then the mapping mode of table 2 is that A is mapped as A2, then the map information that table 2 is recorded is that A is mapped as A2, B mappings For B2.If there is the name B of the address code of destination operand in the instruction 2 corresponding to table 2, and instructs the address of 2 destination operand The name B of code is modified to B3.Then the mapping mode of table 3 is that B is mapped as B3, then the map information that table 3 is recorded is that A is mapped as A2, B It is mapped as B3.If there is the name A of the address code of destination operand in the instruction 3 corresponding to table 3, and instruct 3 destination operand The corresponding register A of name is modified to A3 in address.Then the mapping mode of table 4 is that A is mapped as A3, then the mapping letter that table 4 is recorded Cease and be mapped as A3 for A, B is mapped as B3.It is noted that the source operand address code or non-renaming of the non-renaming of instruction Destination operand address code can be modified according to the record of instruction corresponding Register renaming map table in itself.
As shown in figure 3, renaming preprocess method of the present invention further comprises step 1007：To the instruction Jing Guo renaming Carry out instruction fetch.The step 1007 further comprises the steps：
Step 3001：Confirm a correct branched program of the branch point to be processed.The branch point to be processed is performed to take Under first instruction it is upper one instruction jump instruction, obtain the program indicated by the jump instruction, then redirect this Indicated program is instructed as the correct branched program of the branch point to be processed.Or execution branch point to be processed takes Under first instruction it is upper one instruction branch instruction, the program indicated by the branch instruction is obtained, then by the branch Indicated program is instructed as the correct program of the branch point to be processed.
Step 3002：Judge the correct branched program whether the branched program with the configuration processor of the branch point to be processed It is identical.If the branch of the configuration processor of the correct branched program and the branch point to be processed is identical, it is determined that from will The branched program that the branch point of processing removes execution is correct, then performs step 3003.If the correct branched program with The configuration processor branch of the branch point to be processed is different, it is determined that the branch of execution is removed from the branch point to be processed Program is wrong, then performs step 3005.
Step 3003：Judge whether stored from this point to be processed in prefetched instruction caching and execution unit caching The branch instruction that fulcrum is removed.If being stored in prefetched instruction caching and execution unit caching from this point to be processed The branch instruction that fulcrum is removed, then perform step 3004.It is worth mentioning, the branch instruction removed includes passing through renaming Instruction and general branch instruction.
Step 3004：Will be stored from the branch point to be processed from prefetched instruction caching and execution unit caching On the branch instruction removed delete.
Step 3005：Judge whether stored from this point to be processed in prefetched instruction caching and execution unit caching The branch instruction that fulcrum is removed.If being stored in prefetched instruction caching and execution unit caching from this point to be processed The branch instruction that fulcrum is removed, then perform step 3006.If not having in prefetched instruction caching and execution unit caching The branch instruction removed from the branch point to be processed is stored, step is performed：3007.
Step 3006：Remove what is removed in this to be performed branch point from prefetched instruction caching and execution unit caching A upper finger for first instruction of the configuration processor that the branch point to be processed is removed is performed among branched program in system The corresponding branched program that the jump instruction of order or branch instruction are confirmed is used as this to be performed branch determined from this The branched program removed of point, after then the branched program is removed, then remove from some caching prefetched instruction caching and The execution unit caches and is performed the configuration processor that the branch point to be processed is removed in system among unexistent branched program First instruction a upper instruction jump instruction or the corresponding branched program that is confirmed of branch instruction, and after removing Branch next branch using branch prediction method confirm after removed again from some caching, then by the prefetched instruction caching with The branch instruction removed from the branch point to be processed contained in execution unit caching is deleted.It is worth mentioning that step The program removed among rapid 3006 is performed as a configuration processor under execution system arrangement after the removal.It is worth mentioning The instruction not decoded in the instruction for being the branched program that the branch point is removed, is decoded to the instruction not decoded.To solution To carrying out the command operating that non-renaming is operated after code, first by the corresponding register renaming of the instruction at the beginning of non-renaming Mapping table is dealt into the renaming unit for being responsible for processing configuration processor renaming, and the instruction that then this do not carried out to renaming operation is put Renaming operation is carried out in the renaming unit for being responsible for processing configuration processor renaming.
Step 3007：Without operation.
It is noted that when carrying out renaming operation, to each another may correct program set pair The group name answered operates for renaming, so as to avoid another two or more possible correct programs from carrying out simultaneously When renaming is operated, the identical alias is used to register.It is noted that group name may be provided at the renaming table In.
It is noted that resetting instruction fetch in the beginning instruction buffer for handling another possible correct program Afterwards, in processing ending instruction buffer instruction fetch, according to the beginning instruction buffer weight for handling another possible correct program Special case, the time of the good processing ending instruction buffer input instruction vacant without spatial cache of layout and position are there remains after dress Put.For example, a caching has been stored for A branches, the number of instructions of A branches is then calculated, so that it is determined that filling up idle space Input time and input position.Then basis fills up the input time of idle space and input position takes from another caching Instruction, to put forward the utilization rate of effect caching.
It is noted that when being stored in the instruction in prefetched instruction caching, energy in being cached according to prefetched instruction Number of instructions, advance layout need to be stored in well the number of instructions in prefetched instruction caching.
If it is noted that this another may correct program be conditional branching program, can be by the conditional branching Address information in the corresponding prefetched instruction caching that the address that program adds the respective conditions is calculated.When condition is performed Afterwards, the address information in being cached according to the prefetched instruction finds corresponding prefetched instruction cache instruction position and prefetched.
If, may be just by another related to the branch it is noted that some branched program will be performed True program locking.The branched program of locking is just preferentially looked for after branch prediction failure.
Renaming preprocess method of the present invention further provides a setting at least renaming unit.The renaming unit is supplied Carry out renaming operation.First, another possible correct program is allocated to the renaming unit.It is noted that If there are multiple another possible correct program, correctly program the heavy life may be distributed respectively by each another Name unit.Then, the renaming situation and the situation of program of each register before the branch point to be processed are recorded.Specifically Ground says, in this procedure, before the branch point to be processed, the original name of each register, and repaiied after renaming is operated The title and the title of last time amendment just crossed.It is noted that these situations all may be recorded in the renaming table.Value Obtain one and be mentioned that in each register during renaming, the instruction corresponding to alias that each register is used is in the branch point The alias finally corrected before is also recorded in the renaming table.It is noted that the renaming table is available for record at each point The renaming situation and the situation of program of each register before fulcrum.Specifically, in this procedure, to be processed every Before one branch point, the original name of each register, and corrected title and last time amendment after renaming is operated Title.It is noted that these situations all may be recorded in the renaming table.Preferably, two renaming units are set.Respectively The corresponding renaming table can be set in renaming unit, in order to carry out renaming operation.The renaming table can this be heavy by two Unit access is named, to avoid each renaming unit from carrying out using identical alias when respective renaming is operated.But this is heavy Name list can only be changed by corresponding renaming unit.
The above enumerates for the specific embodiment of the present invention, for the equipment and structure of wherein not detailed description, should When being interpreted as taking the existing common apparatus in this area and universal method to be practiced.
The above embodiment of the present invention is only that explanation technical solution of the present invention is used simultaneously, only the row of technical solution of the present invention Lift, the technical scheme and its protection domain being not intended to limit the invention.Using equivalent technologies mean, equivalent apparatus etc. to this hair The improvement of technical scheme disclosed in bright claims and specification is considered to be without departing from claims of the present invention And the scope disclosed in specification.

Claims (8)

1. a kind of renaming preprocess method, it is characterised in that comprise the following steps：
(A) another possible correct procedure in a branch point is determined；
(B) decode it is described another may correct program, and set a temporal cache for storage decoding it is described another may One group of instruction that correct procedure is obtained；
(C) register renaming operation is carried out, sets a prefetched instruction to cache for the instruction after storage renaming operation；Its In, the step (C) further comprises the steps：(C.1)：Operation note position confirms in selected source operand address code Position；
(C.2)：Judge the branch point into the program for not including selected instruction between selected instruction with the presence or absence of the behaviour selected Make the related destination operand address code of register-bit；
If there is the operation note position selected in the branch point to the program for not including selected instruction between selected instruction Related destination operand address code, then it is each present in the program of selected instruction to not including between selected instruction in the branch point Last that operation note selected position is arranged in individual the selected related destination operand address code in operation note position Related destination operand address code is known as operation note position and confirms destination operand address code, into step (C.3),
If the operation note selected is not present in the branch point to the program for not including selected instruction between selected instruction The related destination operand address code in position, into step (C.4)；
(C.3)：Confirm that destination operand address code carries out renaming, i.e. destination register and ordered again to operation note position Name, the operation note position confirms that the operation note contained among destination operand address code position is corrected in renaming Operation, just as the operation note operation corrected of position, into step (C.7)；
(C.4)：Judge with whether there is the related destination operand of the operation note selected in the program before the branch point Location code,
If there is the related destination operand address code in operation note position selected in the program before the branch point, at this Row is last in the related destination operand address code in operation note position that each is selected present in program before branch point The related destination operand address code in that operation note selected position is referred to as operation note position with confirming destination operand Location code, into step (C.5),
If the related destination operand address code in operation note position selected is not present in the program before the branch point, enter Step (C.6)；
(C.5)：Confirm that destination operand address code carries out renaming, i.e. destination register and ordered again to operation note position Name, the operation note position confirms that the operation note contained among destination operand address code position is corrected in renaming Operation, just as the operation note operation corrected of position, into step (C.7)；
(C.6)：The operation of selected operation note position in the source operand address code of a selected non-renaming, just Carry out reservation origin operation；
(C.7)：The operation of the register operated in source operand address code is selected after the operation note bit manipulation corrigendum It is corrected, the name corresponding to operated register is corrected as selected source operand address Code memory name renaming Renaming register name；
(D) one group of execution unit is set to cache, each execution unit caching corresponds to each execution unit respectively, for storing described perform Corresponding instruction performed by unit, wherein, distribute the instruction extremely execution list corresponding with the instruction of renaming of renaming Execution unit buffer memory corresponding to member, to improve the execution efficiency of execution unit；
(E) fetching is carried out to the instruction through renaming.
2. renaming preprocess method as claimed in claim 1, it is characterised in that the step (E) further comprises following Step：
(E.1) a correct branched program of the branch point to be processed is confirmed；
(E.2) whether judge the correct branched program is phase with the branched program of the configuration processor of the branch point to be processed Together, if the branch of the configuration processor of the correct branched program and the branch point to be processed is identical, it is determined that from will The branched program removed of the branch point of processing is correct, then performs step (E.3), if the correct branched program with The configuration processor branch of the branch point to be processed is different, it is determined that the branch removed from the branch point to be processed Program is wrong, then performs step (E.5)；
(E.3) judge whether stored from the branch to be processed in prefetched instruction caching and execution unit caching The removed branch instruction of point, if being stored in prefetched instruction caching and execution unit caching from institute to be processed The branch instruction that branch point is removed is stated, then performs step (E.4)；
(E.4) branch instruction removed from the branch point to be processed is deleted；
(E.5) judge whether stored from the branch to be processed in prefetched instruction caching and execution unit caching The removed branch instruction of point, if being stored in prefetched instruction caching and execution unit caching from institute to be processed The branch instruction that branch point is removed is stated, then performs step (E.6), if delaying in prefetched instruction caching and the execution unit The branch instruction removed from the branch point to be processed is not stored in depositing, step (E.7) is performed；
(E.6) remove the corresponding branched program removed from the branch point to be processed of the branch instruction as from It is determined that the branched program that the branch point to be performed is removed, after the branched program to be performed is removed, is prefetched described The branch instruction removed from the branch point to be processed having in instruction buffer and execution unit caching is deleted；With
(E.7) without operation.
3. renaming preprocess method as claimed in claim 2, it is characterised in that the step (A) further comprises following Step：
(A.1) Branch Processing Unit and an at least recording unit are set；
(A.2) an at least subrecord unit is distributed in the recording unit, for recording used point under the branch point Zhi Chengxu state；
(A.3) by handling the subrecord cell data, conventional branched program, the branched program being of little use and pole are judged not Conventional branched program, if branched program is conventional branched program, performs step (A.4), if branched program is to be of little use Branched program, then perform step (A.5), if branched program is the branched program that is of little use of pole, perform step (A.6)；
(A.4) the conventional branched program deposit caching that will be judged by performing in step (A.3)；
(A.5) branched program that is of little use judged by performing in step (A.3) is removed；With
(A.6) remove and be of little use branched program by performing the pole judged in step (A.3), and cancel corresponding described Subrecord unit.
4. renaming preprocess method as claimed in claim 1, it is characterised in that non-renaming in destination operand address code Register name corresponding to the operation note position of register be the non-renaming register-bit of destination operand address code, mesh Operand address code in non-renaming register name corresponding to register be that the non-renaming of destination operand address code is posted Storage, wherein, the register mappings among register section occupied by the non-renaming register-bit of destination operand address code To the purpose of the same position sequence number of position serial number of the operation note position with the non-renaming register of destination operand address code Among the register among register section occupied by operand address code renaming register-bit.
5. renaming preprocess method as claimed in claim 4, it is characterised in that removing another when the branch point may The address code of the instruction of correct program is source operand address code or destination operand address code, then the address code instructed is relative The register for the non-renaming register name answered maps out post in the Register renaming map table that instruction has been quoted Name corresponding to storage, the register name for the renaming being corrected as the address code register name renaming of instruction.
6. renaming preprocess method as claimed in claim 4, it is characterised in that the branch point removes another may be just The corresponding Register renaming map table of first of true program instruction, and being used for of removing of the branch point is performed journey The content of the corresponding Register renaming map table of first instruction of sequence removes another as the branch point may be correct First of program instruction corresponding Register renaming map table content, i.e., described branch point removes another may be just The corresponding Register renaming map table of first instruction of true program just completes reference.
7. renaming preprocess method as claimed in claim 4, it is characterised in that
When in the address code in the configuration processor for being not applied to be not carried out in the register name of renaming, then posting renaming The register name of selected part cancels the configuration processor distributed to and be not carried out among storage name, and being then assigned to another may be just True program is used, and carry out another may correct program renaming, and among renaming each non-renaming purpose The register name for the renaming that operand address code division is used with a possible correct program,
Wherein, each the register name of the renaming of the destination operand address code distribution of non-renaming is different.
8. renaming preprocess method as claimed in claim 4, it is characterised in that
When another may program be correctly conditional branching program, then it will be added in the conditional branching program according to the condition Address computation come out corresponding prefetched instruction caching in address information；
After condition is performed, the location of instruction in corresponding prefetched instruction caching is found according to the address information and prefetched.
CN201410419560.0A 2014-06-12 2014-08-25 Renaming preprocess method Active CN104156196B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410419560.0A CN104156196B (en) 2014-06-12 2014-08-25 Renaming preprocess method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN2014102618460 2014-06-12
CN201410261846.0 2014-06-12
CN201410261846 2014-06-12
CN201410419560.0A CN104156196B (en) 2014-06-12 2014-08-25 Renaming preprocess method

Publications (2)

Publication Number Publication Date
CN104156196A CN104156196A (en) 2014-11-19
CN104156196B true CN104156196B (en) 2017-10-27

Family

ID=51881706

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410419560.0A Active CN104156196B (en) 2014-06-12 2014-08-25 Renaming preprocess method

Country Status (1)

Country Link
CN (1) CN104156196B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106874442B (en) * 2017-02-08 2023-08-18 三和智控(北京)系统集成有限公司 Method and device for realizing self-carrying characteristic information of data through naming of data name
CN109101276B (en) * 2018-08-14 2020-05-05 阿里巴巴集团控股有限公司 Method for executing instruction in CPU
CN111506347B (en) * 2020-03-27 2023-05-26 上海赛昉科技有限公司 Renaming method based on instruction read-after-write related hypothesis

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
CN1186981A (en) * 1996-12-09 1998-07-08 松下电器产业株式会社 Information processing device by using small scale hardware for high percentage of hits branch foncast
US5878254A (en) * 1995-02-24 1999-03-02 Hitachi, Ltd. Instruction branching method and a processor
CN101187863A (en) * 2006-11-17 2008-05-28 国际商业机器公司 Data processing system, processor and method of data processing
CN103282874A (en) * 2010-10-12 2013-09-04 索夫特机械公司 An instruction sequence buffer to enhance branch prediction efficiency
CN103838550A (en) * 2012-11-26 2014-06-04 上海芯豪微电子有限公司 Branch treatment system and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US20140025894A1 (en) * 2012-07-18 2014-01-23 Electronics And Telecommunications Research Institute Processor using branch instruction execution cache and method of operating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US5878254A (en) * 1995-02-24 1999-03-02 Hitachi, Ltd. Instruction branching method and a processor
CN1186981A (en) * 1996-12-09 1998-07-08 松下电器产业株式会社 Information processing device by using small scale hardware for high percentage of hits branch foncast
CN101187863A (en) * 2006-11-17 2008-05-28 国际商业机器公司 Data processing system, processor and method of data processing
CN103282874A (en) * 2010-10-12 2013-09-04 索夫特机械公司 An instruction sequence buffer to enhance branch prediction efficiency
CN103838550A (en) * 2012-11-26 2014-06-04 上海芯豪微电子有限公司 Branch treatment system and method

Also Published As

Publication number Publication date
CN104156196A (en) 2014-11-19

Similar Documents

Publication Publication Date Title
CN1310155C (en) Appts. for memory communication during runhead execution
US10409605B2 (en) System and method for using a branch mis-prediction buffer
CA1200318A (en) Central processor
KR100341431B1 (en) Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US7707397B2 (en) Variable group associativity branch target address cache delivering multiple target addresses per cache line
US5519841A (en) Multi instruction register mapper
CN101558388B (en) Data cache virtual hint way prediction, and applications thereof
JP3542021B2 (en) Method and apparatus for reducing set associative cache delay by set prediction
CN101449238B (en) Local and global branch prediction information storage
US8627047B2 (en) Store data forwarding with no memory model restrictions
EP2204741B1 (en) Processor and method for using an instruction hint to prevent hardware prefetch from using certain memory accesses in prefetch calculations
US20070204107A1 (en) Cache memory background preprocessing
US20030200396A1 (en) Scheme for reordering instructions via an instruction caching mechanism
US20130086564A1 (en) Methods and systems for optimizing execution of a program in an environment having simultaneously parallel and serial processing capability
CN1790256A (en) Branch lookahead prefetch for microprocessors
CN109196485A (en) Method and apparatus for maintaining the data consistency in non-homogeneous computing device
US20100312968A1 (en) Arithmetic processing apparatus and method of controlling the same
CN1196997C (en) Load/load detection and reorder method
CN109313554A (en) Method and apparatus for being scheduled in non-homogeneous computing device
CN104156196B (en) Renaming preprocess method
CN109196489A (en) Method and apparatus for reordering in non-homogeneous computing device
CN105814549A (en) Cache system with primary cache and overflow FIFO cache
US5581719A (en) Multiple block line prediction
JP2002527798A (en) Mechanism for load block based on store address generation and universal dependency vector
US9311247B1 (en) Method and apparatus for detecting patterns of memory accesses in a computing system with out-of-order program execution

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20200917

Address after: No.2, 4th floor, building a, No.88, Beijing East Road, Taicang Development Zone, Suzhou City, Jiangsu Province

Patentee after: Suzhou Yunshou Software Technology Co.,Ltd.

Address before: 528322, 15 Village Road, Huanglian Town, Leliu Town, Shunde District, Guangdong, Foshan

Patentee before: Gong Weifeng

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20211221

Address after: Room 701, building 3, No. 10, Luhe guanhuangtang Road, Huangjing, Taicang, Suzhou, Jiangsu 215400

Patentee after: Suzhou Jubei Machinery Design Co.,Ltd.

Address before: 215000 No. 2, floor 4, building a, No. 88, Beijing East Road, Taicang Development Zone, Suzhou, Jiangsu

Patentee before: Suzhou Yunshou Software Technology Co.,Ltd.

TR01 Transfer of patent right