CN104156196A

CN104156196A - Renaming pretreatment method

Info

Publication number: CN104156196A
Application number: CN201410419560.0A
Authority: CN
Inventors: 龚伟峰
Original assignee: Individual
Current assignee: Suzhou Jubei Machinery Design Co ltd
Priority date: 2014-06-12
Filing date: 2014-08-25
Publication date: 2014-11-19
Anticipated expiration: 2034-08-25
Also published as: CN104156196B

Abstract

A renaming pretreatment method includes the following steps that firstly, another possible right program is determined in a branch point; secondly, the possible right program is decoded and a temporary cache for storing a set of commands obtained when the possible right program is decoded is arranged; thirdly, renaming operation is conducted on the set of commands, and a prefetching command cache for storing the commands generated after the renaming operation is conducted is arranged; fourthly, a set of unit caches is arranged, the unit caches correspond to the corresponding execution units so as to store the corresponding commands executed by the executing units, and the renamed commands are distributed to the unit caches corresponding to the corresponding executing units corresponding to the renamed commands.

Description

Rename preprocess method

Technical field

The present invention relates to branch prediction method, particularly a kind of rename preprocess method, by adopting this rename preprocess method, may correct program deposit another in buffer memory in advance, to reduce instruction flow line line series, thereby improves processor performance.

Background technology

In the prior art, processor is all provided with buffer memory (Cache).The object that buffer memory is set is in order to allow the processing speed of velocity adaptive processor of data access.The capacity of buffer memory is much smaller than internal memory, but speed can approach the frequency of processor.In the time that processor sends memory access request, first check in buffer memory, whether there is request msg.If there is request msg (hitting) in buffer memory, directly obtain data from buffer memory; If there is not request msg (failure) in buffer memory, want first the corresponding data in internal memory to be written into buffer memory, then returned to processor.

Register renaming is also a kind of technology that improves processor performance, and its object has been to avoid machine instruction or the unnecessary orderization of microoperation to carry out, thereby has improved processor processing power.The operand that processor adopting register is held instruction and result.Different instructions can have the different execution time.For example, the execution time of the instruction of a rdma read, enough carry out other instruction of hundreds of bar.Therefore, in the situation that allowing many executing instructions, the instruction of those instruction address backs, than reading more Zao completing of internal memory instruction, this has just formed instruction execution sequence and has been different from its order in program.This out of order execution is one of crucial way of high-performance processor raising arithmetic speed.But the quantity of the operable register name of processor is limited.But a lot of high-performance processors have a lot of physical registers, can in the time that processor instruction streamline is carried out, be different physical registers these register mappings, thereby provide extra parallel ability at hardware level.

But, if many instruction has been used same memory location, if these instructions are carried out and may be caused 3 kinds of data hazard (data hazard) not according to program address order: write-then-read (Read-after-write, RAW): the data that read from register or internal memory must be to deposit in herein before.This situation is real data dependence instruction stream dependence in other words.Must carry out successively according to procedure order.First write after write (Write-after-write, WAW): write continuously specific register or internal memory, this memory location finally only comprises the data of writing for the second time so.This can cancel or abolish write operation for the first time.Relevant being also said to be of WAW is " output is relevant " (output dependencies).Write-after-read (Write-after-read, WAR): the data that read operation obtains write before this, instead of the result of write operation after this.Therefore this is a kind of spurious correlation (false dependency), can solve by rename.Needn't wait for after all read operations complete and carry out again write operation, can keep two parts of copies of this memory location: old value and new value.Reading the operation of old value can proceed, and without consideration, those are write new value and even write the operation of reading new value afterwards of new value.This spurious correlation is removed, and has produced extra out of order execution chance.When all read old Value Operations and be satisfied after, the register that old value is used both can discharge.This is the essence of register renaming.

Branch predictor is also a technology that improves processor performance.Use the object of branch predictor to be to guess which branch will be performed before branch instruction execution finishes, to improve the flow process of instruction pipeline, thus the performance of raising processor.

Conditional branch instructions has the follow-up execution of two-way branch conventionally.Do not take (not taken) redirect, continuation order is carried out; And take (taken) to jump to another piece program internal memory and go to carry out instruction there.Whether conditional jump has only passed through the execute phase (execution stage) and just can decide in instruction pipelining in this branch instruction.If there is no branch predictor, processor will wait for that branch instruction passed through the execute phase of instruction pipelining, just next instruction is sent into the first stage-instruction fetch phase (fetch stage) of streamline.This technology is called pipeline stall (stream stalled).This is the way of the streamline execution of the reply branch instruction of early time treatment device employing.

In branch predictor conjecture two-way branch, which most probable occurs, and then speculates to carry out the instruction on this road, the time waste of avoiding pipeline stall to cause.If found afterwards branch prediction mistake, those intermediate results of speculating in streamline so to carry out are all abandoned, and the instruction again obtaining on correct point branch line starts to carry out, thereby have caused the delay that program is carried out.From instruction fetch to the progression of streamline that executes instruction (but also not writing back result) in the time of branch prediction when failure waste.Modern processors trend adopts very long streamline, and therefore branch prediction unsuccessfully may be paid very large cost, if wherein.The branch prediction that longer streamline has just needed.Branch prediction techniques mainly contains static prediction technology and the large class of performance prediction technology two.No matter static prediction technology or performance prediction technology are all to speculate to carry out a road instruction, and just carry out after need to confirming carrying out Gai road instruction errors to another road instruction.May relate to the operation of fetching data but carry out another road instruction from internal memory.Once occur fetching data from internal memory.If pack in advance another road instruction into buffer memory,, when after the confirmation command mistake of carrying out, carry out another road instruction.But, in existing branch prediction techniques, there is not such technology.

Summary of the invention

For defect of the prior art, the object of this invention is to provide a kind of rename preprocess method.

According to a kind of rename preprocess method provided by the invention, comprise the following steps:

(A) determine the correct program of another possibility of one in a take-off point;

(B) the correct program of described another possibility of decoding, and one group of instruction that an interim buffer memory obtains for the correct program of described another possibility of storage decoding is set;

(C) carry out register renaming operation, a prefetched instruction buffer memory is set and heavily orders the described instruction after operation for storage.

Further, wherein, further comprise afterwards step (D) in step (C): one group of performance element buffer memory is set, each performance element buffer memory is corresponding each performance element respectively, for the performed corresponding instruction of the described performance element of storage, the instruction of wherein, distributing rename to the corresponding performance element buffer memory of corresponding performance element of the described instruction of rename.

Further, described step (D) further comprises step (E) afterwards: the described instruction through rename is carried out to instruction fetch.

Further, described step (C) is further comprising the steps:

(C.1): operation note position acknowledgement bit in a selected source operand address code;

(C.2): judge that this take-off point is to not comprising whether there is the selected operation note position destination operand address code of being correlated with in the program of selected instruction between selected instruction;

If at this take-off point to there being the selected operation note position destination operand address code of being correlated with in not comprising the program of selected instruction between selected instruction, just be called operation note position and confirm destination operand address code to arranging the relevant destination operand address code in that last selected operation note position in the relevant destination operand address code in each selected operation note position existing in not comprising the program of selected instruction between selected instruction at this take-off point, enter step (C.3)

If to there not being the selected operation note position destination operand address code of being correlated with in not comprising the program of selected instruction between selected instruction, enter step (C.4) at this take-off point;

(C.3): described operation note position confirmation destination operand address code is carried out to rename, i.e. destination register rename;

(C.4): judge in the program before this take-off point, whether there is the selected operation note position destination operand address code of being correlated with,

If there is the selected operation note position destination operand address code of being correlated with in the program before this take-off point, in the relevant destination operand address code in each selected operation note position of existing in the program before this take-off point, arranging the relevant destination operand address code in that last selected operation note position is just called destination address code and is called operation note position and confirms destination operand address code, enter step (C.5)

If there is not the selected operation note position destination operand address code of being correlated with in the program before this take-off point, enter step (C.6);

(C.6): described operation note position confirmation destination operand address code is carried out to rename, i.e. destination register rename;

(C.6): a selected not operation for the selected operation note position in the source operand address code of rename, just retains origin operation.

Further, described step (E) is further comprising the steps:

(E.1) confirm a correct branched program of described take-off point to be processed;

(E.2) judge that whether described correct branched program is identical with the branched program of the executive routine of described take-off point to be processed, if described correct branched program is identical with the branch of the executive routine of described take-off point to be processed, determine that the branched program taking off from described take-off point to be processed is correct, then execution step (E.3), if described correct branched program is different from the executive routine branch of described take-off point to be processed, determine that the branched program taking off from described take-off point to be processed is wrong, then execution step (E.5.),

(E.3) judge in described prefetched instruction buffer memory and described performance element buffer memory whether store the branch instruction of taking off from described take-off point to be processed.If stored the branch instruction of taking off from described take-off point to be processed in described prefetched instruction buffer memory and described performance element buffer memory, execution step (E.4);

(E.4) branch instruction of taking off from described take-off point to be processed is deleted;

(E.5) judge in described prefetched instruction buffer memory and described performance element buffer memory whether store the branch instruction of taking off from described take-off point to be processed, if stored the branch instruction of taking off from described take-off point to be processed in described prefetched instruction buffer memory and described performance element buffer memory, execution step (E.6), if do not stored the branch instruction of taking off from described take-off point to be processed in described prefetched instruction buffer memory and described performance element buffer memory, execution step (E.7);

(E.6) take off described branched program corresponding to described branch instruction as the branched program taking off from the described described take-off point that will carry out of having determined, after the described branched program that will carry out is taken off, the described branch instruction of having taken off from described take-off point to be processed having in described prefetched instruction buffer memory and described performance element buffer memory is deleted; With

(E.7) do not operate.

Further, described step (A) is further comprising the steps:

(A.1) Branch Processing Unit and at least one record cell are set;

(A.2) distribute at least one subrecord unit at described record cell, for the state that is recorded in the used branched program under described take-off point;

(A.3) by processing described subrecord cell data, judge the branched program that conventional branched program, the branched program being of little use and the utmost point are of little use, if described branched program is conventional branched program, execution step (A.4), if described branched program is the branched program being of little use, execution step (A.5), if described branched program is the branched program that the utmost point is of little use, execution step (A.6);

(A.4) deposit conventional described branched program in buffer memory immediately;

(A.5) remove described in the branched program that is of little use; With

(A.6) remove described in the branched program that is of little use, and cancel corresponding described subrecord unit.

Further, wherein, step (A.4) is further comprising the steps:

(A.4.1) a decoding instruction buffer memory is set;

(A.4.2) the conventional described branched program of decoding, obtains one group of decoding instruction; With

(A.4.3) decoded instruction is deposited in to decoding instruction buffer memory.

Further, in described destination operand address code not the register mappings in the middle of this occupied register section of the corresponding register of register name of rename to this destination operand address code in not this position sequence number of the corresponding register of register name of rename be in the middle of the register in the middle of the occupied register section of this destination operand address code rename register-bit of same sequence number.

As preferred version, when the address code of described instruction is source operand address code or destination operand address code, the corresponding name of register that the register renaming mapping table that register of the corresponding not rename register name of the address code of this instruction has been quoted in this instruction shines upon out, the register name of the rename being corrected as the address code register name rename of this instruction.

As preferred version, the content that the corresponding register renaming mapping table of Article 1 instruction that described take-off point takes off the program that another may be correct takes off the corresponding register renaming mapping table of the Article 1 instruction of program that another may correct for the content of the corresponding register renaming mapping table of the Article 1 instruction of executive routine as described take-off point described take-off point, the corresponding register renaming mapping table that described take-off point takes off the Article 1 instruction of the program that another may be correct has just completed and has quoted.

As preferred version, when not being used in the register name of rename in the address code in unenforced executive routine, the register name of selected part in the middle of the register name of rename is cancelled and distributed to unenforced executive routine, after distribute to program that another may be correct and use, and carry out the program rename that another may be correct, and the destination operand address code of the central each not rename of rename is joined the register name of the rename of a possible correct program use

The register name difference of the rename that wherein, the destination operand address code of each not rename is distributed.

As preferred version, when another may correct program be conditional branching program, will add in described conditional branching program according to the address information in the address computation of this condition corresponding prefetched instruction buffer memory out;

After condition is carried out, find the location of instruction in corresponding prefetched instruction buffer memory to look ahead according to described address information.

Compared with prior art, the present invention has following beneficial effect:

Carrying out in branch prediction, in carrying out most possible correct branched program, in advance another may correct program be processed.And deposit result in buffer memory, and the guide to result is provided, thus make in the time that most possible correct branched program is identified mistake, according to guiding the result that helps to find the program that another possibility is correct.And then reduce loss that microprocessor causes due to branch prediction mistake and the energy of waste, and improve the treatment effeciency of microprocessor, help to save energy.Rename preprocess method of the present invention, provides one group of performance element buffer memory, and the each performance element of this performance element buffer memory is corresponding one by one, reduces the addressing time of each performance element, improves the efficiency of performance element.

Brief description of the drawings

By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:

Fig. 1 is the process flow diagram of one preferred embodiment of rename preprocess method according to the present invention;

Fig. 2 is the process flow diagram of the rename operation of one preferred embodiment of rename preprocess method according to the present invention;

Fig. 3 is the process flow diagram of a rename instruction fetch method of a preferred embodiment of the rename preprocess method according to the present invention;

Fig. 4 is the register mapping table amendment schematic diagram of one preferred embodiment of rename preprocess method according to the present invention.

Embodiment

According to claim of the present invention and the disclosed content of instructions, described in technical scheme of the present invention literary composition specific as follows.

As shown in Figure 1, rename preprocess method of the present invention comprises step 1001: determine the program that another may be correct.A take-off point in a program is got multiple branched programs.Through branch prediction, by most possible correct branched program instruction fetch on this take-off point, and pack execution into.Then, while confirmation in the correct branch of this take-off point, determine possible branched program.Specifically, in the time that the correct branch of this take-off point does not confirm, be responsible for indicating this take-off point to select the indicated branched program of branched program by analyzing this take-off point, or use by the branched program of analyzing branch instruction the used branched program recording in record, thereby determine the possible branched program that this take-off point has.It is worth mentioning that, because most possible correct branched program is used to carry out, so this possible branched program does not comprise the branched program that this is most possible.Then, at this take-off point, one of them possible branched program or multiple possible branched program are carried out to instruction fetch, and deposit the branched program of fetched instruction in buffer memory.Be worth mentioning, can analyze each possible branched program, to predict the possibility of taking of each possible branched program.According to the possibility of taking of possible branched program, determine than the branched program that may carry out, then this more possible branched program is carried out to instruction fetch, then deposit the branched program of fetched instruction in buffer memory.Finally, in the middle of getting multiple may but the program of uncertain execution will take off from take-off point and the program that deposits buffer memory in is defined as the program that another may be correct.If the program that another may be correct is taken off and is used to carry out from take-off point takes off depositing buffer memory in again from take-off point, what be also defined as that another may correct program be worth mentioning is, the branched program that access is the highest, and more possible branched program is all suitable for rename preprocess method of the present invention.It is worth mentioning that, a decoded instruction of decoding instruction buffer memory confession storage is set.One of them buffer memory in the desirable self processor of instruction fetch of the program that another possibility is correct, also can take from this decoding instruction buffer memory.

It is worth mentioning that, rename preprocess method of the present invention can, for a Branch Processing Unit and at least one record cell are set, with according to the state of each branched program, deposit conventional branched program in buffer memory.This Branch Processing Unit can arrange corresponding this record cell according to the state of branched program, and this Branch Processing Unit distributes at least one subrecord unit at this record cell.This subrecord unit is for the used branched program that records same case, and a subrecord unit correspondence is at next used branched program of same case.One, for recording the data that used accordingly this branched program.This Branch Processing Unit reads respectively the data of each subrecord unit of this record cell that this branched program is corresponding, and process, with the branched program of determining the most frequently used under same case and/or recently the most frequently used branched program, conventional and/or recently conventional branched program, the branched program that is of little use and/or is of little use recently and the utmost point is of little use and/or proximal pole is of little use.Deposit conventional and/or nearest conventional branched program in buffer memory, or deposit buffer memory in the time taking this conventional branched program.This branched program that is of little use and/or is of little use recently in decoding instruction buffer memory is removed.The utmost point is of little use and/or this branched program that proximal pole is of little use is removed and cancels that the utmost point is of little use and/or subrecord unit corresponding to branched program that proximal pole is of little use.

The existing invention of society in the world give tacit consent to the cache algorithm of inventing for example have " least recently used algorithm " (LRU), " recently least conventional page replacement algorithm " (LFU), fifo algorithm (FIFO).

For example, to correcting the operation of branched program, the branched program that a record cell uses for the Article 1 that records an execution and pack into can be set.Specifically, this Branch Processing Unit is that in the Article 1 branch packing into, used branched program distributes respectively a corresponding subrecord unit at this record cell, for the service condition data of this branched program corresponding to record.Preferably, the access times of this subrecord unit record this branched program corresponding with this subrecord unit and/or frequency of utilization and/or service condition and recently service condition when recently.In carrying out, after the mistake of prediction, whether the branched program that the Article 1 that this Branch Processing Unit analysis packs into is taken has distributed this subrecord unit corresponding to branched program of taking with this Article 1 at this record cell.If this subrecord unit distributes, the data in this subrecord unit are modified.Preferably, its number of times having used and/or service condition and/or recently service condition when recently by the data modification in this subrecord unit.If this subrecord unit does not distribute, distribute a subrecord unit for the data that record the branched program that this Article 1 takes, and the data of this subrecord unit are revised.Preferably, be to have used once and/or increased to use recently record and/or increase the record when using recently by the data correction of this subrecord unit.This processing unit reads the data of this subrecord unit that each branched program is corresponding, then give tacit consent to the cache algorithm (for example: LRU) of inventing by the existing invention of society in the world the each data of this subrecord unit are processed, to determine conventional in respectively this branched program packing into and/or conventional branched program recently.Specifically, this Branch Processing Unit is by the each subelement recorded data of analysis, comparison and computing, determines this branched program, the branched program that is of little use and/or is of little use recently of commonly using in respectively this branched program packing into and the utmost point is of little use and/or proximal pole is of little use branched program.Then will after first this conventional and/or recently conventional correction branched program instruction fetch, decode, then the decoding instruction of this conventional and/or recently conventional correction branched program be deposited in decoding instruction buffer memory.Or in the time that this conventional and/or nearest conventional correction branched program is taken, after this conventional and/or recently conventional correction branched program is decoded, obtain after the decoding instruction of this conventional and/or recently conventional correction branched program, the decoding instruction of this conventional and/or recently conventional correction branched program is deposited in decoding instruction buffer memory.Correct branch and remove from buffer memory and will be of little use and/or be of little use recently, the utmost point is of little use and/or proximal pole is of little use corrects branch and from buffer memory, removes and distribution is also cancelled in this subrecord unit of its correspondence.

The Article 2 branched program that another this record cell packs into for recording an execution can be set.Specifically, this Branch Processing Unit is that the used branched program of Article 2 branched program packing into distributes corresponding subrecord unit for the data that record corresponding this branched program at another this record cell.Preferably, the access times of this subrecord unit record this branched program corresponding with this subrecord unit and/or frequency of utilization and/or service condition and recently service condition when recently.In carrying out, after the mistake of prediction, whether the branched program that the Article 2 that this Branch Processing Unit analysis packs into is taken has distributed this subrecord unit corresponding to this branched program of taking with this Article 2 at this record cell.If this subrecord unit distributes, the data in this subrecord unit are modified.Preferably, the data modification in this subrecord unit has been used to number of times and/or recently service condition and/or recently service condition when for it.If this subrecord unit does not distribute, distribute a subrecord unit for the data that record the branched program that this Article 2 takes, and the data of this subrecord unit are revised.Preferably, be to have used once and/or increased to use recently record and/or increase the record when using recently by the data correction of this subrecord unit.This processing unit reads the data of this subrecord unit that each branched program is corresponding, then for example, with cache algorithm of the prior art (: LRU) the each data of this subrecord unit are processed, to determine conventional in respectively this branched program packing into and/or conventional branched program recently.Specifically, this Branch Processing Unit is by the each subelement recorded data of analysis, comparison and computing, determines this branched program, the branched program that is of little use and/or is of little use recently conventional and/or that commonly use recently in respectively this branched program packing into and the utmost point is of little use and/or proximal pole is of little use branched program.Then will after first this conventional and/or recently conventional correction branched program instruction fetch, decode, then the decoding instruction of this is conventional and/or recently conventional correction branched program deposits in decoding instruction buffer memory, or at this conventional and/or recently conventional correction branched program decoded after taking after at that time, the decoding instruction of this conventional and/or recently conventional correction branched program is deposited in decoding instruction buffer memory.Correct branch and remove from buffer memory and will be of little use and/or be of little use recently, the utmost point is of little use and/or proximal pole is of little use corrects branch and from buffer memory, removes and distribution is also cancelled in this subrecord unit of its correspondence.The branched program record that this Branch Processing Unit can be used for non-execution to look ahead operates.

One record cell can be set for recording this non-execution branched program of looking ahead, and this Branch Processing Unit distributes respectively a corresponding subrecord unit to each non-execution branched program of looking ahead in this record cell, for the look ahead data of branched program of this non-execution corresponding to record.Preferably, record this non-execution the look ahead access times of branched program and/or frequency of utilization and/or service condition and the recently data of service condition when recently.When the branched program of looking ahead with non-executive mode, whether this Branch Processing Unit is analyzed this record cell is that this non-executive mode branched program of looking ahead distributes this corresponding subrecord unit.If this corresponding subrecord unit distributes, the data of this corresponding subrecord unit are revised its number of times having used and/or service condition and/or recently service condition when recently.If this corresponding subrecord unit does not distribute, corresponding this subrecord unit of finger assignments that this processing unit is looked ahead for this non-execution in this record cell.Then this subrecord unit recorded data is revised.Preferably, this subrecord unit recorded data is modified to the record that has used once and/or increased nearest use record and/or when use recently.This Branch Processing Unit reads each non-execution respectively this subrecord unit corresponding to branched program of looking ahead, and then processes, to determine that those are look ahead conventional in branched program and/or conventional branches recently of non-execution.Specifically, this Branch Processing Unit is given tacit consent to the cache algorithm (for example: LRU) of inventing to respectively data analysis, comparison and the computing of this subrecord unit by the existing invention of society in the world, determines the most frequently used and/or recently the most frequently used non-execution look ahead branched program, conventional and/or conventional non-execution recently look ahead branched program, the non-execution that is of little use and/or is of little use recently look ahead branched program and the utmost point is of little use and/or proximal pole is of little use non-execution looks ahead branched program.Conventional and/or conventional this non-execution are recently looked ahead after the first instruction fetch of branched program and decoded, then the look ahead decoding instruction of branched program of conventional and/or conventional this non-execution is recently deposited in to decoding instruction buffer memory, or in processor, in one of them buffer memory, take conventional and/or conventional this non-execution recently look ahead decoded after branched program after at that time, deposit the look ahead decoding instruction of branched program of conventional and/or conventional this non-execution recently in decoding instruction buffer memory.This non-execution that is of little use and/or is of little use recently branched program of looking ahead is removed from buffer memory.The utmost point is of little use and/or the look ahead instruction of branched program of this non-execution that proximal pole is of little use is removed and cancels that the utmost point is of little use and/or this non-execution that proximal pole is of little use subrecord unit corresponding to branched program of looking ahead from buffer memory.

It is worth mentioning that, if this another may be correct program in there is branched program, can by use manufacture carry out after refitting this another may be correct program time the same branch record and confirm to need the branched program having of the program that this another possibility of instruction fetch is correct by same branch prediction method predict command, then by its instruction fetch, finally carried out rename preprocess method of the present invention.Or this another may be correct the branched program having of program refer to adopt and get multiple possible branched programs, then carried out rename preprocess method of the present invention.

Rename preprocess method of the present invention further comprises step 1002: first decode this another may be correct program, obtains one group of instruction, but before instruction fetch, decoded instruction adopts the decoding that keeps former instruction, and an interim buffer memory is set supplies this group instruction of storage.Be worth mentioning, this group instruction comprises not decoding instruction and decoding instruction, and decoding instruction does not need to carry out decode operation.It is worth mentioning that, this group instruction, according to position, sequence and the time of instruction input after refitting, is stored into the position that this interim buffer memory is corresponding.Rename preprocess method of the present invention further comprises step 1003: this group instruction is carried out to register renaming operation.Then, perform step 1005: a prefetched instruction buffer memory is set, the instruction of carrying out register renaming is stored in to this prefetched instruction buffer memory.Rename preprocess method of the present invention further comprises step 1006: one group of performance element buffer memory is set, a corresponding performance element of performance element buffer memory.Each performance element is carried out corresponding instruction type.First judge the instruction type of each instruction of rename, then the described instruction of rename is sent in the corresponding performance element buffer memory of the described performance element corresponding with the described instruction of rename and is stored, to improve the execution efficiency of this performance element.It is worth mentioning that, in step 1005, after executing rename operation, can reorder to the instruction executing after rename operation, then be stored in this prefetched instruction buffer memory.Each instruction type of renamed instructions that judgement has been reordered further, then by described in reordering renamed instructions be sent in the corresponding performance element buffer memory of described performance element corresponding with the described instruction of having reordered of rename and store.

As shown in Figure 2, the register renaming operation that step 1003 is mentioned, specifically comprises:

Step 2001: operation note position acknowledgement bit (bit addressing) in a selected source operand address code.In address code the operation of operation note (register addressing) be divided into only do not operate a position and also between the position of operation be the operation (bit addressing) of different each operation note position.

This another may be correct program in a selected instruction, and a selected source operand address code for rename not in a formerly fixed instruction, and selected one not in the source operand address code of rename the operation (register addressing) of operation note be divided into only do not operate a position and also between the position of operation be the operation (bit addressing) of different each operation note position, and the operation (bit addressing) of central operation note position is called the operation of operation note position, and the operation (bit addressing) of a selected operation note position in the operation (bit addressing) of selected each an operation note position not being divided in the source operand address code of rename, be called the operation of selected operation note position.The operated position of operation of this selected operation note position, is called the acknowledgement bit of this selected operation note position.

If not there is not operating the acknowledgement bit (bit addressing) of this selected operation note position in the destination operand address code of rename, this destination operand address code is called the relevant destination operand address code in selected operation note position.If the acknowledgement bit of selected operation note position has appearred operating in the operation of operation note position, be called selected operation note position associative operation register-bit operation.

The arrangement of address code is sequential, and the order of address code place instruction in its corresponding programme, just as the order of address code.In program, the arrangement of address code is to arrange by after arriving first by the order of its address code.

Step 2002: judge that this take-off point is to not comprising whether there is the selected operation note position destination operand address code of being correlated with in the program of selected instruction between selected instruction.

If at this take-off point to there being the selected operation note position destination operand address code of being correlated with in not comprising the program of selected instruction between selected instruction, just be called operation note position and confirm destination operand address code to arranging the relevant destination operand address code in that last selected operation note position in the relevant destination operand address code in each selected operation note position existing in not comprising the program of selected instruction between selected instruction at this take-off point, enter step 2003.

If to there not being the selected operation note position destination operand address code of being correlated with in not comprising the program of selected instruction between selected instruction, enter step 2004 at this take-off point.

Step 2003: described operation note position confirmation destination operand address code is carried out to rename, i.e. destination register rename.Query manipulation register-bit confirm the operation (register addressing) of operation note in the middle of destination operand address code be divided into only do not operate a position and also between the position of operation be the operation (bit addressing) of different each operation note position, in the middle of the operation of the operation note position selected with this, the operated position of its operation operated be the operation of identical that operation note position, this operation note position that operates in of operated position is confirmed to be corrected the rear operated position that is (bit addressing) in the rename of destination address code, just be corrected the rear operated position (bit addressing) that is as the operation of this selected operation note position.

Step 2004: judge whether there is the selected operation note position destination operand address code of being correlated with in the program before this take-off point.

If there is the selected operation note position destination operand address code of being correlated with in the program before this take-off point, in the relevant destination operand address code in each selected operation note position of existing in the program before this take-off point, arrange the relevant destination operand address code in that last selected operation note position and be just called destination address code and be called operation note position and confirm destination operand address code, enter step 2005.

If there is not the selected operation note position destination operand address code of being correlated with in the program before this take-off point, enter step 2006.

Step 2005: described operation note position confirmation destination operand address code is carried out to rename, i.e. destination register rename.Query manipulation register-bit confirm the operation (register addressing) of operation note in the middle of destination address code be divided into only do not operate a position and also between the position of operation be the operation (bit addressing) of different each operation note position, in the middle of the operation of the operation note position selected with this, the operated position of its operation operated be the operation (bit addressing) of identical that operation note position, this operation note position that operates in of operated position is confirmed to be corrected the rear operated position that is (bit addressing) in the rename of destination address code, just be corrected the rear operated position (bit addressing) that is as the operation of this selected operation note position.

Step 2006: a selected not operation for the selected operation note position in the source operand address code of rename, just retains origin operation.

It is worth mentioning that, the operation of the register operating in this source operand address code is divided into after the operation of each operation note position after corrigendum step 2001, step 2002 or step 2003 by above-mentioned or step 2004 or step 2005 or step 2006 corrigendum, the operation of the register operating in this source operand address code is corrected the corresponding name of the rear operated register that is, the register name of the rename being just corrected as this source operand address Code memory name rename.

It is worth mentioning that, the register name of the revised address code of register name of address code is to enroll among address code register name.Program point is exactly the program corresponding point of certain location of instruction in program.

It is worth mentioning that, the existing invention of society is in the world given tacit consent to the rename algorithm of inventing and is referred to the various algorithms of inventing the rename for being applied to program.

It is worth mentioning that: definite method of the name of the rename described in step 1003 is: first analyze in the middle of those address codes for the program carried out that are not used to that those have not carried out in the middle of the name of those renames, if in the middle of the address code of those that are not used in the middle of the name of rename that those have not carried out for the program carried out, just the name of choosing a fraction in the middle of the name of these renames is first cancelled and being distributed in the program that is reserved as execution of not carried out, and then distribute to by central another and may correct program use, and carry out the program rename that another may be correct, and in the middle of rename each this not the destination operand address code of rename join one another may be correct the name of the rename that uses of program, but the name of each this rename that the destination operand address code of rename is not distributed is different.Distribute and distribute that can adopt the existing invention of society in the world to give tacit consent to the rename algorithm of inventing, or by random name of selecting to distribute rename, but some rename algorithm that the destination operand address code of rename can also not adopt the existing invention of society in the world to give tacit consent to invent to multiple differences or be not same this between the destination operand address code of rename, do not have in the situation of special relationship, change same rename.

It is worth mentioning that, carry out the corresponding register mappings information that the register in the middle of the operation of the mentioned register renaming of step 1003 can record according to a register mapping table and revise.

It is worth mentioning that, executive routine is also to use this register mapping table, and on mathematics, mapping is term, refers to the element relation of " correspondence " mutually between the collection of two elements, is noun; Also refer to " formation corresponding relation " this action, verb.Below mapping refers to correspondence, or finger-type becomes corresponding.

Below with an embodiment, register renaming mapping table is described.

On arranging, this register renaming mapping table corresponding to this instruction is just to should instruction.

Position in this destination operand address code in the middle of the corresponding register of register name of rename, is just called this destination operand address code rename register-bit.In this destination operand address code, the corresponding register of register name of rename, is just called this destination operand address code rename register.The position in the middle of the corresponding register of register name of rename not in this destination operand address code, is just called not rename register-bit of this destination operand address code.The corresponding register of register name of rename not in this destination operand address code, is just called not rename register of this destination operand address code.The mapping arranging in destination operand address code is called the mapping of destination operand address code,

Illustrate: this destination operand address code not rename position is the not register section of rename register of this destination operand address code, is also a register.This destination operand address code rename position is the register section of this destination operand address code rename register, is also a register.The part of register is in a word also a register.

This destination operand address code arranges mapping: in this destination operand address code, the mapping of the position in the middle of the corresponding register of register name of rename is not all to shine upon by the example of mapping below.And in example below taking the example of each in the middle of the corresponding register of register name of rename not in example represents this destination operand address code of a position in the middle of the corresponding register of register name of rename not in this destination operand address code, an and position in the middle of the corresponding register of register name of rename not in this destination operand address code below, be called in this destination operand address code not this position of the corresponding register of register name of rename, in this destination operand address code, this of the corresponding register of register name of rename is not each one of them position of the corresponding register of register name of rename not in this destination operand address code.This of the corresponding register of register name of rename do not refer in that this destination operand address code of below mentioning for the first time not this position of the corresponding register of register name of rename below and in each this destination operand address code occurring.

Step 4001: mapping relations explanation, in the middle of the mapping of this destination operand address code setting because in central this destination operand address code, each position of the corresponding register of register name of rename is not to have a sequence number, and also there is a sequence number each position of this destination operand address code rename register, so in central this destination operand address code not this occupied register section of the corresponding register of register name of rename be mapped to this destination operand address code in not this position sequence number of the corresponding register of register name of rename be in the middle of the occupied register section of this destination operand address code rename register-bit of same position sequence number.Also in the middle of can saying in this destination operand address code not the register in the middle of this occupied register section of the corresponding register of register name of rename be mapped to this destination operand address code in not this position sequence number of the corresponding register of register name of rename be in the middle of the register in the middle of the occupied register section of this destination operand address code rename register-bit of same sequence number.

And in this destination operand address code not each of the corresponding register of register name of rename all carried out the rear mapping producing of step 4001, the mapping arranging as this destination operand address code, and the mapping of this destination operand address code setting also comprises: in this destination operand address code not each of the corresponding register of register name of rename all carried out in the middle of the rear mapping producing of step 4001 in this destination operand address code not the corresponding register mappings of register name of rename in this destination operand address code rename register, this mapping.

After the register renaming mapping table of a upper instruction completes and quotes, the register renaming mapping table of next instruction is just quoted.Each register renaming mapping table is to complete and quote one by one by the order of its corresponding instruction.

Quoting of table in instruction, taking an instruction as example, an instruction below, is called this instruction.And the example of this instruction example of the register renaming mapping table of this instruction just.

The destination operand address code of an instruction in this instruction is the mapping in the register renaming mapping table of the corresponding register of register name instruction in this instruction of rename not, claim in this instruction its destination operand address code of instruction not rename register relate to mapping.The destination operand address code of an instruction in this instruction is the mapping in the register renaming mapping table of each register instruction in this instruction in the corresponding register of register name of rename not, be called in this instruction its destination operand address code of instruction not the little register of rename relate to mapping.If the mapping in the register renaming mapping table of an instruction in this instruction, neither in this instruction its destination operand address code of instruction not rename register relate to mapping, on neither this instruction its destination operand address code of instruction not the little register of rename relate to mapping, such mapping is called non-upper command mappings.

The corresponding register renaming mapping table of this instruction is quoted in the table of a upper instruction of this instruction and is called the mapping of non-upper command mappings, and quote in each destination operand address code of an instruction in the destination operand address code mapping that arranges.If the corresponding register renaming mapping table of this instruction completes the mapping that is called non-upper command mappings in the table of a upper instruction of quoting this instruction, and complete in each destination operand address code of quoting an instruction in the destination operand address code mapping that arranges, the corresponding register renaming mapping table of this instruction has just completed and has quoted.The corresponding register renaming mapping table of this instruction completes the mapping that is called non-upper command mappings in the table of a upper instruction of quoting this instruction, and complete in each destination operand address code of quoting an instruction in after the destination operand address code mapping that arranges, the corresponding register renaming mapping table of this instruction is just called the register renaming mapping table of having quoted

This take-off point takes off the corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct, this take-off point can also be taken off to the content that the content of the corresponding register renaming mapping table of having quoted of the Article 1 instruction of the program for carrying out is taken off the corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct as this take-off point.This take-off point takes off the corresponding register renaming mapping table that content this take-off point after this take-off point takes off the content of corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct that the corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct takes off the corresponding register renaming mapping table of the Article 1 instruction of the program for carrying out using this take-off point takes off the Article 1 instruction of the program that another may be correct and has just completed and quoted.This take-off point takes off the corresponding register renaming mapping table that the content of corresponding register renaming mapping table that the corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct takes off the Article 1 instruction of the program for carrying out using this take-off point this take-off point after this take-off point takes off the content of corresponding register renaming mapping table of the Article 1 instruction of the program that another may be correct takes off the Article 1 instruction of the program that another may be correct just also can call the register renaming mapping table of having quoted.

Taking an address code in an instruction as example, and instruction in example is called this instruction, and address code in example is called this address code.

If this address code of this instruction is a source operand address code, the register that register corresponding to the register name of the not rename of this address code of this instruction shines upon out under the mapping of the register renaming mapping table of having quoted corresponding to this instruction is arranging corresponding name, the register name of the rename being just corrected as this address code register name rename of this instruction.

If this address code of this instruction is a destination operand address code, the register that register corresponding to the register name of the not rename of this address code of this instruction shines upon out under the mapping of the register renaming mapping table of having quoted corresponding to this instruction is arranging corresponding name, the register name of the rename being just corrected as this address code register name rename of this instruction, can also give new rename name of this address code register name of this instruction through rename algorithm in addition.

It is worth mentioning that, in data movement instruction or exchange instruction, if this in the data command of some type or exchange instruction not the register name of the source operand address code of rename the register name of the destination operand address code of rename is not different from this, the register that register corresponding to register name of the not rename of the source operand address code of rename do not shine upon out under the mapping of the register renaming mapping table of having quoted corresponding to this instruction of this in this data command is arranging corresponding name, the register name of the register renaming being just corrected as this source operand address Code memory name rename of its this instruction, then the register name of this register renaming that this source operand address code of revised this data command of register name employing of the destination operand address code of rename is not corrected as of this data command is as the register name of this rename that the destination operand address code register name rename of rename is not corrected as, thereby make, the register name of the source operand address code of this rename of revised this data command is identical with the register name of the destination operand address code of this rename.If the register name of the destination operand address code in the data movement instruction of some type or exchange instruction is identical with the register name of source operand address code, this instruction register that the register name correction of the destination operand address code of rename does not adopt under the mapping of register corresponding to the register name of this destination operand address code of its this instruction in the register renaming mapping table of having quoted corresponding to this instruction to shine upon is out arranging corresponding name, the name of the register renaming being corrected as this destination operand address code register name rename of its this instruction revises or this instruction is translated into dummy instruction, but this register mapping table corresponding to this instruction do not revised.

The example for one group of register renaming mapping table of application shown in Fig. 4.Table 1 is the corresponding register renaming mapping table of instruction 1, and the corresponding instruction 1 of table 1.Table 2 is the corresponding register renaming mapping table of instruction 2, and the corresponding instruction 2 of table 2.Table 3 is the corresponding register renaming mapping table of instruction 3, and the corresponding instruction 3 of table 3.Table 4 is the corresponding register renaming mapping table of instruction 4.A, A1, B, B2 represent respectively register.The map information that table 1 records is: A is mapped as A1, and B is mapped as B2.If the name A of the address code of operand appears in the corresponding instruction 1 of table 1, and the name A of the address code of the destination operand of instruction 1 is modified to A2.The mapping mode of table 2 is that A is mapped as A2, and the map information that table 2 records is that A is mapped as A2, and B is mapped as B2.If the name B of the address code of destination operand appears in the corresponding instruction 2 of table 2, and the name B of the address code of the destination operand of instruction 2 is modified to B3.The mapping mode of table 3 is that B is mapped as B3, and the map information that table 3 records is that A is mapped as A2, and B is mapped as B3.If the name A of the address code of destination operand appears in the corresponding instruction 3 of table 3, and in the address of the destination operand of instruction 3, register A corresponding to name is modified to A3.The mapping mode of table 4 is that A is mapped as A3, and the map information that table 4 records is that A is mapped as A3, and B is mapped as B3.It is worth mentioning that, the instruction not source operand address code of rename or the destination operand address code of not rename can be revised according to the record of the corresponding register renaming mapping table of instruction itself.

As shown in Figure 3, rename preprocess method of the present invention further comprises step 1007: the instruction through rename is carried out to instruction fetch.This step 1007 is further comprising the steps:

Step 3001: a correct branched program of confirming this take-off point to be processed.Carry out the jump instruction of a upper instruction of the Article 1 instruction that this take-off point to be processed takes off, obtain the indicated program of this jump instruction, then the correct branched program of this using program indicated this jump instruction as this take-off point to be processed.Or carry out the branch instruction of a upper instruction of the Article 1 instruction that this take-off point to be processed takes off, obtain the indicated program of this branch instruction, then this correct program using program indicated this branch instruction as this take-off point to be processed.

Step 3002: judge that whether this correct branched program is identical with the branched program of the executive routine of this take-off point to be processed.If this correct branched program is identical with the branch of the executive routine of this take-off point to be processed, determine that the branched program that takes off execution from this take-off point to be processed is correct, then performs step 3003.If this correct branched program is different from the executive routine branch of this take-off point to be processed, determine that the branched program that takes off execution from this take-off point to be processed is wrong, then performs step 3005.

Step 3003: judge in this prefetched instruction buffer memory and this performance element buffer memory whether store the branch instruction of taking off from this take-off point to be processed.If stored the branch instruction of taking off from this take-off point to be processed in this prefetched instruction buffer memory and this performance element buffer memory, performed step 3004.Be worth mentioning, the branch instruction of taking off comprises through the instruction of rename and general branch instruction.

Step 3004: stored branch instruction of taking off from this take-off point to be processed from this prefetched instruction buffer memory and this performance element buffer memory is deleted.

Step 3005: judge in this prefetched instruction buffer memory and this performance element buffer memory whether store the branch instruction of taking off from this take-off point to be processed.If stored the branch instruction of taking off from this take-off point to be processed in this prefetched instruction buffer memory and this performance element buffer memory, performed step 3006.If do not stored the branch instruction of taking off from this take-off point to be processed in this prefetched instruction buffer memory and this performance element buffer memory, execution step: 3007.

Step 3006: in the middle of this prefetched instruction buffer memory and this performance element buffer memory take off the branched program taking off at this take-off point that will carry out, carried out in system the executive routine that this take-off point to be processed taken off Article 1 instruction the jump instruction of an instruction or corresponding branched program that branch instruction is confirmed as the branched program taking off from this this take-off point that will carry out of having determined, then after described branched program being taken off, from certain buffer memory, take off again in the middle of this prefetched instruction buffer memory and the unexistent branched program of this performance element buffer memory the jump instruction of a upper instruction of the Article 1 instruction of being carried out the executive routine that this take-off point to be processed taken off in system or the corresponding branched program that branch instruction is confirmed, and the next branch of branch after taking off takes off from certain buffer memory after adopting branch prediction method to confirm again, then the branch instruction of taking off from this take-off point to be processed containing in this prefetched instruction buffer memory and this performance element buffer memory is deleted.It is worth mentioning that the program of taking off in the middle of step 3006 carries out under executive system arranges as an executive routine after taking off.It is worth mentioning that the not instruction of decoding in the instruction of the described branched program that this take-off point takes off, the instruction of not decoding is decoded.To the command operating operating carrying out not rename after decoding, first this register renaming mapping table corresponding to instruction at the beginning of rename is not dealt into the rename unit of being responsible for the rename of processing execution program, then this instruction of not carrying out rename operation is placed on to the rename unit of being responsible for the rename of processing execution program and carries out rename operation.

Step 3007: do not operate.

It is worth mentioning that, in the time carrying out rename operation, the group name that another possible correct program arranges correspondence to each operates for rename, thereby while avoiding the two or more correct programs of another possibility to carry out rename operation, register is used to this identical another name simultaneously.It is worth mentioning that, this group name can be arranged in this rename table.

It is worth mentioning that, after this beginning instruction buffer refitting instruction fetch of program that may be correct in processing this another, in the time processing the instruction fetch of ending instruction buffer, after the beginning instruction buffer refitting of program that may be correct according to processing this another, go back remaining space situation, layout does not have well time and the position of the vacant processing ending instruction buffer input instruction of spatial cache.For example, a buffer memory has been stored A branch, then calculates the number of instructions of A branch, thereby determines input time and the input position of filling up idle space.Then according to filling up this input time of idle space and input position from another buffer memory instruction fetch, to put forward the utilization factor of effect buffer memory.

It is worth mentioning that, in this instruction is stored in to this prefetched instruction buffer memory time, according to the number of instructions of energy use in prefetched instruction buffer memory, layout in advance need be stored in well the number of instructions in this prefetched instruction buffer memory.

It is worth mentioning that, if this another may correct program be conditional branching program, can be by the address information in the corresponding prefetched instruction buffer memory that adds the address of this respective conditions to calculate in this conditional branching program.After condition is carried out, find the corresponding prefetched instruction buffer memory location of instruction to look ahead according to the address information in this prefetched instruction buffer memory.

It is worth mentioning that, if certain branched program is about to be performed, by program locking correct another possibility relevant to this branch.When just preferentially looking for the branched program of locking after branch prediction failure.

Rename preprocess method of the present invention further provides at least one rename unit has been set.This rename unit is for carrying out rename operation.First, this another correct program of possibility be assigned to this rename unit.It is worth mentioning that, if exist multiple this another may be correct program, by each, another may correct program distribute respectively this rename unit.Then, record the rename situation of this take-off point to be processed each register 10 before and the situation of program.Specifically, in this program, before this take-off point to be processed, the original name of each register, and through corrected title after rename operation and the last title of revising.It is worth mentioning that, these situations all can be recorded in this rename table.It is worth mentioning that, at each register, in rename process, the corresponding instruction of another name that each register uses last another name of revising before this take-off point is also recorded in this rename table.It is worth mentioning that, this rename table can be for being recorded in the rename situation of each take-off point each register 10 before and the situation of program.Specifically, in this program, before each take-off point to be processed, the original name of each register, and through corrected title after rename operation and the last title of revising.It is worth mentioning that, these situations all can be recorded in this rename table.Preferably, two rename unit are set.Each rename unit can arrange this corresponding rename table, so that carry out rename operation.This rename table can be by two these rename unit access, to avoid each rename unit to use identical another name when the rename operation of carrying out separately.But this rename list can only be revised by corresponding rename unit.

Foregoing is exemplifying of specific embodiments of the invention, for the wherein not equipment of detailed description and structure, should be understood to take the existing common apparatus in this area and universal method to be implemented.

The above embodiment of the present invention, only for the use of explanation technical solution of the present invention, is only enumerating of technical solution of the present invention simultaneously, is not limited to technical scheme of the present invention and protection domain thereof.Adopt equivalent technologies means, equivalent apparatus etc. to be considered to be and not to exceed the claims in the present invention book and the disclosed scope of instructions the improvement of the claims in the present invention book and the disclosed technical scheme of instructions.

Claims

1. a rename preprocess method, is characterized in that, comprises the following steps:

(A) determine another possibility correct procedure of one in a take-off point;

(B) the correct program of described another possibility of decoding, and one group of instruction that an interim buffer memory obtains for described another possibility correct procedure of storage decoding is set;

2. rename preprocess method as claimed in claim 1, it is characterized in that, wherein, further comprise afterwards step (D) in step (C): one group of performance element buffer memory is set, each performance element buffer memory is corresponding each performance element respectively, for storage described performance element performed corresponding instruction, wherein, the instruction of distributing rename to the corresponding performance element buffer memory of corresponding performance element of the described instruction of rename.To improve the execution efficiency of performance element.

3. rename preprocess method as claimed in claim 1, is characterized in that, described step (D) further comprises step (E) afterwards: the described instruction through rename is carried out to fetching.

4. the rename preprocess method as described in claim 1,2 or 3, is characterized in that, (C) is further comprising the steps for described step:

(C.5): described operation note position confirmation destination operand address code is carried out to rename, i.e. destination register rename;

5. rename preprocess method as claimed in claim 3, is characterized in that, (E) is further comprising the steps for described step:

(E.3) judge in described prefetched instruction buffer memory and described performance element buffer memory whether store the branch instruction of taking off from described take-off point to be processed, if stored the branch instruction of taking off from described take-off point to be processed in described prefetched instruction buffer memory and described performance element buffer memory, execution step (E.4);

(E.7) do not operate.

6. rename preprocess method as claimed in claim 4, is characterized in that, (E) is further comprising the steps for described step:

(E.2) judge that whether described correct branched program is identical with the branched program of the executive routine of described take-off point to be processed, if described correct branched program is identical with the branch of the executive routine of described take-off point to be processed, determine that the branched program taking off from described take-off point to be processed is correct, then execution step (E.3), if described correct branched program is different from the executive routine branch of described take-off point to be processed, determine that the branched program taking off from described take-off point to be processed is wrong, then execution step (E.5),

(E.6) take off described branched program corresponding to described branch instruction as the branched program taking off from the described described take-off point that will carry out of having determined, after the described branched program that will carry out is taken off, the branch instruction of taking off from described take-off point to be processed having in described prefetched instruction buffer memory and described performance element buffer memory is deleted; With

(E.7) do not operate.

7. rename preprocess method as claimed in claim 6, is characterized in that, (A) is further comprising the steps for described step:

(A.1) Branch Processing Unit and at least one record cell are set;

(A.4) deposit conventional described branched program in buffer memory immediately, or in the time taking conventional described branched program, deposit conventional described branched program in buffer memory;

(A.5) remove described in the branched program that is of little use; With

8. rename preprocess method as claimed in claim 5, is characterized in that, (A) is further comprising the steps for described step:

(A.1) Branch Processing Unit and at least one record cell are set;

(A.4) deposit conventional described branched program in buffer memory;

(A.5) remove described in the branched program that is of little use; With

9. rename preprocess method as claimed in claim 7, is characterized in that, wherein, step (A.4) is further comprising the steps:

(A.4.1) a decoding instruction buffer memory is set;

10. rename preprocess method as claimed in claim 4, it is characterized in that, in described destination operand address code not the register mappings in the middle of this occupied register section of the corresponding register of register name of rename to this destination operand address code in not this position sequence number of the corresponding register of register name of rename be in the middle of the register in the middle of the occupied register section of this destination operand address code rename register-bit of same sequence number.

11. rename preprocess methods as claimed in claim 10, it is characterized in that, when the address code of described instruction is source operand address code or destination operand address code, the corresponding name of register that the register renaming mapping table that register of the corresponding not rename register name of the address code of this instruction has been quoted in this instruction shines upon out, the register name of the rename being corrected as the address code register name rename of this instruction.

12. rename preprocess methods as claimed in claim 10, it is characterized in that, described take-off point takes off the content that the corresponding register renaming mapping table of Article 1 instruction of the program that another may be correct takes off the corresponding register renaming mapping table of the Article 1 instruction of another possible correct program for the content of the corresponding register renaming mapping table of the Article 1 instruction of executive routine as described take-off point described take-off point, be that the corresponding register renaming mapping table that described take-off point takes off the Article 1 instruction of the program that another may be correct has just completed and quoted.

13. rename preprocess methods as claimed in claim 10, is characterized in that,

When not being used in the register name of rename in the address code in unenforced executive routine, the register name of selected part in the middle of the register name of rename is cancelled and distributed to unenforced executive routine, after distribute to program that another may be correct and use, and carry out the program rename that another may be correct, and the destination operand address code of the central each not rename of rename is joined the register name of the rename of a possible correct program use

14. rename preprocess methods as claimed in claim 10, is characterized in that,

When another may correct program be conditional branching program, will add in described conditional branching program according to the address information in the address computation of this condition corresponding prefetched instruction buffer memory out;