CN104156049B - Power domain verification device, facility and method - Google Patents
Power domain verification device, facility and method Download PDFInfo
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- CN104156049B CN104156049B CN201410392600.7A CN201410392600A CN104156049B CN 104156049 B CN104156049 B CN 104156049B CN 201410392600 A CN201410392600 A CN 201410392600A CN 104156049 B CN104156049 B CN 104156049B
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Abstract
The invention provides a power domain verification device, facility and method. The device comprises a processing unit, a power switch connected with a power domain unit, a clock signal generation unit, a signal judgment unit, a time storage unit, a process time point comparison unit and a process time calculation unit. The processing unit triggers the power switch according to the power source state information of the power domain unit to connect or disconnect a path for supplying power to the power domain unit. The signal judgment unit converts a power domain control signal into a level signal according to the stimulation of the power domain control signal, the duration time is stored by the time storage unit, the process time point comparison unit judges two adjacent working state time points to determine whether a process is completed or not, and the process time calculation unit calculates the difference of the two adjacent working state time points to determine the time of a power domain for changing the working state. By means of the power domain verification device, facility and method, the power domain power-off working process and the power domain power-on working process are automatically detected, and the aim of judging whether output clamping values are correct or not is achieved.
Description
Technical field
The present invention relates to technical field of power management, particularly relate to a kind of power domain checking device, equipment and method.
Background technology
Along with the rapid increase of SOC scale, the power consumption of control jumbo chip has become as the thorny of chip industry and asks
Topic.Chip being divided into different power domain, being mesh by turn off the power supply of not operating circuit place power domain saving power consumption
Before direct effect the most significantly save power consumption means.But, due to the complex circuit designs of many supply domain, therefore validation difficulty
Greatly.So, the most also lack verification platform the most easily and fast.
Summary of the invention
In view of the above problems, the present invention provides a kind of one overcoming the problems referred to above or at least partly solving the problems referred to above
Power domain checking device, equipment and method.
The present invention provides a kind of power domain checking device, for the duty of control chip multiple power domain unit, and should
Device includes that processing unit and multiple on and off switch, each on and off switch and this power domain unit connect, this processing unit
Power state information according to the power domain unit detected produces corresponding power domain control signal, triggers corresponding power supply and opens
Closing on or off is the path that power domain unit is powered.This device also includes:
Dock signal generation unit, is used for producing clock signal.
Signal judging unit, the electricity that this processing unit is produced by the clock signal produced according to this dock signal generation unit
This power domain control signal is converted to the level signal of correspondence by the incentive action of source domain control signal.
Time memory cell, for storing the level exported by this signal judging unit under the timing effect of a timer
The persistent period of signal.
Flow time point comparing unit, controls letter for obtaining each power domain of storage in this time memory cell respectively
Number time point that adjacent two duties are corresponding, and time point is compared to determine whether corresponding flow process completes.And
Flow time computing unit is adjacent for obtaining each power domain control signal of storage in this time memory cell
The corresponding time point of two duties, and calculate time difference, change duty with true corresponding power territory unit and experienced
Time.
The present invention also provides for a kind of power domain checking equipment, including power supply, and the power domain checking equipment being as above somebody's turn to do.
The present invention also provides for a kind of power domain verification method, and the method includes:
The power supply status of detection power domain unit, and produce corresponding power domain control according to the power state information detected
Signal processed.
Controlling power supply according to the power domain control signal produced is the path that power domain unit is powered.
According to clock signal, this power domain control signal is converted to by the incentive action of power domain control signal correspondence
Level signal.
Timing also preserves persistent period of level signal of output.
Obtain the time point that adjacent two duties of power domain control signal of storage are corresponding respectively, and the time is clicked on
Row compares to determine whether corresponding flow process completes.And
Obtain the corresponding time point of adjacent two duties of power domain control signal of storage, and calculate time difference,
To determine that corresponding power territory changes the time that duty is experienced.
A kind of power domain checking device, equipment and the method that the present invention provides, turns off or on stream by power domain unit
The corresponding time point of adjacent two duties produced in journey and the detection of persistent period obtain corresponding information, and then
Judge that flow process is whether correct, it is achieved thereby that automatically the detection powered-down workflow of power domain, power domain open electricity workflow and
The purpose that output clamp value is the most correct, solves in prior art due to the complex circuit designs of many supply domain, therefore verifies difficulty
Degree is big and cannot fast and effeciently carry out the technical problem verified.
Accompanying drawing explanation
Fig. 1 is the high-level schematic functional block diagram of the power domain checking device in embodiment of the present invention；
Fig. 2 is that the power domain checking device in embodiment of the present invention carries out the functional module of level signal conversion portion and shows
It is intended to；
Fig. 3 be in embodiment of the present invention up and down along the high-level schematic functional block diagram of judgment sub-unit；
Fig. 4 is the schematic flow sheet of the power domain verification method in embodiment of the present invention；
Fig. 5 is that the method sub-process utilizing clock signal to encourage power domain control signal in embodiment of the present invention is shown
It is intended to.
Label declaration:
Equipment 10
Device 100
Dock signal generation unit 101
Signal judging unit 102
Up and down along judgment sub-unit 1021,1022,1023,1024,1025,1026
First order depositor 1027
Second pole depositor 1028
Judge module 1029
Power switch unit 103
Level conversion unit 104
Clamping unit 105
Time memory cell 106
Upper fall time storing sub-units 1061,1062,1063,1064,1065,1066
Timing unit 107
Flow time computing unit 108
Flow time point comparing unit 109
Clamper inspection unit 110
Detection record unit 111
Processing unit 112
Power domain unit 113
Power supply 20
Detailed description of the invention
By describing the technology contents of the present invention, structural feature in detail, being realized purpose and effect, below in conjunction with embodiment
And coordinate accompanying drawing to be explained in detail.
Refer to Fig. 1, verify the high-level schematic functional block diagram of device, this device for the power domain in embodiment of the present invention
To control this SOC difference electricity in 100 electronic equipments 10 that can apply to include SOC (System-on-a-Chip) chip
The duty of source domain.This device 100 includes dock signal generation unit 101, signal judging unit 102, power switch unit
103, level conversion unit 104, clamping unit 105, time memory cell 106, timing unit 107, flow time computing unit
108, flow time point comparing unit 109, clamper inspection unit 110, detection record unit 111 and processing unit 112.
This device 100 also includes multiple power domain unit 113, function treatment on the corresponding chip of each power domain unit 113
Circuit, such as, RTC real-time clock power domain, PMU Power Management Unit power domain, image procossing power domain etc..This electronic equipment
10 include the power subsystem 20 for providing working power for chip.Further, each power domain unit 113 and a power supply
Switch 103 is corresponding to be connected.
This processing unit 112 is used for detecting the power supply status of each power domain unit 113, and according to the power supply shape detected
State information produces corresponding power domain control signal, and wherein, this power domain control signal includes the power domain power supply being sequentially generated
Close electric control signal, power domain clock switch signal, power switch control signal, power domain reset signal, clamp control signals.
Specifically, judge according to the testing result of the power supply status to each power domain unit 113 when this processing unit 112
When needing to close one or more power domain unit 113 (hereinafter referred to as wait closing power domain unit), it is sequentially generated effective electricity
Source domain power supply closes electric control signal, power domain clock switch shutdown signal, invalid power domain reset signal and effective pincers
Position control signal.This processing unit 112 produces this effective power domain power supply and closes electric control signal to turn off the power switch control
Signal, triggers on and off switch 103 and responds this power switch control signal and close, thus cut off the electricity supply 20 for this power supply to be closed
The path of territory unit 113 power supply so that this power domain unit 113 power down to be closed is closed.At this power subsystem 113 to be closed
After supply path cuts off, this processing unit 112 also detects its power supply status and is output as the power state information of closed mode, and
And this clamp units 105 responds this effective clamp control signal and this power subsystem 113 to cut out exports other normal works
The signal of power domain unit 113 made is clamped down at fixing level, to avoid the power domain unit 113 not having power supply 20 to power can
The power domain unit 113 of other normal work is impacted by the random level that can export.
When according to the testing result of the power supply status to each power domain unit 113, this processing unit 112 judges that needs are opened
When opening one or more power domain unit 113 (power domain unit the most to be opened), it is sequentially generated invalid power domain electricity
Electric control signal, effective power domain reset signal, invalid clamp control signal and invalid power domain reset letter are closed in source
Number.This processing unit 112 produces this invalid power domain power supply and closes electric control signal to turn on the power switch control signal, triggers
On and off switch 103 responds this power switch control signal and opens, thus connects power supply 20 for this power domain unit 113 to be opened
Supply path so that this power-on territory unit 113 works on power.It is effective that this power domain unit 113 to be opened is also responsive to this
Power domain reset signal reset so that circuit can the most normally work after the power-up, and responds this nothing after unlatching
The power domain reset signal of effect cancels reset.
This level conversion unit 104 is for carrying out voltage conversion between different electrical power territory unit 113 so that different electrical power
Can be with proper communication between territory unit 113.
Further, during on power domain unit 113, electric-opening or power down are closed, this dock signal generation unit
101 produce clock signal, and in the present embodiment, this dock signal generation unit 101 is high frequency clock signal generation unit, use
In producing high frequency clock signal.The clock signal pair that this signal judging unit 102 produces according to this dock signal generation unit 101
This power domain control signal is converted to the level of correspondence by the incentive action of the power domain control signal that this processing unit 112 produces
Signal, and, pre-set varying level signal effective or effective when trailing edge when rising edge.Such as, pre-set
Power domain power supply closes electric control signal when rising edge level effectively, and is invalid when trailing edge level, works as power domain
Power supply closes electric control signal and exports rising edge level through the excitation of the clock signal of this dock signal generation unit 101 generation
During signal, then this power domain power supply closes electric control signal is effective.Thus, as it has been described above, at this signal judging unit 102
Under process, the power domain control signal produced by processing unit 112 is converted to utilize rising edge level signal or trailing edge level
Its effectiveness of characterization is relevant with show in this device 100 in electric-opening in each power domain 113 or power down closing process
Status information, as power domain reset, power domain are clamped down on.
This time memory cell 106 stores the electricity exported by signal judging unit 102 under the timing effect of timer 107
Ordinary mail duration, i.e. become the time that trailing edge level signal is experienced from rising edge level signal, or from decline
The time that rising edge level signal is experienced is become along level signal.
Please refer to Fig. 2, this signal judging unit 102 include up and down along judgment sub-unit 1021,1022,1023,
1024,1025 and 1026, this time memory cell 106 include fall time storing sub-units 1061,1062,1063,
1064,1065 and 1066.Below with up and down along judgment sub-unit 1021 with upper fall time storing sub-units 1061 to power supply
Territory power supply closes as a example by electric control signal processes and is described in detail, and wherein, pre-sets this power domain power supply and closes electric control
Signal is that rising edge level is effective.
This clock signal produced along judgment sub-unit 1021 according to this dock signal generation unit 101 up and down is to this power supply
Territory power supply closes the excitation of electric control signal and exports corresponding rising edge level signal or trailing edge level signal.When output rising edge
During level signal, then show that the power domain unit 113 in device 100 is in power down closing process, when output trailing edge level
During signal, then show that the power domain unit 113 in device 100 is in and power in opening process.
Please refer to Fig. 3, in embodiment of the present invention up and down along the high-level schematic functional block diagram of judgment sub-unit, often
Individual all include up and down first order depositor the 1027, second pole depositor 1028 and judge module 1029 along judgment sub-unit.With
Sample, to enter power domain power supply pass electric control signal along judgment sub-unit 1021 with upper fall time storing sub-units 1061 up and down
Row is described in detail as a example by processing.
This first order depositor 1027 receives power domain and closes electric control signal and clock signal, this second level depositor
1028 value receiving the output of this first order depositor 1027 and clock signals, this judge module 1029 is deposited according to this second level
The value of device 1028 output is carried out up and down along the judgement of level signal.In the present embodiment, export when first order depositor 1027
Value be value high, the output of this second level depositor 1028 when being low, then judge module 1029 is defined as rising edge level signal.
When the value that the value of first order depositor 1027 output is the output of low, second level depositor 1028 is high, then this judge module
1029 are defined as trailing edge level signal.
On this, fall time storing sub-units 1061 preserves its duration according to the level signal of output.
Similarly, when this receives power domain along judgment sub-unit 1022,1023,1024,1025 and 1026 is corresponding up and down
The power supply status letter of clock switching signal, clamp control signals, power switch control signal, power domain reset signal and power supply
Cease, and the clock signal produced by dock signal generation unit 101 respectively as described above encourages and exports corresponding rising edge
Signal or trailing edge signal.Fall time storing sub-units 1061,1062,1063,1064,1065 and 1066 root respectively on this
Timing effect record correspondence rising edge signal or the persistent period of trailing edge signal according to timer 107.
This flow time point comparing unit 109 obtains each power domain control of storage in this time memory cell 106 respectively
The time point that adjacent two duties of signal processed are corresponding, and time point is compared to determine whether corresponding flow process completes,
That is, being considered as correct order when the time point of a rear duty is more than the time point of previous duty, flow process is complete
Become, otherwise output error state.
This flow time computing unit 108 obtains each power domain control signal of storage in this time memory cell 106
The corresponding time point of adjacent two duties, and calculate time difference, with true corresponding power territory unit 113 from upper electric-opening shape
The time that state is experienced to power down closed mode, or the time experienced from power down closed mode supreme electric-opening state.
This detection record unit 111 is for recording time and this flow process that this flow time point computing unit 108 determines
The judged result of time point comparing unit 109 output.
In the present embodiment, in the power domain control signal that processing unit 112 is produced by this clamper inspection unit 110
Clamp control signals detects, to judge whether it meets expected value, so that it is determined that this is waited to close electricity by this clamp units 105
Clamper testing result the most effectively, is sent in this detection record unit 111 preserve by the effect of clamping down on of source unit 113 simultaneously.
Referring to Fig. 4, for the schematic flow sheet of the power domain verification method in embodiment of the present invention, the method includes:
Step S30, this processing unit 112 detects the power supply status of each power domain unit 113, and according to the electricity detected
Source status information produces corresponding power domain control signal.
Wherein, this power domain control signal includes that the power domain power supply being sequentially generated closes electric control signal, power domain clock
Switching signal, power switch control signal, power domain reset signal, clamp control signals.
When this processing unit 112 judges to need to close according to the testing result of the power supply status to each power domain unit 113
When closing one or more power domain unit 113 (hereinafter referred to as wait closing power domain unit), it is sequentially generated effective power domain electricity
Source is closed electric control signal, power domain clock switch shutdown signal, invalid power domain reset signal and effectively clamps control
Signal.
When according to the testing result of the power supply status to each power domain unit 113, this processing unit 112 judges that needs are opened
When opening one or more power domain unit 113 (power domain unit the most to be opened), it is sequentially generated invalid power domain electricity
Electric control signal, effective power domain reset signal, invalid clamp control signal and invalid power domain reset letter are closed in source
Number.
Step S31, this processing unit 112 opens or closes power supply according to the power domain power supply pass electric control signal produced and opens
Close control signal, trigger on and off switch 103 and respond this power switch control signal and be turned on and off, thus control power supply 20 and be
The supply path of this power domain unit 113 to be opened.
This processing unit 112 produces this effective power domain power supply and closes electric control signal to turn off the power switch control letter
Number, trigger on and off switch 103 and respond this power switch control signal and close, thus cut off the electricity supply 20 for this power domain to be closed
The path of unit 113 power supply so that this power domain unit 113 power down to be closed is closed.
This processing unit 112 produces this invalid power domain power supply and closes electric control signal to turn on the power switch control letter
Number, trigger on and off switch 103 and respond this power switch control signal and open, thus connect power supply 20 for this power domain to be opened
The supply path of unit 113 so that this power-on territory unit 113 works on power.
Step S32, the clock signal that this signal judging unit 102 produces according to this dock signal generation unit 101 is to this
This power domain control signal is converted to the level letter of correspondence by the incentive action of the power domain control signal that processing unit 112 produces
Number.
Wherein, varying level signal is pre-set effective or effective when trailing edge when rising edge.Such as, set in advance
Put power domain power supply pass electric control signal effective when rising edge level, and be invalid when trailing edge level, work as power supply
Territory power supply closes electric control signal and exports rising edge electricity through the excitation of the clock signal of this dock signal generation unit 101 generation
During ordinary mail, then this power domain power supply closes electric control signal is effective.Thus, as it has been described above, at this signal judging unit 102
Process under, the power domain control signal produced by processing unit 112 is converted to utilize rising edge level signal or trailing edge electricity
Its effectiveness of flat characterization, to show in this device 100 electric-opening in each power domain 113 or the phase in power down closing process
Off status information, as power domain reset, power domain are clamped down on.
Please refer to Fig. 5, this step S32 also includes following sub-step:
Sub-step S320, this first order depositor 1027 is defeated according to the power domain control signal received and clock signal
Go out corresponding value.
Sub-step S321, value and clock that this second level depositor 1028 exports according to this first order depositor 1027 are believed
Number corresponding value of output.
Sub-step S322, this judge module 1029 is carried out up and down along level according to the value that this second level depositor 1028 exports
The judgement of signal.
In the present embodiment, export for high, this second level depositor 1028 when the value of first order depositor 1027 output
Value when being low, then judge module 1029 is defined as rising edge level signal.When first order depositor 1027 output value be low,
When the value of second level depositor 1028 output is high, then this judge module 1029 is defined as trailing edge level signal.
Step S33, this time memory cell 106 stores by signal judging unit 102 under the timing effect of timer 107
The level signal duration of output.
This level signal duration by becoming, from rising edge level signal, the time that trailing edge level signal is experienced,
Or become, from trailing edge level signal, the time that rising edge level signal is experienced.
Step S34, this flow time point comparing unit 109 obtains in this time memory cell 106 each of storage respectively
The time point that adjacent two duties of power domain control signal are corresponding, and time point is compared to determine corresponding flow process is
No complete.
Wherein, when the time point of a rear duty is more than the time point of previous duty, this flow time point compares
Unit 109 thinks that flow process is correct order, and flow process completes, otherwise output error state.
Step S35, this flow time computing unit 108 obtains each power domain of storage in this time memory cell 106
The corresponding time point of adjacent two duties of control signal, and calculate time difference, with true corresponding power territory unit 113 from upper
The time that electric-opening state is experienced to power down closed mode, or experienced from power down closed mode supreme electric-opening state
Time.
Step S36, this detection record unit 111 records time that this flow time point computing unit 108 determines and should
The judged result of flow time point comparing unit 109 output.
In the present embodiment, in the power domain control signal that processing unit 112 is produced by this clamper inspection unit 110
Clamp control signals detects, to judge whether it meets expected value, so that it is determined that this is waited to close electricity by this clamp units 105
Clamper testing result the most effectively, is sent in this detection record unit 111 preserve by the effect of clamping down on of source unit 113 simultaneously.
A kind of power domain checking device, equipment and the method that the present invention provides, turns off or on stream by power domain unit
The corresponding time point of adjacent two duties produced in journey and the detection of persistent period obtain corresponding information, and then
Judge that flow process is whether correct, it is achieved thereby that automatically the detection powered-down workflow of power domain, power domain open electricity workflow and
The purpose that output clamp value is the most correct, solves in prior art due to the complex circuit designs of many supply domain, therefore verifies difficulty
Degree is big and cannot fast and effeciently carry out the technical problem verified.
The foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, every utilize this
Equivalent structure or equivalence flow process that bright description and accompanying drawing content are made convert, or are directly or indirectly used in other relevant skills
Art field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (13)
1. a power domain checking device, for the duty of control chip multiple power domain unit, described device includes place
Managing unit and multiple on and off switch, described in each on and off switch and, power domain unit connects, and described processing unit is according to inspection
The power state information of the power domain unit measured produces corresponding power domain control signal, triggers the conducting of corresponding on and off switch
Or it is cut to the path that power domain unit is powered；It is characterized in that, described device also includes:
Dock signal generation unit, is used for producing clock signal；
Signal judging unit, the electricity that described processing unit is produced by the clock signal produced according to described dock signal generation unit
Described power domain control signal is converted to the level signal of correspondence by the incentive action of source domain control signal；
Time memory cell, for storing the level letter exported by described signal judging unit under the timing effect of a timer
Number persistent period；
Flow time point comparing unit, for obtaining each power domain control signal of storage in described time memory cell respectively
The time point that adjacent two duties are corresponding, and time point is compared to determine whether corresponding flow process completes；And
Flow time computing unit, for obtaining each power domain control signal adjacent two of storage in described time memory cell
The corresponding time point of individual duty, and calculate time difference, to determine that corresponding power territory unit changes duty and experienced
Time.
2. power domain checking device as claimed in claim 1, it is characterised in that described device also includes:
Detection record unit, compares for recording time that described flow time point computing unit determines and described flow time
The judged result of unit output.
3. power domain checking device as claimed in claim 1, it is characterised in that described power domain control signal includes producing successively
Raw power domain power supply closes electric control signal, power domain clock switch signal, power switch control signal, power domain reset letter
Number, clamp control signals.
4. power domain checking device as claimed in claim 3, it is characterised in that described device also includes:
Clamp units, is used for that when a power domain unit is closed the power domain unit of described closedown is exported other and normally works
The signal of power domain unit clamp down at fixing level.
5. power domain checking device as claimed in claim 4, it is characterised in that described device also includes:
Clamper inspection unit, the clamp control signals in the power domain control signal producing described processing unit is examined
Survey, to judge whether it meets expected value, so that it is determined that described clamp units is treated and closed whether clamping down on of power subsystem acts on
Effectively.
6. power domain checking device as claimed in claim 3, it is characterised in that described signal judging unit includes described in correspondence
In power domain control signal each signal arrange up and down along judgment sub-unit, described time memory cell include corresponding described on
The lower upper fall time storing sub-units being correspondingly arranged along judgment sub-unit；Each described include along judgment sub-unit up and down:
First order depositor, is used for receiving described power domain control signal and clock signal,
Second pole depositor, for receiving value and the clock signal of the output of described first order depositor；And
Judge module, for carrying out up and down along the judgement of level signal according to the value of described second pole depositor output.
7. a power domain checking equipment, including power supply, it is characterised in that include as described in claim 1～6 any one
Power domain checking device.
8. a power domain verification method, it is characterised in that described method includes:
The power supply status of detection power domain unit, and produce corresponding power domain control letter according to the power state information detected
Number；
Controlling power supply according to the power domain control signal produced is the path that power domain unit is powered；
According to clock signal, described power domain control signal is converted to by the incentive action of power domain control signal the electricity of correspondence
Ordinary mail number；
Timing also preserves persistent period of level signal of output；
Obtain the time point that adjacent two duties of power domain control signal of storage are corresponding respectively, and time point is compared
Relatively to determine whether corresponding flow process completes；And
Obtain the corresponding time point of adjacent two duties of power domain control signal of storage, and calculate time difference, with really
Determine corresponding power territory and change the time that duty is experienced.
9. power domain verification method as claimed in claim 8, it is characterised in that described method also includes:
Record described power domain and change the time that duty is experienced and the judged result that whether flow process completes accordingly.
10. power domain verification method as claimed in claim 8, it is characterised in that described according to clock signal to power domain control
The step of the level signal that described power domain control signal is converted to correspondence by the incentive action of signal processed includes:
By first order register root according to the power domain control signal received and the corresponding value of clock signal output；
The value exported according to described first order depositor by second level register root and the corresponding value of clock signal output；And
Value according to the output of described second level depositor is carried out up and down along the judgement of level signal.
11. power domain verification methods as claimed in claim 8, it is characterised in that described power domain control signal includes successively
The power domain power supply produced closes electric control signal, power domain clock switch signal, power switch control signal, power domain reset letter
Number, clamp control signals.
12. power domain verification methods as claimed in claim 11, it is characterised in that described according to the power domain control letter produced
Number control power supply be the path that power domain unit is powered step after also include:
When a power domain unit is closed, the power domain unit of described closedown is exported other power domain unit normally worked
Signal clamp down at fixing level.
13. power domain verification methods as claimed in claim 12, it is characterised in that described method also includes:
Clamp control signals in described power domain control signal is detected, to judge whether it meets expected value, thus
Determine treat close power subsystem clamp down on effect the most effective.
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| CN104914967B (en) * | 2015-06-10 | 2018-01-26 | 福州瑞芯微电子股份有限公司 | The reset control method and device of power domain |
| CN113330388B (en) * | 2019-12-30 | 2023-06-13 | 成都海光集成电路设计有限公司 | Chip design method, chip design device, chip and electronic equipment |
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| CN103838892A (en) * | 2012-11-26 | 2014-06-04 | 飞思卡尔半导体公司 | Multi-voltage-domain circuit design verification method |
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