CN104133088A - Method of testing voltage sag of to-be-tested device - Google Patents
Method of testing voltage sag of to-be-tested device Download PDFInfo
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- CN104133088A CN104133088A CN201310159029.XA CN201310159029A CN104133088A CN 104133088 A CN104133088 A CN 104133088A CN 201310159029 A CN201310159029 A CN 201310159029A CN 104133088 A CN104133088 A CN 104133088A
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Abstract
The invention discloses a method of testing voltage sag of a to-be-tested device. the method comprises steps: an operation device carries out a test program so as to generate a group of control instructions to be transmitted to a power supply device; the power supply device generates a rated voltage or a sag voltage in each time interval to be supplied to the to-be-tested device according to the group of control instructions; the to-be-tested device generates a corresponding response voltage to be transmitted to a load simulator according to the rated voltage or the sag voltage; the load simulator measures the response voltage and transmits the response voltage to the operation device; and the operation device judges whether the response voltage is within the normal response voltage range, and if not, the operation device records the corresponding failure information to a database.
Description
Technical field
The present invention relates to a kind of method of testing, particularly relate to a kind of for testing the method for testing of the voltage dip of device to be measured.
Background technology
Electric equipment products in use, if while having the problem such as power-off, voltage supply deficiency and circuit overload to occur, easily cause that electric appliance component is aging, damage or fault.In view of this, many countries have all required product by the test of Electro Magnetic Compatibility (Electro Magnetic Compatibility), just can come into the market to sell.The electromagnetic compatibility rules of various countries are to be all derived from international rules (IEC Standard) at present, and in these rules of IEC61000-4-11, it provides following test specification to voltage dip (Voltage Dip):
■ rated voltage rapid drawdown 30% continues the 0.5AC cycle, repeats 10 times.
Each AC cycle step rated voltage rapid drawdown 60% of ■ continues the 0.5AC cycle to 500 millisecond, repeats 10 times.
Each AC cycle step rated voltage rapid drawdown 100% of ■ continues the 0.5AC cycle to 5000 millisecond, repeats 10 times.
In the past for the test practice of these rules of IEC61000-4-11 for a source of sound disc is put into a DVD player, when this DVD player reads and changes and then drive a driving governor (ON/OFFController) to control at random the duration of single port output AC power source supply output voltage producing random source of sound while moving, to drive a device action to be measured.This device to be measured is also electrically connected to a loads simulator that is used for measuring the output voltage of this device to be measured.When output voltage is not within the scope of normal voltage, this loads simulator can flash the redlight, and tester must be to its record in addition, this kind of practice need be bought expensive device, as DVD player, driving governor, and tester will constantly stare at this loads simulator to record bright light information, not only labor intensive, also misregistration likely.In addition, because this DVD player and this driving governor can only be controlled when output voltage of this list port output AC power source supply, or output voltage when not, it is the situation of one of voltage dip percentage hundred, but when tester wants test voltage rapid drawdown 30 percent or 60 percent, can only manually remove to adjust the output voltage of this list port output AC power source supply with the situation of emulation voltage dip by tester, real genus inconvenience, therefore, be necessary seeking solution.
Summary of the invention
The object of the present invention is to provide a kind of for testing the method for testing of the voltage dip of device to be measured.
The present invention comprises for testing the method for testing of voltage dip of device to be measured: (A) arithmetic unit is carried out a test procedure, to produce one group of steering order, is sent to a power supply unit that is electrically connected on this arithmetic unit; (B) this power supply unit is organized steering order according to this, in a very first time interval, produces a rated voltage and is supplied to a device to be measured; (C) this device to be measured, according to this rated voltage, produces one first response voltage and is sent to a loads simulator being electrically connected to this arithmetic unit and device to be measured; (D) this loads simulator measures this first response voltage and is sent to this arithmetic unit; (E) this arithmetic unit judges that this first response voltage is whether in a normal response voltage range, if result of determination is no, this arithmetic unit by a Fisrt fault information recording in a database; (F) this power supply unit is organized steering order according to this, in one second time interval, produces a slump voltage and is supplied to this device to be measured, and wherein this slump voltage is less than this rated voltage; (G) this device to be measured, according to this slump voltage, produces one second response voltage and is sent to this loads simulator; (H) this loads simulator measures this second response voltage and is sent to this arithmetic unit; And (I) this arithmetic unit judges that this second response voltage is whether in this normal response voltage range, if result of determination is no, this arithmetic unit is recorded in one second failure message in this database.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, this loads simulator is one to comprise a variable-resistance digital electric meter.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, this power supply unit and loads simulator all comprise a general purpose interface bus interface card, for the data transmission interface card as between this arithmetic unit and this power supply unit and loads simulator.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, this arithmetic unit is one to comprise the computing machine of storer of a processor and this test procedure of storage.
Of the present inventionly for testing the method for testing of the voltage dip of device to be measured, also comprise, in this (D) step, one oscillograph being electrically connected to this arithmetic unit and device to be measured measures the one first response voltage waveform corresponding to this first response voltage, and the first response voltage waveform being measured is sent to this arithmetic unit, then this arithmetic unit by this first response voltage waveform recording in this database.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, this oscillograph comprises a general purpose interface bus interface card, for the data transmission interface card as between this arithmetic unit and oscillograph.
Of the present inventionly for testing the method for testing of the voltage dip of device to be measured, also comprise, in this (H) step, this oscillograph measures the one second response voltage waveform corresponding to this second response voltage, and the second response voltage waveform being measured is sent to this arithmetic unit, then this arithmetic unit by this second response voltage waveform recording in this database.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 30%.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 60%.
Of the present invention for testing the method for testing of the voltage dip of device to be measured, the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 100%.
Beneficial effect of the present invention is: by this arithmetic unit, produce this group steering order and make this power supply unit in this very first time interval, produce this rated voltage and in this second time interval, produce this slump voltage, and do not need manual adjustment.In addition, the present invention is also recorded in this database by this arithmetic unit by this Fisrt fault information and the second failure message and reaches self registering object.
Accompanying drawing explanation
Fig. 1 is a system architecture diagram, illustrates for implementing the present invention for testing the test macro of preferred embodiment of method of testing of the voltage dip of device to be measured;
Fig. 2 is a process flow diagram, illustrates that the present invention is for testing the preferred embodiment of method of testing of the voltage dip of device to be measured;
Fig. 3 is a process flow diagram, and the detailed step of one first test period of one first test phase is described;
Fig. 4 is a process flow diagram, and the detailed step of one first test period of one second test phase is described; And
Fig. 5 is a process flow diagram, and the detailed step of one first test period of one the 3rd test phase is described.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail.
Refer to Fig. 1, the present invention implements with a test macro for testing the preferred embodiment of method of testing of the voltage dip of device to be measured.This test macro comprises an arithmetic unit 1, a power supply unit 2, a loads simulator 3, an oscillograph 4 and a database 5.
This arithmetic unit 1 is carried out a test procedure 13, to produce one group of steering order, is sent to this power supply unit 2 being electrically connected to this arithmetic unit 1.In this preferred embodiment, this arithmetic unit 1 is a computing machine, and comprises the storer 12 of a processor 11 and this test procedure 13 of storage.
This power supply unit 2 comprises that one for carrying out general purpose interface bus (the General Purpose Interface Bus of itself and this 1 data transmission of arithmetic unit, hereinafter to be referred as GPIB) interface card 21, and this power supply unit 2 is according to this group steering order, in each time interval, produce a rated voltage or slump voltage and be supplied to this device 9 to be measured.This device 9 to be measured, again according to this rated voltage or slump voltage, produces a corresponding response voltage.In this preferred embodiment, this power supply unit 2 is the output AC power source supply of port more than, and a plurality of device to be measured 9 this rated voltage or slump voltage can be provided simultaneously.
This loads simulator 3 is electrically connected to this arithmetic unit 1 and device to be measured 9, and comprise that one for carrying out and the gpib interface card 31 of 1 data transmission of this arithmetic unit, and this loads simulator 3 is for measuring this device 9 to be measured at corresponding this response voltage of each time interval, and be sent to this arithmetic unit 1, in this preferred embodiment, this loads simulator 3 is one to comprise the digital electric meter of a variable resistor (not shown).
This oscillograph 4 is electrically connected to this arithmetic unit 1 and device to be measured 9, and comprise one for as and the gpib interface card 41 of 1 data transmission of this arithmetic unit, and this oscillograph 4 is for measuring this device 9 to be measured at the corresponding response voltage waveform of each time interval, and be sent to this arithmetic unit 1.
This arithmetic unit 1 also for judge this device 9 to be measured at corresponding this response voltage of each time interval whether in a normal response voltage range, if result of determination is no, this arithmetic unit 1 is recorded in a failure message of correspondence in this database 5.Wherein this corresponding failure message comprises that this rated voltage of supplying at this power supply unit 2 of each time interval or slump voltage, this loads simulator 3 measure this corresponding response voltage, this oscillograph 4 measures one of this corresponding response voltage waveform and this arithmetic unit 1 correspondence and judges fail result.In this preferred embodiment, this arithmetic unit 1 also can record this device 9 to be measured at corresponding this response voltage of each time interval in this normal response voltage range one by information in this database 5.Wherein should be included in this rated voltage that this power supply unit 2 of each time interval supplies or slump voltage, this corresponding response voltage that this loads simulator 3 measures, this corresponding response voltage waveform that this oscillograph 4 measures and a judgement of this arithmetic unit 1 correspondence by information and pass through result.Wherein, this normal response voltage range is for for example, if the output voltage of this device 9 to be measured is 24 volts, this normal response voltage range is 21.6 volts～26.4 volts of the positive and negative 10%(of 24 volts).Yet described 24 volts is only for example, in other embodiments of the invention, this normal response voltage range can, according to different device 9 changes to be measured, not be limited with the present embodiment.
Result is passed through in corresponding this judgement fail result or judgement that this database 5 is judged for this rated voltage of storing this power supply unit 2 of each time interval and supplying or slump voltage, this corresponding response voltage that this loads simulator 3 measures, this corresponding response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1.
In this preferred embodiment, the number of this device 9 to be measured is one.Yet, because this power supply unit 2 is the output AC power source supply of port more than, therefore, in other embodiments of the invention, also can be a plurality of devices to be measured 9, and according to the quantity correspondence of device 9 to be measured, increase the quantity of this loads simulator 3.
Consult Fig. 2, corresponding to system of the present invention, the present invention for the preferred embodiment of method of testing of voltage dip of testing device to be measured for to carry out the following step according to the standard of these rules of IEC61000-4-11.
As shown in step 60, this arithmetic unit 1 is carried out this test procedure 13, to produce this group steering order, is sent to this power supply unit 2.
Then,, as shown in step 61, this test macro is carried out one first test phase.
Wherein, as shown in step 610, this test macro carries out one first test period of this first test phase.
Consult Fig. 3, further describe the detailed process of step 610, as shown in step 701, this power supply unit 2, according to this group steering order, in a very first time interval, produces a rated voltage and is supplied to this device 9 to be measured.Then,, as shown in step 702, this device 9 to be measured, according to this rated voltage, produces one first response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 703, the one first response voltage waveform that these loads simulator 3 these first response voltages of measurement and this oscillograph 4 measure corresponding to this first response voltage, and respectively this first response voltage being measured and the first response voltage waveform are sent to this arithmetic unit 1.
As shown in step 704, this arithmetic unit 1 judges that this first response voltage is whether in a normal response voltage range; If so, proceed the processing of step 705; Otherwise, proceed the processing of step 706.
As shown in step 705, this arithmetic unit 1 by one first by information recording in this database 5, wherein this first is included in one first of this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage that this loads simulator 3 measures, this first response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information very first time and judges and pass through result.
As shown in step 706, this arithmetic unit 1 is by a Fisrt fault information recording in this database 5, and wherein this Fisrt fault information is included in this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage, this oscillograph 4 that this loads simulator 3 measures very first time and measures one first of this first response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
As shown in step 707, this power supply unit 2, according to this group steering order, in one second time interval, produces a slump voltage and is supplied to this device 9 to be measured, and wherein this slump voltage is less than this rated voltage.Then,, as shown in step 708, this device 9 to be measured, according to this slump voltage, produces one second response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 709, the one second response voltage waveform that these loads simulator 3 these second response voltages of measurement and this oscillograph 4 measure corresponding to this second response voltage, and respectively this second response voltage being measured and the second response voltage waveform are sent to this arithmetic unit 1.
As shown in step 710, this arithmetic unit 1 judges that this second response voltage is whether in a normal response voltage range; If so, proceed the processing of step 711; Otherwise, proceed the processing of step 712.
As shown in step 711, this arithmetic unit 1 by one second by information recording in this database 5, wherein this second is included in one second of this slump voltage that this power supply unit 2 of this second time interval supplies, this second response voltage that this loads simulator 3 measures, this second response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information and judges and pass through result.
As shown in step 712, this arithmetic unit 1 is recorded in one second failure message in this database 5, and wherein this second failure message comprises that this second response voltage, this oscillograph 4 that this slump voltage of supplying at this power supply unit 2 of this second time interval, this loads simulator 3 measure measure one second of this second response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
Consult Fig. 2 and Fig. 3, wherein, as shown in step 611～619, this test macro carries out one second test period, one the 3rd test period, one the 4th test period, one the 5th test period, one the 6th test period, one the 7th test period, one the 8th test period, one the 9th test period of this first test phase until 1 the tenth test period, wherein this second test period to the tenth test period its detailed process be similar to this first test period of this first test phase, perform step 701～712, so no longer repeat in this.It is worth mentioning that, in this preferred embodiment, each second time interval of this first test phase is all the 0.5AC cycle, and the frequency of the voltage that this power supply unit 2 provides is 50Hz, therefore, each second time interval of this first test phase is 10 milliseconds.Yet described 50Hz, only for this preferred embodiment, in other embodiments, can change according to the actual electric voltage frequency providing of this power supply unit 2, not as limit.In addition, each rated voltage of this first test phase and the difference between each slump voltage and the ratio of each rated voltage are all 30%.
Then,, as shown in step 62, this test macro is carried out one second test phase.
Wherein, as shown in step 620, this test macro carries out one first test period of this second test phase.
Consult Fig. 4, further describe the detailed process of step 620, as shown in step 713, this power supply unit 2, according to this group steering order, in a very first time interval, produces a rated voltage and is supplied to this device 9 to be measured.Then,, as shown in step 714, this device 9 to be measured, according to this rated voltage, produces one first response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 715, the one first response voltage waveform that these loads simulator 3 these first response voltages of measurement and this oscillograph 4 measure corresponding to this first response voltage, and respectively this first response voltage being measured and the first response voltage waveform are sent to this arithmetic unit 1.
As shown in step 716, this arithmetic unit 1 judges that this first response voltage is whether in a normal response voltage range; If so, proceed the processing of step 717; Otherwise, proceed the processing of step 718.
As shown in step 717, this arithmetic unit 1 by one first by information recording in this database 5, wherein this first is included in one first of this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage that this loads simulator 3 measures, this first response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information very first time and judges and pass through result.
As shown in step 718, this arithmetic unit 1 is by a Fisrt fault information recording in this database 5, and wherein this Fisrt fault information is included in this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage, this oscillograph 4 that this loads simulator 3 measures very first time and measures one first of this first response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
As shown in step 719, this power supply unit 2, according to this group steering order, in one second time interval, produces a slump voltage and is supplied to this device 9 to be measured, and wherein this slump voltage is less than this rated voltage.Then,, as shown in step 720, this device 9 to be measured, according to this slump voltage, produces one second response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 721, the one second response voltage waveform that these loads simulator 3 these second response voltages of measurement and this oscillograph 4 measure corresponding to this second response voltage, and respectively this second response voltage being measured and the second response voltage waveform are sent to this arithmetic unit 1.
As shown in step 722, this arithmetic unit 1 judges that this second response voltage is whether in a normal response voltage range; If so, proceed the processing of step 723; Otherwise, proceed the processing of step 724.
As shown in step 723, this arithmetic unit 1 by one second by information recording in this database 5, wherein this second is included in one second of this slump voltage that this power supply unit 2 of this second time interval supplies, this second response voltage that this loads simulator 3 measures, this second response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information and judges and pass through result.
As shown in step 724, this arithmetic unit 1 is recorded in one second failure message in this database 5, and wherein this second failure message comprises that this second response voltage, this oscillograph 4 that this slump voltage of supplying at this power supply unit 2 of this second time interval, this loads simulator 3 measure measure one second of this second response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
As shown in step 725, this test procedure 13 increases by a fixed cycle by this second time interval.
As shown in step 726, this test procedure 13 judges whether this second time interval is greater than a Preset Time; If so, proceed the processing of step 727; Otherwise, proceed the processing of step 713.
As shown in step 727, this test procedure 13 is initialized as an initial time by this second time interval.
Consult Fig. 2 and Fig. 4, wherein, as shown in step 621～629, this test macro carries out one second test period, one the 3rd test period, one the 4th test period, one the 5th test period, one the 6th test period, one the 7th test period, one the 8th test period, one the 9th test period of this second test phase until 1 the tenth test period, wherein this second test period to the tenth test period its detailed process be similar to this first test period of this second test phase, perform step 713～727, so no longer repeat in this.Wherein each test period all has a plurality of test subcycles, from step 713～724, be a test subcycle, in each test period, carry out step 713 for the first time～724 be one first test subcycle, carry out step 713 for the second time～724 be one second test subcycle, the rest may be inferred.In this preferred embodiment, the second time interval of each the first test subcycle of this second test phase is all the 0.5AC cycle (10 milliseconds), and each fixed cycle of this second test phase is all the 0.5AC cycle, each Preset Time is all 500 milliseconds and each initial time and is all the 0.5AC cycle, therefore, each test period of this second test phase all has 50 test subcycles, and (the second time interval of each the first test subcycle is all 10 milliseconds, the second time interval of each the second test subcycle is all 20 milliseconds, the second time interval of each the 3rd test subcycle is all 30 milliseconds, the second time interval of each the 50 test subcycle is all 500 milliseconds), in addition, each rated voltage of this second test phase and the difference between each slump voltage and the ratio of each rated voltage are all 60%.
Then,, as shown in step 63, this test macro is carried out one the 3rd test phase.
Wherein, as shown in step 630, this test macro carries out one first test period of the 3rd test phase.
Consult Fig. 5, further describe the detailed process of step 630, as shown in step 728, this power supply unit 2, according to this group steering order, in a very first time interval, produces a rated voltage and is supplied to this device 9 to be measured.Then,, as shown in step 729, this device 9 to be measured, according to this rated voltage, produces one first response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 730, the one first response voltage waveform that these loads simulator 3 these first response voltages of measurement and this oscillograph 4 measure corresponding to this first response voltage, and respectively this first response voltage being measured and the first response voltage waveform are sent to this arithmetic unit 1.
As shown in step 731, this arithmetic unit 1 judges that this first response voltage is whether in a normal response voltage range; If so, proceed the processing of step 732; Otherwise, proceed the processing of step 733.
As shown in step 732, this arithmetic unit 1 by one first by information recording in this database 5, wherein this first is included in one first of this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage that this loads simulator 3 measures, this first response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information very first time and judges and pass through result.
As shown in step 733, this arithmetic unit 1 is by a Fisrt fault information recording in this database 5, and wherein this Fisrt fault information is included in this rated voltage that interval this power supply unit 2 of this supplies, this first response voltage, this oscillograph 4 that this loads simulator 3 measures very first time and measures one first of this first response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
As shown in step 734, this power supply unit 2, according to this group steering order, in one second time interval, produces a slump voltage and is supplied to this device 9 to be measured, and wherein this slump voltage is less than this rated voltage.Then,, as shown in step 735, this device 9 to be measured, according to this slump voltage, produces one second response voltage and is sent to this loads simulator 3 and oscillograph 4.Then, as shown in step 736, the one second response voltage waveform that these loads simulator 3 these second response voltages of measurement and this oscillograph 4 measure corresponding to this second response voltage, and respectively this second response voltage being measured and the second response voltage waveform are sent to this arithmetic unit 1.
As shown in step 737, this arithmetic unit 1 judges that this second response voltage is whether in a normal response voltage range; If so, proceed the processing of step 738; Otherwise, proceed the processing of step 739.
As shown in step 738, this arithmetic unit 1 by one second by information recording in this database 5, wherein this second is included in one second of this slump voltage that this power supply unit 2 of this second time interval supplies, this second response voltage that this loads simulator 3 measures, this second response voltage waveform that this oscillograph 4 measures and this arithmetic unit 1 correspondence by information and judges and pass through result.
As shown in step 739, this arithmetic unit 1 is recorded in one second failure message in this database 5, and wherein this second failure message comprises that this second response voltage, this oscillograph 4 that this slump voltage of supplying at this power supply unit 2 of this second time interval, this loads simulator 3 measure measure one second of this second response voltage waveform of arriving and this arithmetic unit 1 correspondence and judge fail result.
As shown in step 740, this test procedure 13 increases by a fixed cycle by this second time interval.
As shown in step 741, this test procedure 13 judges whether this second time interval is greater than a Preset Time; If so, proceed the processing of step 742; Otherwise, proceed the processing of step 728.
As shown in step 742, this test procedure 13 is initialized as an initial time by this second time interval.
Consult Fig. 2 and Fig. 5, wherein, as shown in step 631～639, this test macro carries out one second test period, one the 3rd test period, one the 4th test period, one the 5th test period, one the 6th test period, one the 7th test period, one the 8th test period, one the 9th test period of the 3rd test phase until 1 the tenth test period, wherein this second test period to the tenth test period its detailed process be similar to this first test period of the 3rd test phase, perform step 728～742, so no longer repeat in this.Wherein each test period all has a plurality of test subcycles, from step 728～739, be a test subcycle, in each test period, carry out step 728 for the first time～739 be one first test subcycle, carry out step 728 for the second time～739 be one second test subcycle, the rest may be inferred, in this preferred embodiment, the second time interval of each the first test subcycle of the 3rd test phase is all the 0.5AC cycle (10 milliseconds), and each fixed cycle of the 3rd test phase is all the 0.5AC cycle, each Preset Time is all 5000 milliseconds and each initial time and is all the 0.5AC cycle, therefore, each test period of the 3rd test phase all has 500 test subcycles, and (the second time interval of each the first test subcycle is all 10 milliseconds, the second time interval of each the second test subcycle is all 20 milliseconds, the second time interval of each the 3rd test subcycle is all 30 milliseconds, the second time interval of each the 500 test subcycle is all 5000 milliseconds).In addition, each rated voltage of the 3rd test phase and the difference between each slump voltage and the ratio of each rated voltage are all 100%.
Wherein, the normal response voltage range in each test phase for the output voltage of this device 9 to be measured be for example 24 volts, this normal response voltage range is 21.6 volts～26.4 volts of the positive and negative 10%(of 24 volts).Yet described 24 volts is only for example, in other embodiments of the invention, can, according to different device 9 changes to be measured, with the present embodiment, not be limited.In addition, in this preferred embodiment, the very first time interval of each test phase is all 3 seconds, but not as limit.It is worth mentioning that, the rated voltage that will first test the rated voltage of rapid drawdown 30% or the rated voltage of rapid drawdown 60% or rapid drawdown 100% due to these rules of IEC61000-4-11 no standard, therefore, the testing sequence of this first test phase, this second test phase and the 3rd test phase can change depending on demand, with the present embodiment, is not limited.
In sum, the present invention is by this arithmetic unit 1, to produce this group steering order to make this power supply unit 2 produce this rated voltage or slump voltage is supplied to this device 9 to be measured to reach self-adjusting effect at each time interval for testing the method for testing of voltage dip of device to be measured, and judge that by this arithmetic unit 1 each response voltage is whether in this normal response voltage range, and by each failure message or by information recording in this database 5, reach self registering object, so really can reach object of the present invention.
As described above, be only preferred embodiment of the present invention, and when not limiting scope of the invention process with this, i.e. all simple equivalences of doing according to the claims in the present invention book and description change and modify, and all still belong to the scope of patent of the present invention.
Claims (10)
1. for testing a method of testing for the voltage dip of device to be measured, it is characterized in that, comprise the following step:
(A) arithmetic unit is carried out a test procedure, to produce one group of steering order, is sent to a power supply unit that is electrically connected on this arithmetic unit;
(B) this power supply unit is organized steering order according to this, in a very first time interval, produces a rated voltage and is supplied to a device to be measured;
(C) this device to be measured, according to this rated voltage, produces one first response voltage and is sent to a loads simulator being electrically connected to this arithmetic unit and device to be measured;
(D) this loads simulator measures this first response voltage and is sent to this arithmetic unit;
(E) this arithmetic unit judges that this first response voltage is whether in a normal response voltage range, if result of determination is no, this arithmetic unit by a Fisrt fault information recording in a database;
(F) this power supply unit is organized steering order according to this, in one second time interval, produces a slump voltage and is supplied to this device to be measured, and wherein this slump voltage is less than this rated voltage;
(G) this device to be measured, according to this slump voltage, produces one second response voltage and is sent to this loads simulator;
(H) this loads simulator measures this second response voltage and is sent to this arithmetic unit; And
(I) this arithmetic unit judges that this second response voltage is whether in this normal response voltage range, if result of determination is no, this arithmetic unit is recorded in one second failure message in this database.
2. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: this loads simulator is one to comprise a variable-resistance digital electric meter.
3. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: this power supply unit and loads simulator all comprise a general purpose interface bus interface card, for the data transmission interface card as between this arithmetic unit and this power supply unit and loads simulator.
4. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: this arithmetic unit is one to comprise the computing machine of storer of a processor and this test procedure of storage.
5. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: the method also comprises, in this (D) step, one oscillograph being electrically connected to this arithmetic unit and device to be measured measures the one first response voltage waveform corresponding to this first response voltage, and the first response voltage waveform being measured is sent to this arithmetic unit, then this arithmetic unit by this first response voltage waveform recording in this database.
6. according to claim 5 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: this oscillograph comprises a general purpose interface bus interface card, for the data transmission interface card as between this arithmetic unit and oscillograph.
7. according to claim 5 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: the method also comprises, in this (H) step, this oscillograph measures the one second response voltage waveform corresponding to this second response voltage, and the second response voltage waveform being measured is sent to this arithmetic unit, then this arithmetic unit by this second response voltage waveform recording in this database.
8. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 30%.
9. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 60%.
10. according to claim 1 for testing the method for testing of the voltage dip of device to be measured, it is characterized in that: the difference between this rated voltage and this slump voltage and the ratio of this rated voltage are 100%.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104459422A (en) * | 2014-12-26 | 2015-03-25 | 环旭电子股份有限公司 | Power line interference test system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104459422A (en) * | 2014-12-26 | 2015-03-25 | 环旭电子股份有限公司 | Power line interference test system and method |
| CN104459422B (en) * | 2014-12-26 | 2017-08-18 | 环旭电子股份有限公司 | The method of testing of Interference from the power supply wire test system |
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Application publication date: 20141105 |