CN104124956A - Analog voltage buffer circuit with high-frequency compensation - Google Patents
Analog voltage buffer circuit with high-frequency compensation Download PDFInfo
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- CN104124956A CN104124956A CN201410359994.6A CN201410359994A CN104124956A CN 104124956 A CN104124956 A CN 104124956A CN 201410359994 A CN201410359994 A CN 201410359994A CN 104124956 A CN104124956 A CN 104124956A
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Abstract
The invention discloses an analog voltage buffer circuit with high-frequency compensation. The analog voltage buffer circuit with the high-frequency compensation comprises a main voltage buffer, a main load network connected with the main voltage buffer, a high-frequency compensation circuit connected with the main voltage buffer and comprising an auxiliary voltage buffer, and an auxiliary load network connected with the auxiliary voltage buffer, and the auxiliary voltage buffer is connected with the main voltage buffer through the auxiliary load network, wherein the high-frequency compensation circuit has no influence on the main voltage buffer during low frequency or direct current and leading the main voltage buffer to be subjected into current compensation during high frequency. The analog voltage buffer circuit with the high-frequency compensation can convey compensation currents into the main voltage buffer during high frequency to compensate load current effects of the main load network for performing current compensation, improve linearity under high-frequency input of the voltage buffer and expand operation bandwidth.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of analog voltage buffer circuits with high frequency compensation.
Background technology
ADC (Analog-to-digital converter, analog-digital converter) conventionally formed by a sampling hold circuit and a quantizer, wherein sample/hold amplifier completes the periodic sampling to input signal under the control of clock, and each sample-hoking a period of time is carried out to mould/number conversion for quantizer.Therefore, sampling hold circuit can accurate tracking input signal go forward side by side line sampling and maintenance, be the precondition that realizes high accuracy mould/number conversion.Sampling hold circuit is realized by switched-capacitor circuit conventionally, and it requires sampling capacitance within half clock cycle, to follow the tracks of fast input signal to sample accurately.Therefore, in order to realize this point, input signal source must have enough bandwidth, normally more than 3～5 of sampling frequency times, so in the analog link of system, High Performance ADC above need an analog driver, in order to bring into play the performance of ADC, ensure overall signal processing accuracy, this driver should possess broadband, high linear performance.Wherein, for the broadband analog voltage buffer in analog driver, it is to adopt emitter follower (for Bipolar and BiCMOS technique) and source follower (for CMOS technique) that the most reliable circuit is realized.
In correlation technique, under low frequency input condition, only have a fixing voltage difference between the input signal of voltage buffer and output signal, output signal can accurately be followed the tracks of the variation of input signal, has realized higher input and output linearity.But, under high frequency input condition, on the load circuit of voltage buffer, can produce a load current, and load current is an alternating current, voltage difference between input signal and the output signal of voltage buffer cannot be fixed, cause output signal cannot accurately follow the tracks of the variation of input signal, make the input and output of whole circuit occur non-linear, and along with uprising of frequency input signal, linear variation thereupon, cause having limited bandwidth of operation, cannot improve the linearity of voltage buffer under high frequency input, and cannot expand bandwidth of operation.
Summary of the invention
The present invention is intended to solve at least to a certain extent one of technical problem in correlation technique.
For this reason, the object of the invention is to propose a kind ofly can improve the linearity of voltage buffer under high frequency input, can also expand the analog voltage buffer circuits with high frequency compensation of bandwidth of operation.
For achieving the above object, the embodiment of the present invention has proposed a kind of analog voltage buffer circuits with high frequency compensation, comprising: principal voltage buffer; The main laod network being connected with described principal voltage buffer; High frequency compensation, described high frequency compensation is connected with described principal voltage buffer, and described high frequency compensation comprises: inferior voltage buffer; The inferior laod network being connected with described voltage buffer, described time voltage buffer is connected with described principal voltage buffer by described laod network, wherein, described in the time of low frequency or direct current, high frequency compensation does not form impact to described principal voltage buffer, in the time of high frequency described in high frequency compensation described principal voltage buffer is carried out to current compensation.
The analog voltage buffer circuits with high frequency compensation proposing according to the embodiment of the present invention, produce the offset current mating with main load current by high frequency compensation, offset current is fed through to principal voltage buffer in the time of high frequency and carries out current compensation with the load current effect that compensates main laod network, improve the linearity of voltage buffer under high frequency input, expansion bandwidth of operation.
In addition, the analog voltage buffer circuits with high frequency compensation according to the above embodiment of the present invention can also have following additional technical characterictic:
In one embodiment of the invention, described main laod network comprises: the first resistance, and one end of described the first resistance is connected with described principal voltage buffer; And first electric capacity, one end of described the first electric capacity is connected with the other end of described the first resistance, the other end ground connection of described the first electric capacity.
Further, in one embodiment of the invention, described principal voltage buffer comprises: the first metal-oxide-semiconductor, and the drain electrode of described the first metal-oxide-semiconductor is connected with power supply, and the grid of described the first metal-oxide-semiconductor is connected with input voltage; The second metal-oxide-semiconductor, the drain electrode of described the second metal-oxide-semiconductor is connected with the source electrode of described the first metal-oxide-semiconductor, and the grid of described the second metal-oxide-semiconductor is connected with the first bias voltage; The 3rd metal-oxide-semiconductor, the drain electrode of described the 3rd metal-oxide-semiconductor is connected with the source electrode of described the second metal-oxide-semiconductor, the grid of described the 3rd metal-oxide-semiconductor is connected with the second bias voltage, the source ground of described the 3rd metal-oxide-semiconductor, wherein, between described the second metal-oxide-semiconductor and described the 3rd metal-oxide-semiconductor, have first node, between described the first metal-oxide-semiconductor and described the second metal-oxide-semiconductor, have Section Point, described first node is connected with described the first resistance.
Further, in one embodiment of the invention, described time laod network comprises: the second resistance, and one end of described the second resistance is connected with described voltage buffer; And second electric capacity, one end of described the second electric capacity is connected with the other end of described the second resistance, and the other end of described the second electric capacity is connected with described Section Point.
Further, in one embodiment of the invention, described time voltage buffer comprises: the 4th metal-oxide-semiconductor, and the drain electrode of described the 4th metal-oxide-semiconductor is connected with power supply, and the grid of described the 4th metal-oxide-semiconductor is connected with input voltage; The 5th metal-oxide-semiconductor, the drain electrode of described the 5th metal-oxide-semiconductor is connected with the source electrode of described the 4th metal-oxide-semiconductor, and the grid of described the 5th metal-oxide-semiconductor is connected with described the first bias voltage; The 6th metal-oxide-semiconductor, the drain electrode of described the 6th metal-oxide-semiconductor is connected with the source electrode of described the 5th metal-oxide-semiconductor, the grid of described the 6th metal-oxide-semiconductor is connected with described the second bias voltage, the source ground of described the 6th metal-oxide-semiconductor, wherein, between described the 5th metal-oxide-semiconductor and described the 6th metal-oxide-semiconductor, have the 3rd node, described the 3rd node is connected with described the second resistance.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Brief description of the drawings
The present invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments obviously and easily and understand, wherein:
Fig. 1 is the circuit diagram of analog voltage buffer circuits in correlation technique;
Fig. 2 is the circuit diagram with the analog voltage buffer circuits of high frequency compensation according to an embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skill in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
In description of the invention, it should be noted that, unless otherwise prescribed and limit, term " installation ", " being connected ", " connection " should be interpreted broadly, for example, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be to be directly connected, and also can indirectly be connected by intermediary, for the ordinary skill in the art, can understand as the case may be the concrete meaning of above-mentioned term.
Before describing the analog voltage buffer circuits with high frequency compensation proposing according to the embodiment of the present invention, the analog voltage buffer circuits in correlation technique once is simply described first below.
In correlation technique, shown in figure 1, bias voltage VB1 ' and bias voltage VB2 ' provide bias voltage for transistor MN1 ' and transistor MN2 ', transistor MN1 ' and transistor MN2 ' form the current source of a high output impedance, the source electrode that transistor MN3 ' is received in current source output is that transistor MN3 ' provides direct current biasing, and VI ' is input signal, receives the grid of transistor MN3 ', output signal is VIB ', and draws from the source electrode of transistor MN ' 3.Wherein, transistor MN1 ', transistor MN2 ' and transistor MN3 ' form a source follower circuit, or perhaps voltage buffer, drive for input signal VI ' provides buffering.In adc circuit, the Several Typical Load of this voltage buffer is that a switching capacity sampling keeps network,, uses the conducting resistance of resistance Rsw ' representation switch here, capacitor C s ' represents sampling capacitance, and the series connection of resistance R sw ' and capacitor C s ' is for the load of analog voltage buffer.Particularly, the operation principle of circuit is: transistor MN1 ' and transistor MN2 ' form the current source of high output impedance, for transistor MN3 ' provides stable current offset IB ', like this, under low frequency, the electric current that flows through transistor MN3 ' does not change with the variation of input signal VI ', but keep stable, the gate source voltage VGS3 ' of transistor MN3 ' also remains unchanged, so, output signal VIB '=VI '-VGS3 ', between output signal VIB ' and input signal VI ', only has a fixing voltage difference, output signal VIB ' can accurately follow the tracks of the variation of input signal VI ', realize higher input and output linearity.Obviously, it is that gate source voltage VGS3 ' is remained unchanged that this circuit is realized the high linear key of input and output, but, under high frequency input condition, form on capacitive load circuit and have a load current IL ' by resistance R sw ' and capacitor C s ', this load current IL ' is an alternating current, it can change along with the variation of output signal VIB ', and flow through electric current I DS3 '=IB '-IL ' of transistor MN3 ', electric current I DS3 ' also can change along with the variation of load current IL ' so, it is no longer a fixing bias current, like this, gate source voltage VGS3 ' also can be along with variation, output signal VIB ' no longer accurately follows the tracks of the variation of input signal VI ', consequently, the input and output of whole circuit occur non-linear, and, along with uprising of frequency input signal, it is large that the amplitude of load current IL ' becomes, linear variation thereupon.
Hence one can see that, there is a shortcoming clearly in the analog voltage buffer circuits in correlation technique, that is exactly when incoming frequency is higher, on the capacitive load network that connect, can extract larger load current thereafter, this electric current can change the electric current flowing through on input transistors, causes voltage input/output relation to occur non-linear.In other words, its linearity is obvious variation along with the rising of incoming frequency, causes having limited bandwidth of operation.
The present invention is just based on the problems referred to above, and proposed a kind of analog voltage buffer circuits with high frequency compensation.
The analog voltage buffer circuits with high frequency compensation proposing according to the embodiment of the present invention is described with reference to the accompanying drawings.
Shown in Fig. 2, the analog voltage buffer circuits with high frequency compensation proposing according to the embodiment of the present invention, comprises principal voltage buffer 100, main laod network 200, high frequency compensation 300.High frequency compensation 300 comprises time voltage buffer 400 and time laod network 500.
Wherein, main laod network 200 is connected with principal voltage buffer 100.High frequency compensation 300 is connected with principal voltage buffer 100.Inferior laod network 500 is connected with inferior voltage buffer 400.Inferior voltage buffer 400 is connected with principal voltage buffer 100 by time laod network 500, wherein, in the time of low frequency or direct current, high frequency compensation 300 does not form impact to principal voltage buffer 100, and in the time of high frequency, high frequency compensation 300 is carried out current compensation to principal voltage buffer 100.The circuit of the embodiment of the present invention can be fed through offset current principal voltage buffer and carry out current compensation with the load current effect that compensates main laod network in the time of high frequency, improves the linearity of voltage buffer under high frequency input, expansion bandwidth of operation.
Further, in one embodiment of the invention, shown in Fig. 2, main laod network 200 comprises: the first resistance R sw and the first capacitor C s.Wherein, one end of the first resistance R sw is connected with principal voltage buffer 100.One end of the first capacitor C s is connected with the other end of the first resistance R sw, the other end ground connection of the first capacitor C s.
Further, in one embodiment of the invention, shown in Fig. 2, principal voltage buffer 100 comprises: the first metal-oxide-semiconductor MN1, the second metal-oxide-semiconductor MN2 and the 3rd metal-oxide-semiconductor MN3.Wherein, the drain electrode of the first metal-oxide-semiconductor MN1 is connected with power supply, and the grid of the first metal-oxide-semiconductor MN1 is connected with input voltage VB1.The drain electrode of the second metal-oxide-semiconductor MN2 is connected with the source electrode of the first metal-oxide-semiconductor MN1, and the grid of the second metal-oxide-semiconductor MN2 is connected with the first bias voltage VB2.The drain electrode of the 3rd metal-oxide-semiconductor MN3 is connected with the source electrode of the second metal-oxide-semiconductor MN2, the grid of the 3rd metal-oxide-semiconductor MN3 is connected with the second bias voltage VI, the source ground of the 3rd metal-oxide-semiconductor MN3, wherein, between the second metal-oxide-semiconductor MN2 and the 3rd metal-oxide-semiconductor MN3, there is first node a, between the first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2, have Section Point b, first node a is connected with the first resistance R sw.
Further, in one embodiment of the invention, inferior laod network 500 comprises: the second resistance R r and the second capacitor C r.Wherein, one end of the second resistance R r is connected with inferior voltage buffer 400.One end of the second capacitor C r is connected with the other end of the second resistance R r, and the other end of the second capacitor C r is connected with Section Point b.In addition, in one embodiment of the invention, the capacitance of the resistance of the first resistance R sw and the second resistance R r and the first capacitor C s and the second capacitor C r can be set by technical staff according to actual conditions.
Further, in one embodiment of the invention, inferior voltage buffer 400 comprises: the 4th metal-oxide-semiconductor Mr1, the 5th metal-oxide-semiconductor Mr2 and the 6th metal-oxide-semiconductor Mr3.Wherein, the drain electrode of the 4th metal-oxide-semiconductor Mr1 is connected with power supply, and the grid of the 4th metal-oxide-semiconductor Mr1 is connected with input voltage VB1.The drain electrode of the 5th metal-oxide-semiconductor Mr2 is connected with the source electrode of the 4th metal-oxide-semiconductor Mr1, and the grid of the 5th metal-oxide-semiconductor Mr2 is connected with the first bias voltage VB2.The drain electrode of the 6th metal-oxide-semiconductor Mr3 is connected with the source electrode of the 5th metal-oxide-semiconductor Mr2, the grid of the 6th metal-oxide-semiconductor Mr3 is connected with the second bias voltage VB1, the source ground of the 6th metal-oxide-semiconductor Mr3, wherein, between the 5th metal-oxide-semiconductor Mr2 and the 6th metal-oxide-semiconductor Mr3, have the 3rd node c, the 3rd node c is connected with the second resistance R r.
Particularly, in one embodiment of the invention, shown in Fig. 2, the principal voltage buffer 100 of the embodiment of the present invention is consistent with voltage buffer and laod network in correlation technique with main laod network 200, to have increased a high frequency compensation 300 with the circuit difference in correlation technique.Wherein, so-called high frequency compensation 300 is made up of one voltage buffer 400 and inferior laod network 500 of load compensation network.Particularly, inferior voltage buffer 400 also can be realized by an emitter follower (for Bipolar and BiCMOS technique) or source follower (for CMOS technique), the circuit that can be made up of transistor for example the 4th metal-oxide-semiconductor Mr1, the 5th metal-oxide-semiconductor Mr2 and the 6th metal-oxide-semiconductor Mr3 is realized, its input signal is the second bias voltage VI, and output signal is VIBr.Load compensation network is in series by the second resistance R r and the second capacitor C r according to the form of main laod network, as the load of inferior voltage buffer, one terminates to output signal VIBr, the source electrode that the other end is received the second metal-oxide-semiconductor MN2 is Section Point b, the source electrode of the second metal-oxide-semiconductor MN2 is low-resistance node, can be considered as exchanging ground.
Further, under foregoing circuit design, the operation principle of circuit is: in the time of direct current and low frequency input, because the second capacitor C r presents very high impedance, high frequency compensation 300 affects the work of principal voltage buffer 100 circuit hardly, but in the time that high frequency is inputted, export VIBr from inferior voltage buffer 400 and can produce an electric current I Lr to the second metal-oxide-semiconductor MN2 source electrode, the second metal-oxide-semiconductor MN2 is cathode-input amplifier structure, it is current buffer, therefore electric current I Lr can arrive by the second metal-oxide-semiconductor MN2 the output VIB of principal voltage buffer 100, now, main laod network 200 just will extract an electric current I L from output VIB point, so, flow through the electric current I DS3=IB-IL+ILr of the 3rd metal-oxide-semiconductor MN3, therefore, electric current I Lr has compensated electric current I L at output signal VIB point, consequently, the amplitude of variation of electric current I DS3 diminishes, the amplitude of variation of gate source voltage VGS3 diminishes, output signal VIB can follow the tracks of the come in and go out variation of signal VI of the second bias voltage VI more accurately, the linearity of the input and output of final voltage buffer improves.
The analog voltage buffer circuits with high frequency compensation of the embodiment of the present invention comprises a principal voltage buffer, a laod network, and a high frequency compensation.Wherein, principal voltage buffer is a source electrode (or emitter-base bandgap grading) follower circuit, for input analog signal is cushioned, to drive follow-up load.Laod network is a RC network, for simulating the input sample network of analog to digital converter.High frequency compensation is made up of the source electrode mating with principal voltage buffer (or emitter-base bandgap grading) follower circuit and a RC network of mating with laod network, for generation of the offset current mating with load current, this offset current is sent to principal voltage buffer circuits, for the load current effect of compensating load network.On the circuit base of the embodiment of the present invention in correlation technique, increase high frequency compensation, can produce an electric current matching with load current and carry out compensating load current effect, improve voltage input and output linearity, expanded the bandwidth of operation of voltage buffer circuit.In addition, the high frequency compensation increasing, adopt a voltage buffer to cushion input voltage, and then the mode of driving compensating load network, can reduce the load effect that load compensation network increases to input signal, the linearity that improves voltage buffering, particularly, under high frequency input condition, compensation effect is more obvious.
The analog voltage buffer circuits with high frequency compensation proposing according to the embodiment of the present invention, produce the offset current mating with main load current by high frequency compensation, offset current is fed through to principal voltage buffer in the time of high frequency and carries out current compensation with the load current effect that compensates main laod network, improve the linearity of voltage buffer under high frequency input, expansion bandwidth of operation.
Wherein, term " first ", " second " be only for describing object, and can not be interpreted as instruction or hint relative importance or the implicit quantity that indicates indicated technical characterictic.Thus, at least one this feature can be expressed or impliedly be comprised to the feature that is limited with " first ", " second ".In description of the invention, the implication of " multiple " is at least two, for example two, and three etc., unless otherwise expressly limited specifically.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, amendment, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (5)
1. with an analog voltage buffer circuits for high frequency compensation, it is characterized in that, comprising:
Principal voltage buffer;
The main laod network being connected with described principal voltage buffer;
High frequency compensation, described high frequency compensation is connected with described principal voltage buffer, and described high frequency compensation comprises:
Inferior voltage buffer;
The inferior laod network being connected with described voltage buffer, described time voltage buffer is connected with described principal voltage buffer by described laod network, wherein, described in the time of low frequency or direct current, high frequency compensation does not form impact to described principal voltage buffer, in the time of high frequency described in high frequency compensation described principal voltage buffer is carried out to current compensation.
2. the analog voltage buffer circuits with high frequency compensation according to claim 1, is characterized in that, described main laod network comprises:
The first resistance, one end of described the first resistance is connected with described principal voltage buffer; And
The first electric capacity, one end of described the first electric capacity is connected with the other end of described the first resistance, the other end ground connection of described the first electric capacity.
3. the analog voltage buffer circuits with high frequency compensation according to claim 2, is characterized in that, described principal voltage buffer comprises:
The first metal-oxide-semiconductor, the drain electrode of described the first metal-oxide-semiconductor is connected with power supply, and the grid of described the first metal-oxide-semiconductor is connected with input voltage;
The second metal-oxide-semiconductor, the drain electrode of described the second metal-oxide-semiconductor is connected with the source electrode of described the first metal-oxide-semiconductor, and the grid of described the second metal-oxide-semiconductor is connected with the first bias voltage;
The 3rd metal-oxide-semiconductor, the drain electrode of described the 3rd metal-oxide-semiconductor is connected with the source electrode of described the second metal-oxide-semiconductor, the grid of described the 3rd metal-oxide-semiconductor is connected with the second bias voltage, the source ground of described the 3rd metal-oxide-semiconductor, wherein, between described the second metal-oxide-semiconductor and described the 3rd metal-oxide-semiconductor, have first node, between described the first metal-oxide-semiconductor and described the second metal-oxide-semiconductor, have Section Point, described first node is connected with described the first resistance.
4. the analog voltage buffer circuits with high frequency compensation according to claim 3, is characterized in that, described time laod network comprises:
The second resistance, one end of described the second resistance is connected with described voltage buffer; And
The second electric capacity, one end of described the second electric capacity is connected with the other end of described the second resistance, and the other end of described the second electric capacity is connected with described Section Point.
5. the analog voltage buffer circuits with high frequency compensation according to claim 4, is characterized in that, described time voltage buffer comprises:
The 4th metal-oxide-semiconductor, the drain electrode of described the 4th metal-oxide-semiconductor is connected with power supply, and the grid of described the 4th metal-oxide-semiconductor is connected with input voltage;
The 5th metal-oxide-semiconductor, the drain electrode of described the 5th metal-oxide-semiconductor is connected with the source electrode of described the 4th metal-oxide-semiconductor, and the grid of described the 5th metal-oxide-semiconductor is connected with described the first bias voltage;
The 6th metal-oxide-semiconductor, the drain electrode of described the 6th metal-oxide-semiconductor is connected with the source electrode of described the 5th metal-oxide-semiconductor, the grid of described the 6th metal-oxide-semiconductor is connected with described the second bias voltage, the source ground of described the 6th metal-oxide-semiconductor, wherein, between described the 5th metal-oxide-semiconductor and described the 6th metal-oxide-semiconductor, have the 3rd node, described the 3rd node is connected with described the second resistance.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788393A (en) * | 2017-03-15 | 2017-05-31 | 浙江集速合芯科技有限公司 | A kind of circuit for strengthening the voltage buffer linearity |
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| CN101131807A (en) * | 2006-08-24 | 2008-02-27 | 联咏科技股份有限公司 | Voltage buffer and its source electrode driver |
| US20130294294A1 (en) * | 2012-05-07 | 2013-11-07 | Broadcom Corporation | Power-efficient driver architecture |
| CN103888127A (en) * | 2014-03-28 | 2014-06-25 | 中国电子科技集团公司第二十四研究所 | Input buffer for improving linearity |
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| CN101131807A (en) * | 2006-08-24 | 2008-02-27 | 联咏科技股份有限公司 | Voltage buffer and its source electrode driver |
| US20130294294A1 (en) * | 2012-05-07 | 2013-11-07 | Broadcom Corporation | Power-efficient driver architecture |
| CN103888127A (en) * | 2014-03-28 | 2014-06-25 | 中国电子科技集团公司第二十四研究所 | Input buffer for improving linearity |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106788393A (en) * | 2017-03-15 | 2017-05-31 | 浙江集速合芯科技有限公司 | A kind of circuit for strengthening the voltage buffer linearity |
| CN106788393B (en) * | 2017-03-15 | 2023-04-28 | 浙江集速合芯科技有限公司 | Circuit for enhancing linearity of voltage buffer |
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