CN104124946A - Semi-dynamic trigger - Google Patents
Semi-dynamic trigger Download PDFInfo
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- CN104124946A CN104124946A CN201310144046.6A CN201310144046A CN104124946A CN 104124946 A CN104124946 A CN 104124946A CN 201310144046 A CN201310144046 A CN 201310144046A CN 104124946 A CN104124946 A CN 104124946A
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Abstract
The invention provides a semi-dynamic trigger. A selection circuit selects an input signal from a data signal and a testing signal. A charging-discharging circuit carries out charging/discharging on an intermediate node according to the input signal, a clock rate signal and an adjusting signal. A first storage circuit stores the level of the intermediate node. An adjusting circuit generates an adjusting signal according to the clock rate signal and the level of the intermediate node. An output circuit adjusts a level of an output node based on the clock rate signal and the level of the intermediate node. A second storage circuit stores the level of the output node. A reset circuit is used for resetting or setting the level of the output node. And a switch is connected between the adjusting circuit and the charging-discharging circuit and is in a conduction state in a normal operation mode.
Description
Technical field
The present invention relates to logical circuit, especially relate to the improving technology of semi-dynamic trigger.
Background technology
Semi-dynamic trigger (semi-dynamic flip-flop) is a kind of element being generally applied in Digital Logical Circuits, and its front-end circuit is dynamically, and back-end circuit is static.Fig. 1 illustrates a kind of typical semi-dynamic trigger circuit of realizing with complementary metal oxide semiconductor (CMOS).In this trigger 100, mainly comprise discharge circuit 111, pre-charge circuit 112, Circuit tuning 113, the first storage circuit 114, output circuit 115 and the second storage circuit 116.The effect of trigger 100 is according to clock signal CK, input signal D to be sampled, and its sampling result is signal Q and QB.The function mode of following schematic illustration trigger 100.
When clock signal CK edge falls while occurring, trigger 100 enters pre-charging stage.See through the transistor P1 in pre-charge circuit 112, feeder ear VDD can charge to nodes X, makes its voltage be pulled up to high potential.The high potential of the first storage circuit 114 meeting storage node X.Transistor P2, N5 in output circuit 115 are closed, and are equivalent to the link of blocking between intermediate node X and output node Q, make the second storage circuit 116 continue to store the original state of sampling result QB.At clock signal CK, transfer to after electronegative potential, after the delay in Circuit tuning 113, clock signal CKD also can have electronegative potential subsequently, therefore makes the output node Y of Circuit tuning 113 must have high potential, and then makes the transistor N3 conducting in discharge circuit 111.But because transistor N1 is closed by clock signal CK, no matter input signal D why, can not affect the current potential of nodes X.
When the rising edge and occur of clock signal CK, trigger 100 enters evaluation stage (that is stage that input signal D is sampled).If now input signal D has electronegative potential, the current potential of nodes X still can not be affected, and continues to remain on high potential.If first front nodal point Q has electronegative potential, the conducting of transistor N5 can not impact sampling result QB.Relatively, if first front nodal point Q has high potential, the conducting meeting of transistor N5 is pulled low to electronegative potential by the voltage of node Q, and then sampling result QB is changed into and has high potential.After the rising edge and occur of clock signal CK, again through time of delay of three gates contributions in Circuit tuning 113, node Y can change into and has electronegative potential, and transistor N3 is closed.Close transistor N3 can prevent that input signal D from changing high potential into by electronegative potential subsequently time, discharge circuit 111 discharges nodes X.This design makes trigger 100 according to the characteristic that has edge-triggered (edge-triggered).
When trigger 100 enters evaluation stage, if input signal D has high potential, discharge circuit 111 can be discharged to electronegative potential by nodes X.The first storage circuit 114 subsequently can storage node X electronegative potential.Nodes X after current potential reduces can make the transistor P2 conducting in output circuit 115, thereby makes node Y have high potential, and then makes sampling result QB have electronegative potential.
Summary of the invention
The present invention proposes a kind of new semi-dynamic trigger framework, adds function of reset and test function.By the logic element in configuration circuit suitably, can be because not adding new function to cause the highest running speed of semi-dynamic trigger to decline according to semi-dynamic trigger of the present invention.
A specific embodiment according to the present invention is a kind of semi-dynamic trigger, wherein comprises a selection circuit, a charge-discharge circuit, one first storage circuit, a Circuit tuning, an output circuit, one second storage circuit, a reset circuit and a switch.This selection circuit in order to select an input signal according to a selection signal in a data-signal and a test signal.This charge-discharge circuit connects an intermediate node, and is these intermediate node charge or discharge according to this input signal, a clock signal and an adjustment signal.This first storage circuit connects this intermediate node, and in order to store the current potential of this intermediate node.This Circuit tuning is connected between this intermediate node and this charge-discharge circuit, and in order to produce this adjustment signal according to the current potential of this clock signal and this intermediate node.This output circuit is connected between this intermediate node and an output node, and in order to adjust the current potential of this output node according to the current potential of this clock signal and this intermediate node.This second storage circuit connects this output node, and in order to store the current potential of this output node.This reset circuit is in order to reset or to set the current potential of this output node.This switch is connected between this Circuit tuning and this charge-discharge circuit.When this reset circuit, reset or set the current potential of this output node, this switch is set to the link of blocking between this Circuit tuning and this charge-discharge circuit.When this semi-dynamic trigger is in a normal operation pattern, this switch is set to conducting.
Accompanying drawing explanation
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 illustrates a typical semi-dynamic trigger circuit of realizing with complementary metal oxide semiconductor.
Fig. 2 is according to the circuit diagram of the semi-dynamic trigger in one embodiment of the invention.
Fig. 3 is the signal relativeness of the control circuit in one embodiment of the invention.
Element numbers explanation in figure:
100,200: semi-dynamic trigger 111,211: discharge circuit
112,212: pre-charge circuit 113,213: Circuit tuning
114,214: the first storage circuits 115,215: output circuit
116,216: the second storage circuit N1～N7, P1～P6: transistor
217: select circuit 218: switch
219: control circuit
Embodiment
According to one embodiment of the invention, be a semi-dynamic trigger, its circuit framework as shown in Figure 2.Semi-dynamic trigger 200 comprises a charge-discharge circuit (comprising discharge circuit 211 and pre-charge circuit 212), a Circuit tuning 213, one first storage circuit 214, an output circuit 215, one second storage circuit 216, a selection circuit 217, a reset circuit (comprising transistor N6, N7, P3～P6), a switch 218 and a control circuit 219.In Fig. 2, switch 218 is to represent with transmission gate, and namely by a nmos pass transistor and a gate that PMOS transistor combines, but the execution mode of switch 218 is not as limit.Control circuit 219 is comprised of two inverters and a NAND gate.In practical application, semi-dynamic trigger 200 can be incorporated in integrated circuit and other circuit Collaboration, also can independently exist.
The first storage circuit 214 is in order to assist to store the current potential of intermediate node X.The second storage circuit 216 is in order to assist to store the current potential of output node Q, QB.In this embodiment, the first storage circuit 214 and the second storage circuit 216 each freely two inverters form, but in practice not as limit.
The effect of semi-dynamic trigger 200 is according to clock signal CK, input signal D to be sampled, and its sampling result is output as signal Q and QB.Setting signal SN system is in order to force sampling result QB to be set as having high potential.Reset signal RN system is in order to force sampling result QB to be set as having electronegative potential.In selecting circuit 217, the selection signal SE of inversion signal and SEB system, in order to select a signal in data-signal D and test signal SI, provide to the input signal of semi-dynamic trigger 200 as actual each other.Tester can select to replace data-signal D with test signal SI, and to get rid of the impact of data-signal D, whether independent test semi-dynamic trigger 200 can normal operation.The function mode of semi-dynamic trigger 200 is below described.
In this embodiment, when setting signal SN and reset signal RN all have high potential, the enable signal SR_EN that control circuit 219 produces can have electronegative potential.In this situation, transmission gate 218 meeting conductings, junction nodes Y and Circuit tuning 213.In addition,, because enable signal SR_EN and reset signal R (being the inversion signal of reset signal RN) be in electronegative potential, so transistor N6, N7, P4～P6 in reset circuit are all closed, and transistor P3 is conducting.Persons of ordinary skill in the technical field of the present invention can understand, and semi-dynamic trigger 200 is in the case equivalent to the semi-dynamic trigger 100 that Fig. 1 presents, and its function mode repeats no more.
The input signal of control circuit 219 is setting signal SN and reset signal RN, and output signal is reset signal R, enable signal SR_EN and inversion signal SR_ENB thereof.The relativeness of these signals as shown in Figure 3.As seen from Figure 2, the gate characteristic based in control circuit 219, when the setting signal SN of control circuit 219 has electronegative potential or reset signal RN and has electronegative potential, the enable signal SR_EN that control circuit 219 produces is all has high potential.When enable signal, SR_EN has high potential, and transmission gate 218 can conducting, and the transistor N6 in reset circuit must be for conducting, transistor P3 must be for closing.That is to say, any signal in setting signal SN and reset signal RN has electronegative potential, and node Y just can be discharged to electronegative potential, and discharge circuit 211 and pre-charge circuit 212 impact sampled signal Q/QB neither again.
Should be noted that, the setting signal SN in this embodiment and reset signal RN can be set as having electronegative potential simultaneously.
When the setting signal SN of control circuit 219 has electronegative potential and reset signal RN has high potential, transistor P4, the P5 that connects voltage source V DD in reset circuit is conducting, and transistor N7 is for closing, make the intermediate node X that is connected in transistor N7 source electrode keep high potential.Also conducting of transistor P6, so sampled signal QB also has high potential.Due to transistor, P2 is closed, and transistor N4 is switched on, and therefore, when clock signal CK tool high potential, the node of sampled signal Q is pulled to electronegative potential; When clock signal CK tool electronegative potential, the node of sampled signal Q is because be positioned at the other end of the inverter that is output as high potential QB, so sampled signal Q is also maintained at electronegative potential.That is to say, no matter clock signal CK has high potential or electronegative potential, and output circuit 215 neither may draw high sampled signal Q into high potential.Easy speech, sampled signal Q is forced to be set as having electronegative potential, and sampled signal QB is forced to be set as having high potential.
When setting signal SN has high potential and reset signal RN has electronegative potential, transistor P4, the P5 in reset circuit, P6 are for closing, and transistor N7 is conducting, thereby intermediate node X are set to have electronegative potential, and then make transistor P2 conducting.In this situation, sampled signal Q is forced to be set as having high potential, and sampled signal QB is forced to be set as having electronegative potential.
As seen from Figure 2, the adjustment signal that Circuit tuning 213 produces according to the current potential of clock signal CK and intermediate node X is in order to control transistor N3.The Main Function of transmission gate 218 is optionally to get rid of intermediate node X and the impact of clock signal CK on node Y, make the current potential of node Y only be subject to the control of transistor N6, and then avoid discharge circuit 211 at semi-dynamic trigger 200, to be reset or to establish the current potential of Timing intermediate node X.
As discussed previously, when semi-dynamic trigger 200 enters evaluation stage, if input signal D has high potential, discharge circuit 211 can be discharged to electronegative potential by intermediate node X.It should be noted that when transmission gate 218 is conducting, at clock signal CK, via Circuit tuning 213, be passed in the path of node Y, transmission gate 218 has also been contributed one period of time of delay.The increase of this time of delay (compared to the circuit in Fig. 1) can be delayed the pent time of transistor N3, is equivalent to before discharge circuit 211 stops as intermediate node X electric discharge, extends permissive signal D " reach the stable time.Therefore, although select the time that circuit 217 can cause data-signal D or test signal SI to enter discharge circuit 211 to be delayed (that is reduced permissive signal D " reach stable time); the existence of transmission gate 218 is this problem of balance accordingly, thereby the problem that may make the highest running speed of semi-dynamic trigger 200 decline after adding function of reset and test function.
Should be noted that, in practice, the signal that control circuit 219 produces also can be provided by external circuit.Easy speech, control circuit 219 is not the necessary element in semi-dynamic trigger 200.In addition, persons of ordinary skill in the technical field of the present invention can understand, the detailed execution mode of each circuit blocks not with Fig. 2 the person of being illustrated be limited.For example, in the situation that do not change the logic running of semi-dynamic trigger 200, discharge circuit 211, pre-charge circuit 212, output circuit 215 all may comprise more transistor.Or the element that the gate in Circuit tuning 213 can be had identical operational logic by other replaces.
As mentioned above, the present invention proposes a kind of new semi-dynamic trigger framework, adds function of reset and test function.By the logic element in configuration circuit suitably, can be because not adding new function to cause the highest running speed of semi-dynamic trigger to decline according to semi-dynamic trigger of the present invention.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little modification and perfect, so protection scope of the present invention is worked as with being as the criterion that claims were defined.
Claims (2)
1. a semi-dynamic trigger, comprises:
One selects circuit, in order to select an input signal according to a selection signal in a data-signal and a test signal;
One charge-discharge circuit, connects an intermediate node, and is these intermediate node charge or discharge according to this input signal, a clock signal and an adjustment signal;
One first storage circuit, connects this intermediate node, in order to store the current potential of this intermediate node;
One Circuit tuning, is connected between this intermediate node and this charge-discharge circuit, in order to produce this adjustment signal according to the current potential of this clock signal and this intermediate node;
One output circuit, is connected between this intermediate node and an output node, in order to adjust the current potential of this output node according to the current potential of this clock signal and this intermediate node;
One second storage circuit, connects this output node, in order to store the current potential of this output node;
One reset circuit, in order to reset or to set the current potential of this output node; And
One switch, be connected between this Circuit tuning and this charge-discharge circuit, when this reset circuit is reset or sets the current potential of this output node, this switch is set to the link of blocking between this Circuit tuning and this charge-discharge circuit, when this semi-dynamic trigger is in a normal operation pattern, this switch is set to conducting.
2. semi-dynamic trigger as claimed in claim 1, is characterized in that, this switch is a transmission gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310144046.6A CN104124946B (en) | 2013-04-24 | 2013-04-24 | semi-dynamic trigger |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310144046.6A CN104124946B (en) | 2013-04-24 | 2013-04-24 | semi-dynamic trigger |
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| CN104124946A true CN104124946A (en) | 2014-10-29 |
| CN104124946B CN104124946B (en) | 2016-10-05 |
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| CN201310144046.6A Expired - Fee Related CN104124946B (en) | 2013-04-24 | 2013-04-24 | semi-dynamic trigger |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917355A (en) * | 1997-01-16 | 1999-06-29 | Sun Microsystems, Inc. | Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism |
| US20050151560A1 (en) * | 2003-12-22 | 2005-07-14 | Matsushita Electric Industrial Co., Ltd. | Scan flip flop, semiconductor device, and production method of semiconductor device |
| CN1694356A (en) * | 2004-04-29 | 2005-11-09 | 三星电子株式会社 | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop |
| US8122413B2 (en) * | 2006-06-09 | 2012-02-21 | Otrsotech, Limited Liability Company | Transparent test method and scan flip-flop |
-
2013
- 2013-04-24 CN CN201310144046.6A patent/CN104124946B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917355A (en) * | 1997-01-16 | 1999-06-29 | Sun Microsystems, Inc. | Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism |
| US20050151560A1 (en) * | 2003-12-22 | 2005-07-14 | Matsushita Electric Industrial Co., Ltd. | Scan flip flop, semiconductor device, and production method of semiconductor device |
| CN1694356A (en) * | 2004-04-29 | 2005-11-09 | 三星电子株式会社 | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop |
| US8122413B2 (en) * | 2006-06-09 | 2012-02-21 | Otrsotech, Limited Liability Company | Transparent test method and scan flip-flop |
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| CN104124946B (en) | 2016-10-05 |
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