CN104124247B - Non-volatile memory architecture and its manufacturing method - Google Patents
Non-volatile memory architecture and its manufacturing method Download PDFInfo
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- CN104124247B CN104124247B CN201310143791.9A CN201310143791A CN104124247B CN 104124247 B CN104124247 B CN 104124247B CN 201310143791 A CN201310143791 A CN 201310143791A CN 104124247 B CN104124247 B CN 104124247B
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Abstract
The invention discloses a kind of non-volatile memory architecture and its manufacturing method, the control grid of the semiconductor structure operates the wordline of voltage as receive the semiconductor structure one；The semiconductor structure has one first doped region and one second doped region and the channel between first doped region and second doped region, and the wherein channel has one first length along a first direction；The semiconductor structure further has a charge-trapping lamination on that channel and the conductive layer on the charge-trapping lamination, and the wherein conductive layer extends along the first direction；The conductive layer can be simultaneously as the control grid of the semiconductor structure and the wordline.
Description
Technical field
The present invention is related with its manufacturing method with a non-volatile memory architecture.
Background technology
Nonvolatile semiconductor memory array can be widely used in various devices, such as nitride read only
Memory, EEPROM or while being removed for electric power, can still retain the flash memory of memory.Nonvolatile memory known to Figure 1A displayings
The vertical view of array 10, including the grid by the storage unit constructed by multilayer technology feature.Pass through 120 institute of dielectric film
The sightless band of covering is doped region, is inside embedded in substrate and is configured for source electrode or the drain electrode of storage unit.
Conductor wire 140 is in parallel and is orthogonal to item and brings and put, and wherein conductor wire 140 is usually as the word of storage unit
Line, and its storage unit to one row of selection during write-in or read operation.Another conductive layer is covered by wordline 140,
And the conductive layer is configured to act as the grid layer of each storage unit.After the etching step of conductor wire 140, there will be remnants
(commonly known as strip residue (English is known as stringer and is denoted as 160) is along the side wall random shape of dielectric pattern 120 for object
Into.Ideally, the gap between wordline 140 should be without any conductive material, because conductive residue is between wordline
Interference can be caused, however actual state is really not so.
In order to which Figure 1A is more easily understood, Figure 1B is quoted hereby to describe the cross-sectional view along the line AA ' in Figure 1A.One
Dielectric film 120 is located at substrate 100 and is placed in being used for that neighbouring grid layer 130 is isolated on doped region 110.Charge-trapping is folded
Layer (being ONO laminations (oxidenitride oxide) in this diagram) 135 is placed between substrate 100 and grid layer 130.
Fig. 1 C describe the cross-sectional view along line BB ', for showing the region that grid layer 130 or wordline 140 is not present.
Fig. 2A to Fig. 2 E-2 further illustrates a part for the known procedures of manufacture aforementioned memory array 10, and please simultaneously
Drink ginseng Fig. 3 A to Fig. 3 C.The step of forming ONO films 135 and conductive gate layer 130 is omitted.Fig. 2A is used for illustrating that an etching walks
Suddenly, which is introduced into so that by the patterned several bands of composite laminate 130/135, wherein composite laminate 130/135 passes through
Etching is with trapezoidal side wall.Fig. 3 A are the respective top of Fig. 2A.Fig. 2 B are painted to be formed by ion implanting or diffusion technique
Built-in type diffusion band 110.Fig. 2 C illustrate that dielectric film 120 is deposited to be filled in patterned composite laminate 130/
Gap between 135, and to obtain flat top surface after eatch-back or other planarisation steps.Fig. 3 B are the corresponding of Fig. 2 C
Vertical view.Fig. 2 D show the conductive film 140 at the top that composite laminate 130/135 is then deposited on after Fig. 2 C.Finally, it adopts
With etching step, conductive film 140 is cut into several conductor wires 140, as shown in FIG. 3 C.Figure 1B and Fig. 1 C are painted respectively
Along the cross section of the line AA ' (along word-line direction) in Fig. 3 C and line BB ' in Fig. 3 C.It is apparent that according to Known designs and work
Skill, the composite laminate 130/135 with trapezoidal side wall can be such that dielectric film 120 is easy to be filled in gap and be formed as in Fig. 2 C
Dielectric film 120 inverted trapezoidal, and then lead to the conductive film on the side wall of dielectric film 120 shown in Fig. 1 C
130 are likely difficult to be etched step and remove completely.Therefore, after an etching step, conduction is inevitably more or less had
Residue 160 is stayed between wordline.Therefore, by interfering with each other (cross talk) as urgently caused by they's conduction residue
Problem to be solved.
Invention content
The present invention discloses a kind of organization of semiconductor memory, and wherein the memory construction is by the use of wordline as its control gate
Pole, to reduce the laminated thickness above the charge-trapping lamination of memory.
A kind of semiconductor structure includes one first doped region and one second doped region, first doped region and this
Two doped regions can be source electrode or the drain electrode of the semiconductor structure.The semiconductor structure also has a channel, and the channel is along the
One direction has one first length, and the channel is between the first doped region and the second doped region.One conduction is placed on
On a charge-trapping lamination on the channel, wherein the conductive layer extends along the first direction.Conductive layer can be used as should be partly
The control grid of conductor structure, and can simultaneously as receive semiconductor structure operation voltage wordline.
The present invention further has a kind of memory array, including multiple memory storage units, wherein adjacent storage
Device storage element is separated with built-in type diffusion zone along a first direction.Built-in type diffusion zone is along being orthogonal to first
The second direction extension in direction.Memory also has a conductor wire, which is designed to be used for concatenating along a first direction
Multiple memory storage unit.In order to reduce the thickness in storage element superimposed layer, conductor wire can be used as storage element simultaneously
Control grid and wordline.
A kind of method for manufacturing semiconductor structure includes forming multiple built-in type diffusion bands, wherein built-in type in the substrate
Diffusion band extends along a first direction.This method further forms multiple memory storage units on substrate, wherein should
Multiple memory storage units are concatenated by forming wordline in the second direction for be orthogonal to first direction.Wordline is same
When can be as the control grid of each storage element.
Description of the drawings
Figure 1A to Fig. 1 C illustrates the different perspective views of known nonvolatile memory array；
Fig. 2A to Fig. 2 E-2 illustrates to manufacture the technological process of known nonvolatile memory array；
The respective top of schema in Fig. 3 A to Fig. 3 C definition graphs 2A to Fig. 2 E-2；
Fig. 4 describes semiconductor structure, in accordance with the present invention；
Fig. 5 A-1 to Fig. 5 K-3 illustrate to manufacture the technological process of semiconductor structure and corresponding vertical view schema；
Fig. 6 illustrates memory array according to the present invention.
Main element symbol description：
10 nonvolatile memory arrays
40 semiconductor structures
60 memory arrays
100 substrates
110 built-in types spread band
120 dielectric films
130 conductive gate layers
135 charge-trapping laminations
140 wordline
160 conductive residues
400 substrates
401 first/second doped regions
405 channels
410 412 hard mask layers of charge-trapping lamination/hard mask
418 sacrificial layers
420 dielectric films
430 conductive layers
500 masks
510 pellicular cascades
520 gaps
560 dashed circles
610 memory storage units
612 charge-trapping laminations
614 hard masks
616 dielectric layers
620 built-in type diffusion zones
630 conductor wires/wordline
650 interlayer dielectric layers
Specific embodiment
As described below is the embodiment and appended diagram that institute's example is stated in the present invention, this hair is directed in a manner of various illustrations
Bright do more fully illustrates.The various illustrations proposed answer Overall View without should quote a remark out of its context or with this to the present invention be intended to
The range of protection is limited, and disclosed content is completely understood for being familiar with the those skilled in the art in this field.In the description
Used " or " word is a connection term, can be considered " and/or ".In addition, article " one " can be considered singular or plural." coupling "
Or " connection " word can be directly connected between proxy component or is attached indirectly through other components.
Fig. 4 illustrates semiconductor structure 40 according to the present invention.Semiconductor structure 40 is the MOS formed on substrate 400
Structure.Substrate 400 is the first conduction type.The first doped region and the second doped region 401 with the second conduction type are put
In substrate 400, the second conduction type is opposite with the first conduction type.One charge-trapping lamination 410 is placed in the top of substrate 400
On surface, trapping layer 410 includes floating gate structure polysilicon (poly Si) or for silicon nitride (SiN) or other forms electricity
Lotus capture mechanism material, and with upper and lower dielectric layer composition composite construction charge-trapping pellicular cascade (such as OPO,
ONO...etc).Charge-trapping lamination 410 is designed to a memory storage device, which can be in flowing carrier certainly
Carrier will be flowed when channel 405 is injected into trapping layer 410 and is captured state to define memory storage device.Channel 405
It is between the first doped region and the second doped region, X-direction is commonly known as channel-length direction.Semiconductor structure 40 is again
Comprising a dielectric film 420, the top surface of wherein its top surface and charge-trapping lamination 410 is coplanar.Dielectric film 420 is to use
Dielectric material is formed, so that conductive layer 430 and first and second doped region 401 is isolated.Conductive layer 430 is placed in charge-trapping and folds
On layer 410, and conductive layer 430 also can grid in order to control simultaneously, which can come pair based on the bias difference applied
Semiconductor structure 40 carries out the operation of different mode.Conductive layer 430 also along the direction of passage length (X-direction) extend, with
Conductive layer 430 is also used as control grid by other similar semiconductor structure connections, multiple semiconductor structure.In more specific words
It, conductive layer 430 is also the wordline of semiconductor structure 40, also that is, conductive layer 430 can receive operation electricity by control circuit
Pressure, to allow to be written, read or wipe charge in semiconductor structure 40.In the present embodiment, since conductive layer 430 is also half
The control grid of conductor structure 40, therefore can be removed for the conductive gate layer needed for control grid in known structure, therefore
The thickness of grid is reduced.
Fig. 5 A-1 to Fig. 5 K-3 illustrate to be manufactured similarly to the technological process of the semiconductor structure of the embodiment shown in Fig. 4.
Each step is represented by vertical view schema and its corresponding cross-sectional view.Fig. 5 A-1 and Fig. 5 A-2, which are painted, catches charge
It obtains lamination 410 and is covered in 400 surface of substrate.Hard mask layer 412 is placed in charge-trapping as shown in Fig. 5 B-1 and Fig. 5 B-2
On lamination 410.It is then covered thereon with sacrificial layer 418 shown in Fig. 5 C-1 and Fig. 5 C-2.Sacrificial layer 418 can pass through different materials
Material is formed, such as silicon, silica or silicon nitride.In one embodiment, sacrificial layer 418 is formed by polysilicon.If rigid cover
Mold layer 412, which is enough to cover film thereunder during ion implantation technology or injects ions into technique and do one, properly to be adjusted
To reduce the damage of damage underlying film, then the step of forming sacrificial layer 418 can be omitted in certain embodiments.
Fig. 5 D-1 and Fig. 5 D-2, which are painted, carries out photoetching process to be patterned in covering on a part of top surface of sacrificial layer 418
Mould 500 (if being formed selectively sacrificial layer), and uncovered area is injected as built-in type diffusion zone so that substrate 400 receives
Impurity.The patterned hard film that mask 500 can also be placed on sacrificial layer 418 is formed.Then such as Fig. 5 E-1 and Fig. 5 E-
Unsheltered film is removed with etching step shown in 2, and then is formed by charge-trapping lamination 410, hard mask layer 412 with sacrificing
Layer 418 forms the pellicular cascade 510 with trapezoidal side wall.Mask 500 will be removed after pellicular cascade 510 is formed with into
Row subsequent technique.Represent that impurity is placed in by ion implanting or diffusion technique in substrate 400 in Fig. 5 F-1 and Fig. 5 F-2, with shape
Into doped region 401.According to the operation of each semiconductor structure, doped region 401 can be source electrode or drain electrode.Fig. 5 G-1 and figure
5G-2 illustrates that dielectric film 420 is placed on pellicular cascade 510, and also fill into the gap 520 between pellicular cascade 510 with
Insulation between the conductive layer formed in subsequent technique and substrate is provided.Eatch-back or chemical-mechanical planarization (CMP) technique it is flat
Chemical industry skill is introduced into in the excessive dielectric film 420 of the top removal of sacrificial layer 418, as shown in Fig. 5 H-1 and Fig. 5 H-2.
Display adds the removal technique of code-pattern etching to remove part dielectric film 420 in Fig. 5 I-1 and Fig. 5 I-2
And sacrificial layer 418.Code-pattern etching is designed to the similar etch-rate to dielectric film 420 and sacrificial layer 418.Firmly
Formula mask 412 is designed to have more resistance to code-pattern etching step.In some embodiments, dielectric film 420 is oxidation
Silicon thin film and sacrificial layer 418 are silicon thin film, and hard mask 412 is silicon nitride film.The news of nitrogen are detected in endpoint detection device
Number while, code-pattern etching step can stop, which means the exposure of hard mask layer 412.Over etching step can
It optionally carries out to remove the residue in hard mask layer 412, especially from the residue of sacrificial layer 418, to ensure to grasp
Make reliability.
Then as shown in Fig. 5 J-1 and 5J-2, conductive layer 430 is formed after aforementioned etching.Then as retouched in Fig. 5 K-1
It paints, a patterning step is used to further generate multiple conductive strips.Dashed circle 560 represents the list of semiconductor structure
Member, the semiconductor structure are similar to semiconductor structure as shown in Figure 4.Fig. 5 K-2 are the cross section along line AA ', and are schemed
5K-3 is the cross section along line BB '.
Compared with known semiconductor structure, the sacrificial layer 418 retained for known semiconductor structure is (such as institute in Fig. 5 H-2
Show), in an embodiment of the present invention, do not need to sacrificial layer presence.
In some embodiments, mask layer 412 is nitride film, and can be with ONO (oxidenitride oxide)
Lamination trapping layer 410 merges to form ONON (oxidenitride oxide-nitride) lamination.In some embodiments,
Mask layer 412 is nitride film, and can be carved before conductive layer 430 disposes side thereon by the wet method of such as hot H3PO4
It loses to remove.In some embodiments, it is silicon oxide film that it is oxidized, which to capture the remaining mask layer 412 on lamination 410, and with
ONO (oxidenitride oxide) capture laminations 410 merge to form ONO laminations.Elemental semiconductor illustrated in fig. 4
Structure is to capture layer laminate with ONO to characterize.
Fig. 6 illustrates the memory array 60 covered by interlayer dielectric layer 650.Memory array 60 has with parallel side
Multiple conductor wires 630 of formula configuration.It also disposed multiple memory storage units 610 on substrate simultaneously.Each storage element
610 include the charge-trapping lamination 612 for storing capture charge.Conductor wire 630 is placed in the top table of charge-trapping lamination 612
Face and with top surface material contact.Storage element 610 includes the hard mask layer 614 of such as nitride in charge-trapping lamination again
Between 612 and conductor wire 630.Each conductor wire 630 concatenates multiple storage elements 610, and is biased to operate to receive as wordline
Selected storage element.Memory array 60 also comprising multiple built-in type diffusion zones 620, is placed in substrate and along just
Meet at the Y-direction extension of X-direction.Each band of built-in type diffusion zone 620 can be as the source/drain of each storage element
Pole, and storage element adjacent to each other is separated along the X direction.The gap of adjacent storage element is filled with dielectric layer 616.Often
One conductor wire 630 is also the control grid of each storage element 610 simultaneously.Charge-trapping unit 612 can be ONO pellicular cascades or can
For other configurations of memory storage.In certain embodiments, storage element 610 does not include hard mask layer 614.
It is total such as the memory device in Fig. 6 since wordline 630 is also simultaneously the control grid of each storage element
Thickness is reduced.When the size of semiconductor device becomes more and more crucial, the present embodiment, which also provides, makes the volume of crystal grain contract
The advantages of small.
The technology contents and technical characterstic of the present invention have revealed that as above, however one skilled in the art scholar is still potentially based on
Teachings of the present invention and announcement and make various replacements and modification without departing substantially from spirit of the present invention.Therefore, protection scope of the present invention
Those disclosed embodiments should be not limited to, and various replacements and modification without departing substantially from the present invention should be included, and the right for accompanying will
Range is asked to be covered.
Claims (6)
1. a kind of semiconductor structure, it includes：
One first doped region and one second doped region, are placed in substrate；
One channel in the substrate between first doped region and second doped region, and has along a first direction
There is one first length；
One charge-trapping lamination is placed in the top surface and on that channel of substrate；
One conductive layer extends on the charge-trapping lamination and along the first direction, and wherein the conductive layer is partly led as this
The control grid of body structure and the wordline that voltage is operated as receive the semiconductor structure one；
One hard mask layer, the hard mask layer are and the hard mask layers between the conductive layer and the charge-trapping lamination
For silicon nitride film, merge to form an ONON pellicular cascades with the charge-trapping lamination；And
One dielectric film, is placed between substrate and conductive layer, and top surface and the top surface of hard mask layer are coplanar, with
Conductive layer and first and second doped region in substrate is isolated.
2. semiconductor structure according to claim 1, wherein the charge-trapping lamination are an ONO pellicular cascades.
3. a kind of memory array, it includes：
Multiple memory storage units, plurality of neighbouring memory storage unit pass through a built-in type along a first direction
Diffusion zone separates, and wherein the built-in type diffusion zone extends along the second direction for being orthogonal to the first direction；
One conductor wire concatenates multiple memory storage unit along the first direction, and wherein the conductor wire is as the storage
The control grid and wordline of unit；
One charge-trapping lamination, wherein the charge-trapping lamination are between the conductor wire and substrate；
One hard mask layer, the hard mask layer are and the hard mask layers between the conductor wire and the charge-trapping lamination
For silicon nitride, merge to form an ONON pellicular cascades with the charge-trapping lamination；And
One dielectric film, is placed between substrate and conductor wire, and top surface and the top surface of hard mask layer are coplanar, with
Conductor wire and substrate is isolated；
The wherein conductor wire and the top surface material contact of the hard mask layer.
4. a kind of method for manufacturing semiconductor structure, it includes：
Multiple built-in type diffusion bands are formed in a substrate, wherein multiple built-in type diffusion band prolongs along a first direction
It stretches；And
Multiple memory storage units are formed on a substrate, wherein multiple memory storage unit is by being orthogonal to this
The wordline formed in one second direction of first direction is concatenated, and wherein the wordline can be as the control of each storage element
Grid processed；
Wherein, each memory storage unit has the charge-trapping lamination being placed under the wordline, and this method is further wrapped
It is contained between the charge-trapping lamination and the wordline and forms a hard mask layer, make the hard mask layer before the wordline is formed
Oxidation, and the hard mask layer is silicon nitride film, merges to form an ONON pellicular cascades with the charge-trapping lamination.
5. according to the method described in claim 4, it, which is further contained in before forming the wordline, forms a sacrificial layer, wherein should
Sacrificial layer provides the mask for being used to form multiple built-in type diffusion band in a pre-position.
6. according to the method described in claim 5, it, which is further contained in before forming the wordline, removes the sacrificial layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168334A (en) * | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
| CN1855447A (en) * | 2005-04-28 | 2006-11-01 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| CN101308824A (en) * | 2007-03-22 | 2008-11-19 | 海力士半导体有限公司 | Nonvolatile memory device and method of fabricating the same |
-
2013
- 2013-04-24 CN CN201310143791.9A patent/CN104124247B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168334A (en) * | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
| CN1855447A (en) * | 2005-04-28 | 2006-11-01 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| CN101308824A (en) * | 2007-03-22 | 2008-11-19 | 海力士半导体有限公司 | Nonvolatile memory device and method of fabricating the same |
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