CN104124219A - Semiconductor device having silicon through hole and manufacturing method thereof - Google Patents
Semiconductor device having silicon through hole and manufacturing method thereof Download PDFInfo
- Publication number
- CN104124219A CN104124219A CN201310156181.2A CN201310156181A CN104124219A CN 104124219 A CN104124219 A CN 104124219A CN 201310156181 A CN201310156181 A CN 201310156181A CN 104124219 A CN104124219 A CN 104124219A
- Authority
- CN
- China
- Prior art keywords
- silicon
- semiconductor device
- hole
- silicon perforation
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a semiconductor device having a silicon through hole. The semiconductor device includes: a substrate having a front side and back side; and silicon perforation, through the substrate and with circular and rectangular with rounded corners in the dorsal side in the front.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof with silicon perforation.
Background technology
In order to save valuable arrangement space or the efficiency of increase interconnect, a plurality of integrated circuits (IC) chip stack can be become to an IC encapsulating structure together.In order to reach this object, can use a kind of three-dimensional (3D) storehouse encapsulation technology that plural integrated circuit (IC) chip is packaged together.This kind of three-dimensional (3D) storehouse encapsulation technology uses silicon perforation (TSV) widely.Silicon perforation (TSV) is a kind of vertical conduction through hole, and it is through-silicon wafer, silicon plate, made substrate or the chip of any material completely.Now, 3D integrated circuit (3DIC) is used to many fields as internal memory storehouse, image sensing chip etc. by wide.
Although silicon perforation has many advantages, its manufacture method still belongs to frontier for semiconductor industry.In this frontier, there is the development space of many new constructions and/or new manufacturing method.
Summary of the invention
The present invention relates to a kind of semiconductor device with silicon perforation, comprise: substrate, has front side and dorsal part; And silicon perforation, run through this substrate and in this front side, there is circle and at this dorsal part, there is the rectangle of corners.
The manufacture method that the present invention relates to a kind of semiconductor device, comprises: the substrate with the first side and the second side is provided; From this first side, in this substrate, form a through hole; On the sidewall of this through hole, form protective layer but the bottom of exposed this through hole; Expand the bottom of this through hole and revise shape; On the lower curtate of this through hole and sidewall, form dielectric layer; Form the electric conducting material of filling this through hole; And certainly this second sidesway except the part of this substrate is with exposed this electric conducting material and complete a silicon perforation.
Accompanying drawing explanation
Fig. 1 shows according to the cross section sketch plan of the semiconductor device with silicon perforation (TSV) of one embodiment of the invention;
Figure 1A show the perforation of silicon according to an embodiment of the invention (TSV) before side on look sketch plan;
Figure 1B show the perforation of silicon according to an embodiment of the invention (TSV) dorsal part on look sketch plan;
Fig. 2-7 show the manufacture method according to one embodiment of the invention with the many semiconductor devices of silicon perforation (TSV).
Embodiment
To explain preferred embodiment of the present invention below, such as the sub-portion of assembly, assembly described in this, structure, material, configuration etc. all can be disobeyed the order of explanation or affiliated embodiment and be mixed into arbitrarily new embodiment, and these embodiment surely belong to category of the present invention.After having read the present invention; know this skill person when can be without departing from the spirit and scope of the invention; above-mentioned assembly, the sub-portion of assembly, structure, material, configuration etc. are done to a little change and retouching; therefore the present invention's scope of patent protection must be as the criterion depending on the appended claim person of defining of these claims, and these are changed with retouching when belonging in claim of the present invention.
Embodiments of the invention and illustrate numerously, for fear of obscuring, similarly assembly system indicates with same or analogous label.Figure is shown in and passes on concept of the present invention and spirit, therefore the shown distance in figure, size, ratio, shape, annexation .... wait and be all signal but not fact, all distance, size, ratio, shape, annexations that can reach in the same manner identical function or result .... wait and all can be considered equivalent and adopt.
With reference now to Fig. 1,, it shows the cross section sketch plan according to one embodiment of the invention with the semiconductor device of silicon perforation 1000.In the present invention, focus is silicon perforation itself but not silicon perforation top or surroundings, so the interconnect structure of silicon perforation top and driving component around will be omitted in order to avoid fuzzy focus of the present invention unnecessarily.Silicon perforation 1000 (TSV, penetrating electrode, conductive pole etc. are otherwise known as in some technological document) can run through substrate 100 entity and be electrically connected to the dorsal part 102 and front side 101 of substrate 100.Silicon perforation 1000 is in order to operating voltage VSS, VDD or operation signal are coupled to the integrated circuit (not shown) that is formed on substrate 100 or in order to transmit signal and/or the voltage of chip chamber.Compared to ordinary driving component, as transistor, silicon perforation 1000 has micron-sized oversize.In one embodiment, when silicon perforation has circular section, silicon perforation 1000 has the diameter of approximately 30 μ m.In another embodiment, when silicon perforation has circular section, silicon perforation has the diameter of approximately 10 μ m.In another embodiment, when silicon perforation has circular section, the diameter that silicon perforation has at least 1 μ m is as 6 μ m.
Silicon perforation 1000 shown in Fig. 2-5 appears to by intermediate throughholes technique or the made silicon of through hole preliminary processes bores a hole, but silicon perforation 1000 can be made by through hole preliminary processes (manufacturing silicon perforation before transistor), intermediate throughholes technique (manufacturing silicon perforation after transistor is made but during the manufacture of lower level interconnect) or the rearmounted technique of through hole (just manufacturing silicon perforation after interconnect).Be no matter which kind of technique to manufacture silicon perforation 1000 by, the basic structure of silicon perforation 1000 all remains unchanged: through hole 150/150 ' (do not show in Fig. 1 but be shown in Fig. 2-4), the dielectric layer 152 ' on through-hole side wall and fill up the electric conducting material 900 ' of through hole.Dielectric layer 152 ' and electric conducting material 900 ' material used can be depending on manufacture method and required physical characteristic.Silica and silicon nitride are for being the most often used as the material of dielectric layer 152 '.As for electric conducting material 900 ', it can comprise resistance barrier/adhesion layer material and low resistivity material, resistance barrier/adhesion layer material is for example tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese and/or copper, and low resistivity material is for example tungsten, copper, aluminium and/or polysilicon.
On front side in silicon perforation 1000 is device/interconnect layer 500.Device/interconnect layer 500 represented selectively driving component, interlayer dielectric layer and contact bolt (if silicon perforation be by the manufacturing of through hole preliminary processes), metal intermetallic dielectric layer and all interconnect structures being embedded in these metal intermetallic dielectric layer.Should be appreciated that, Fig. 1-6 have shown an overall part, thus substrate 100 can comprise shallow slot isolation structure, various doped region, passive component as resistance, other redundant pattern and optionally driving component as transistor (if silicon perforation is by the manufacturing of through hole preliminary processes).At place, front side, as shown in Figure 1A, in order to be coupled to the silicon perforation 1000 of interconnect structure (not shown), there is the circular section profile that diameter is d.Diameter d is equal to or greater than 1m 5m according to appointment.At dorsal part place, as shown in Figure 1B, in order to be coupled to the silicon perforation 1000 of the line that heavily distributes (RDL) 600 that dorsal part coiling uses, there is the corners rectangular cross sectional profile that long edge lengths is D.Long edge lengths D is at least 1.2 times of diameter d, and therefore long edge lengths D is at least equal to or greater than 1.2m and is for example about 6m.The function of line (RDL) 600 of heavily distributing can be understood to be between silicon perforation 1000 and other silicon perforation be connected or silicon bore a hole 1000 with dimpling piece/projection 700 between be connected, therefore the line 600 that heavily distributes is be similar to the interconnect on front side and can have the plural layer being embedded in dielectric layer in the direction of vertical substrate.Dimpling piece/projection 700 is an external interface, allows silicon perforation be able to exchange with the external world that (so driving component is able to exchange with the external world.
With reference now to Figure 1A and 1B,, it has shown according to looking sketch plan on the front side of the silicon perforation 1000 of one embodiment of the invention Fig. 1 and dorsal part.From Figure 1A and 1B, can know and learn, the long edge lengths D system of corners rectangle is greater than circular diameter d.Figure 1B has not just shown silicon perforation 1000, has more shown and bore a hole the heavily distribution line 600 of 1000 crossovers of silicon.In order to improve silicon perforation 1000 and the contacting between line 600 that heavily distribute, as shown in Figure 1B, on bore a hole 1000 long limit of the silicon at dorsal part place, should be parallel to the long limit of the line 600 that heavily distributes.
Should be appreciated that, principle of the present invention can be applicable to silicon intermediary layer.In this case, Figure 1A representative is embedded in a part for the silicon perforation in substrate 100, and Figure 1B representative is from the two ends of the exposed silicon perforation of side before substrate 100 and dorsal part, and device/interconnect layer 500 is understood by heavily distribute line and dimpling piece/projection of one layer or more and is replaced.
With reference now to Fig. 2-7,, it shows the manufacture method according to one embodiment of the invention with the semiconductor device of silicon perforation (TSV).In Fig. 2, substrate 100 is provided, and from side 101 before substrate, through hole 150 is formed in substrate 100 and does not run through whole substrate 100.Then, dielectric layer 151 is formed on the sidewall and bottom of through hole 150.Substrate 100 can be simple silicon substrate or silicon-on-insulator substrate, or substrate can comprise shallow slot isolation structure, double action assembly as resistance, various doped region, redundant pattern and driving component (if silicon perforation 1000 is by the manufacturing of intermediate throughholes technique) optionally.Through hole 150 can form by photoetching and etch process.Dielectric layer 151 can form by thermal oxidation technology, be formed on whereby on exposed silicon face, or it can amass technique and form by Shen, covers sidewall and the bottom of front side surface and the through hole 150 of whole substrate 100.Dielectric layer 151 can comprise conventional dielectric material as silica and/or silicon nitride.
In Fig. 3, carry out an anisotropic etching to remove the dielectric layer 151 on the bottom of substrate surface upper dielectric layer 151 and through hole 150, obtain whereby annular dielectric layer 151 ' as protective layer to expose the bottom of through hole 150 to the open air but cover the sidewall of through hole 150.
In Fig. 4, carry out a Wet-type etching to expand/to add the bottom of deep via 150 and to revise its shape, so as to the through hole 150 ' that obtains revising.It should be noted that because substrate surface is also exposed to the open air, when substrate surface comprises exposed silicon material, can on substrate surface, form optionally guard shield (not shown) to maintain the complete without wound of substrate surface during Wet-type etching.When substrate surface comprises dielectric material but does not comprise bare silicon material, without forming guard shield.Wet-type etching chemicals used can comprise tetramethyl ammonium hydroxide (TMAH) or ammoniacal liquor.Due to as different in the rate of etch of (10 0) or (1 1 1) for different crystal faces, thus through the through hole 150 ' of modifications through expanding the rectangular cross-section shape can with the bottom of modification with corners.
In Fig. 5, remove optionally guard shield and form another dielectric layer (not shown) on the sidewall of substrate surface, modified through hole 150 ' and bottom.Old dielectric layer 151 ' can combine and become dielectric layer 152 with another dielectric layer (not shown) newly forming herein.Then, form electric conducting material (not shown) to fill up the through hole 150 ' through revising and to carry out a CMP (Chemical Mechanical Polishing) process to remove unnecessary electric conducting material and to form the smooth surface of the overall situation, become whereby electric conducting material 900.Electric conducting material 900 can comprise resistance barrier/adhesion layer material and low resistivity material.Resistance barrier/adhesion layer material is for example tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese and/or copper, and low resistivity material is for example tungsten, copper, aluminium, polysilicon.
In Fig. 6, on the surface of electric conducting material 900 and substrate, form device/interconnect layer 500.Device/interconnect layer 500 represent selectively driving component as transistor, interlayer dielectric layer and contact bolt (if silicon perforation system formed by through hole preliminary processes) and metal intermetallic dielectric layer and all interconnect structures being embedded in wherein.
In Fig. 7, carry out dorsal part ground/polished/thinning with exposed electric conducting material and complete the silicon perforation 1000 that comprises dielectric layer 152 ' and electric conducting material 900 '.
Finally, the dielectric layer (not shown) that forms patterning on dorsal part 102 is formed on difference in silicon perforation 1000 heavily distribute line 600 and isolation heavily distribute line 600 and dimpling piece/projection 700 with isolation.
Under this mode, the present invention can provide silicon perforation and better contact the heavily distributing between line.Also it should be noted that the manufacture method that Fig. 2-7 present is exemplary embodiment, the present invention should not be limited.Other can complete and all should drop in the present invention's category with the manufacture method of the identical silicon perforation structure as shown in 1B as Fig. 1,1A.
Above-described embodiment is only to give an example for convenience of description, though modified arbitrarily by person of ordinary skill in the field, all can not depart from as the scope of institute's wish protection in claims.
Claims (10)
1. a semiconductor device with silicon perforation, comprises:
Substrate, has front side and dorsal part; And
Silicon perforation, runs through this substrate and in this front side, has circle and at this dorsal part, have the rectangle of corners.
2. the semiconductor device with silicon perforation as claimed in claim 1, more comprises:
Device/interconnect layer on this front side.
3. the semiconductor device with silicon perforation as claimed in claim 1, is characterized in that, the long edge lengths of the rectangle of this corners is greater than this circular diameter.
4. the semiconductor device with silicon perforation as claimed in claim 1, is characterized in that, the long edge lengths of the rectangle of this corners is at least 1.2 times of this circular diameter.
5. the semiconductor device with silicon perforation as claimed in claim 1, more comprises:
Dorsal part on this dorsal part heavily distribute online (RDL).
6. the semiconductor device with silicon perforation as claimed in claim 5, is characterized in that, the long limit of the rectangle of this corners is to be parallel to heavily the distribute length direction of online (RDL) of this dorsal part.
7. the semiconductor device with silicon perforation as claimed in claim 1, is characterized in that, this substrate is in order to as a silicon intermediary layer.
8. a manufacture method for semiconductor device, comprises:
The substrate with the first side and the second side is provided;
From this first side, in this substrate, form a through hole;
On the sidewall of this through hole, form protective layer but the bottom of exposed this through hole;
Expand the bottom of this through hole and revise its shape;
On the lower curtate of this through hole and sidewall, form dielectric layer;
Form the electric conducting material of filling this through hole; And
From this second sidesway except the part of this substrate is with exposed this electric conducting material and complete a silicon perforation.
9. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that, the perforation of this silicon has round-shaped and in this second side, has a rectangular shape of corners in the first side.
10. the manufacture method of semiconductor device as claimed in claim 9, is characterized in that, this circle has the long edge lengths system that is equal to or greater than the diameter of 1 μ m and this corners rectangle and is equal to or greater than 1.2 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310156181.2A CN104124219A (en) | 2013-04-28 | 2013-04-28 | Semiconductor device having silicon through hole and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310156181.2A CN104124219A (en) | 2013-04-28 | 2013-04-28 | Semiconductor device having silicon through hole and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104124219A true CN104124219A (en) | 2014-10-29 |
Family
ID=51769581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310156181.2A Pending CN104124219A (en) | 2013-04-28 | 2013-04-28 | Semiconductor device having silicon through hole and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124219A (en) |
-
2013
- 2013-04-28 CN CN201310156181.2A patent/CN104124219A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4577687B2 (en) | Semiconductor device | |
| CN104425453B (en) | 3DIC interconnection means and method | |
| CN106298831A (en) | The technology connected for MRAM MTJ top electrodes | |
| US8753981B2 (en) | Microelectronic devices with through-silicon vias and associated methods of manufacturing | |
| TW201635470A (en) | Novel method for creating alternate hardmask cap interconnect structure with increased overlay margin | |
| CN112567514B (en) | Memory structure and forming method thereof | |
| US11043445B2 (en) | Semiconductor device having a through silicon via and methods of manufacturing the same | |
| US20160155685A1 (en) | Through-substrate structure and mehtod for fabricating the same | |
| CN102760710B (en) | Silicon perforation structure and forming method thereof | |
| US20140264917A1 (en) | A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same | |
| US10103082B2 (en) | Semiconductor device and manufacturing method therefor | |
| CN104867905B (en) | A kind of semiconductor structure comprising silicon hole and its manufacture method | |
| US10707121B2 (en) | Solid state memory device, and manufacturing method thereof | |
| CN108109957A (en) | The antistatic pinboard of system in package | |
| CN104124219A (en) | Semiconductor device having silicon through hole and manufacturing method thereof | |
| US9478464B2 (en) | Method for manufacturing through-hole silicon via | |
| US8993439B2 (en) | Method of manufacturing a semiconductor device | |
| CN102751172A (en) | Integrated passive device and manufacture method thereof | |
| CN104124228A (en) | Integrated structure having silicon through hole | |
| CN104124227A (en) | Semiconductor device | |
| TW201606943A (en) | Memory device and method for fabricating the same | |
| US9349813B2 (en) | Method for fabricating semiconductor device | |
| US20240268112A1 (en) | Semiconductor structure for 3d memory and manufacturing method thereof | |
| CN103579087B (en) | A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure | |
| US20230051597A1 (en) | Semiconductor device including buried contact and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20141029 |