CN104124140B - Form the method for alternately arranged p-type and N-type semiconductor thin layer - Google Patents
Form the method for alternately arranged p-type and N-type semiconductor thin layer Download PDFInfo
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- CN104124140B CN104124140B CN201310145683.5A CN201310145683A CN104124140B CN 104124140 B CN104124140 B CN 104124140B CN 201310145683 A CN201310145683 A CN 201310145683A CN 104124140 B CN104124140 B CN 104124140B
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000000407 epitaxy Methods 0.000 claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 150000003376 silicon Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a kind of method forming alternately arranged p-type and N-type semiconductor thin layer, step includes: 1) Grown silicon epitaxy layer and deielectric-coating；2) define strip groove with photoresist and form region；Groove forms two ends, region and is divided into the identical trench region of two or more shape by one or more photoresist respectively；3) etching forms the first groove and two or more the second groove；4) remove photoresist and deielectric-coating, thermal oxide groove, the silicon epitaxy between the second groove is converted into silica；5) wet etching silica, makes first, second groove merge into a groove；6) in groove, the conduction type silicon epitaxy layer contrary with the silicon epitaxy layer of step 1) is filled.The present invention is performed etching by strip groove two ends are first divided into multiple groove, and remerging is a groove so that the degree of depth at groove two ends is less than the middle degree of depth, thus reduces the difficulty that silicon epitaxy fills groove, and avoids trench interiors generation hole.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of form alternately arranged p-type and N-type semiconductor thin layer
Method.
Background technology
VDMOSFET(Vertical Double-diffused MOSFET, vertical bilateral diffusion field-effect tranisistor) can use and subtract
The thickness of thin drain terminal drift region reduces conducting resistance, but, the thickness of thinning drain terminal drift region will reduce the breakdown potential of device
Pressure, therefore in VDMOS, improves the breakdown voltage of device and the conducting resistance of reduction device is conflict.Super junction MOSFET
Use new structure of voltage-sustaining layer, utilize a series of alternately arranged p-type and N-type semiconductor thin layer, by P under relatively low backward voltage
Type, N-type region exhaust, it is achieved electric charge mutually compensates for, so that p-type, N-type region can realize high breakdown potential under high-dopant concentration
Pressure, thus obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions power MOSFET theoretical limit.
The difficult point of super junction MOSFET is that device architecture forms difficulty, mainly alternately arranged p-type and N-type semiconductor thin layer knot
The formation difficulty of structure.The forming method of alternately arranged p-type and N-type semiconductor laminate structure is usually: at N shape silicon epitaxy layer
Upper formation deep trench, then fill deep trench with p-shaped silicon epitaxy layer.Owing to gash depth is very deep, fill difficulty, particularly at bar
The two ends of shape groove, relative to the zone line of groove, silicon epitaxy grows on 3 sidewalls of groove, as it is shown in figure 1, easily
Causing groove to seal too early, produce hole at trench interiors, easily comes out after chemical mechanical polishing (see figure in these cavities
2), impact is produced on subsequent technique and device performance.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of method forming alternately arranged p-type and N-type semiconductor thin layer, it
Formation difficulty and the cost of super junction can be reduced, it is possible to improve the mechanical performance of super junction.
For solving above-mentioned technical problem, the method forming alternately arranged p-type and N-type semiconductor thin layer of the present invention, including with
Lower processing step:
1) silicon epitaxy layer and deielectric-coating are grown on a semiconductor substrate successively；
2) coating photoresist, defines groove and forms region；Described groove formed region elongated, two ends respectively by one with
Upper photoresist average mark is slit into the identical trench region of two or more shape；
3) photoetching and dry etching, makes groove be formed in the middle of region and forms the first groove, and groove forms two ends, region and forms two respectively
The second identical groove of individual above shape；The width of described second groove less than the half of the first groove width, the second groove deep
Degree is less than the degree of depth of the first groove；
4) remove photoresist and deielectric-coating, thermal oxide is carried out to flute surfaces and sidewall, makes between adjacent two the second groove
Silicon epitaxy layer is fully converted to silica；
5) wet etching, removes silicon completely, makes the first groove and the second groove merge into a groove；
6) in the groove that step 5) is formed, the conduction type silicon epitaxy layer contrary with the silicon epitaxy layer of step 1) is filled.
Above-mentioned steps 4) in, the silicon epitaxy layer (trenched side-wall that i.e. two the second grooves share) between two adjacent the second grooves
Owing to thickness ratio is relatively thin, therefore can be relatively easy to be fully converted to silica, and the silicon epitaxy layer of other positions is thicker,
Silica will not be fully converted to.
The present invention is performed etching by strip groove two ends are first divided into multiple groove, and remerging is a groove so that bar shaped
The degree of depth at groove two ends, less than the middle degree of depth, so reduces silicon epitaxy and fills the difficulty of groove, avoid trench interiors simultaneously
Produce hole, thus not only reduce formation difficulty and the cost of super junction, improve the mechanical performance of super junction also simultaneously.
Brief description
Fig. 1 is the alternately arranged p-type of existing formation and the technique of N-type semiconductor laminate structure, in the trench between and two ends growth
The schematic diagram of silicon epitaxy.
Fig. 2 be existing technique after chemical mechanical polishing, the empty situation in the middle of groove and two ends.
Fig. 3 is the process schematic flow sheet of the embodiment of the present invention 1.
Fig. 4 is the plan view along a longer face of the groove being formed in the embodiment of the present invention 1.
Fig. 5 is the groove perspective view in the embodiment of the present invention 1 after oxide etch.
Fig. 6 is the cross-sectional view of the embodiment of the present invention the 1st, the super junction MOSFET element that 2 ultimately form.
Fig. 7 is the schematic diagram (top view) that the groove that the embodiment of the present invention 2 defines with photoresist forms region.
Fig. 8 is the structure top view that Fig. 7 is formed after etching groove.
In figure, description of reference numerals is as follows:
1: Semiconductor substrate
2: the first silicon epitaxy layers
3: deielectric-coating
4: photoresist
5: the first grooves
6: the second grooves
7: silica
8: groove
9: the second silicon epitaxy layers
10:P type base
11:N type source region
12: gate dielectric layer
13: grid
14: insulating medium layer
15: front metal electrode
16: back metal electrode
Detailed description of the invention
More specifically understand for the technology contents of the present invention, feature are had with effect, in conjunction with embodiment illustrated, describe in detail such as
Under:
Embodiment 1
The present embodiment forms alternately arranged p-type and the method for N-type semiconductor thin layer, and its technological process is as follows:
Step 1, grows the first silicon epitaxy layer 2 and deielectric-coating 3, on semiconductor substrate 1 successively as shown in Fig. 3 (a).
First silicon epitaxy layer 2 has the first conduction type (N-type or p-type), and deielectric-coating 3 is silica, silicon nitride or hydroxide
At least one in silicon.
Step 2, coating photoresist 4, define groove and form region, as shown in Fig. 3 (b) (top view).
It is elongated that described groove forms region, and length is more than 100 microns, two ends respectively by width 0.1～5 micron, length 5～
Photoresist 4 average mark of 50 microns is slit into two identical trench regions of shape, as shown in Figure 3 (b).
Step 3, with photoetching and dry etching, forms region to groove and performs etching, and remove photoetching by dry or wet etch
Glue 4 and deielectric-coating 3.After the etching of this step completes, groove forms and forms the first groove 5 in the middle of region, and groove forms region two
End forms the second groove 6 that two adjacent, that shape is identical respectively, and the width of the second groove 6 is less than the first groove 5 width
Half, as shown in Fig. 3 (c) and Fig. 4.
Owing to gash depth and groove width have relation, groove width is less, and gash depth is more shallow, therefore, forms district at groove
First groove 5 width of territory central authorities is relatively big (1～10 micron), and the degree of depth is relatively deep (10～100 microns), and forms region at groove
4 second groove 6 width at two ends are less (0.4～4.5 micron), the degree of depth shallower (7～80 microns), and the second groove 6
Width and the degree of depth be respectively less than the first groove 5.
Step 4, carries out thermal oxide to flute surfaces and sidewall, and the sidewall making adjacent two the second groove 6 share converts completely
For silica 7, as shown in Fig. 3 (d).The temperature of thermal oxide is 800～1300 DEG C, and pressure is normal pressure.
In thermal oxidation process, the surface of groove 5 and groove 6, and another sidewall of two sidewalls of groove 5 and groove 6,
Also can being oxidized to not shown in silica 7(figure of part).
Owing to the thickness ratio of two adjacent the second shared sidewalls (silicon epitaxy layer) of grooves 6 is relatively thin, i.e. mark in Fig. 3 (c)
Width d smaller (less than 5 microns), therefore can be relatively easy to be fully converted to silica, and outside the silicon of other positions
Prolong layer thicker, silica will not be fully converted to.
Step 5, wet etching, remove the silica 7 that thermal oxide is formed completely, as shown in Fig. 3 (e).
After etching, the first groove 5 and the second groove 6 are merged into a groove 8 together with the groove being newly formed.Groove 8 two ends
Width and intermediate width be equal, but the degree of depth at its two ends is significantly less than the degree of depth of zone line, i.e. the AR at groove two ends is (deep
Wide ratio) significantly less than the AR in the middle of groove, see Fig. 5.
Step 6, (p-type or N-type, with the first conduction type phase to have the second conduction type with silicon epitaxy process to groove 8 filling
The second silicon epitaxy layer 9 instead), as shown in Fig. 3 (f).Owing to the AR at groove 8 two ends is less, easily fills, thus may be used
To avoid groove 8 two ends to remain the risk in cavity after filling.
Step 7, cmp, remove second silicon epitaxy layer 9 at groove top, as shown in Fig. 3 (g).
Owing to when groove 8 is filled, the second silicon epitaxy layer 9 not only can be grown inside groove 8, also can give birth at groove 8 top
Long second silicon epitaxy layer 9, second silicon epitaxy layer 9 at these groove 8 tops is not intended to retain, so chemical machinery to be used
Grind the second silicon epitaxy layer 9 removing groove 8 top, groove 8 top is planarized simultaneously.
Step 8, follow-up conventional MOSFET technique forms p-shaped base, N-type source region, gate dielectric layer, grid, insulation Jie
Matter layer, front metal electrode, wafer thinning and back metal electrode etc., eventually form the super-junction device shown in Fig. 6.
Embodiment 2
The forming method of the alternately arranged p-type of the present embodiment and N-type semiconductor thin layer with embodiment 1, except that,
Groove forms two ends, region and with two photoresists, is divided into 3 identical grooves of shape each the holding level with both hands in strip region respectively
Region, as it is shown in fig. 7, so, is formed for 6 the second groove (see figure 8)s after etching, after wet etching removes silicon,
This 6 second grooves are merged into a groove together with the first groove.The super junction device structure eventually forming is as shown in Figure 6.
Claims (7)
1. form the method for alternately arranged p-type and N-type semiconductor thin layer, it is characterised in that comprise the following steps:
1) silicon epitaxy layer and deielectric-coating are grown on a semiconductor substrate successively；
2) coating photoresist, defines groove and forms region；Described groove formed region elongated, two ends respectively by one with
Upper photoresist average mark is slit into the identical trench region of two or more shape；
3) photoetching and dry etching, makes groove be formed in the middle of region and forms the first groove, and groove forms two ends, region and forms two respectively
The second identical groove of individual above shape；The width of described second groove less than the half of the first groove width, the second groove deep
Degree is less than the degree of depth of the first groove；
4) remove photoresist and deielectric-coating, thermal oxide is carried out to the surface and sidewall of the first groove and the second groove, makes adjacent two
Silicon epitaxy layer between individual second groove is fully converted to silica；
5) wet etching, removes silicon completely, makes the first groove and the second groove merge into a groove；
6) in step 5) fill silicon epitaxy layer, the conduction type of this silicon epitaxy layer and step 1 in the groove that formed) described silicon
The conduction type of epitaxial layer is contrary.
2. method according to claim 1, it is characterised in that described deielectric-coating includes in silica, silicon nitride at least
A kind of.
3. method according to claim 1, it is characterised in that described groove forms the length in region more than 100 microns.
4. method according to claim 1, it is characterised in that step 2), groove forms two ends, region and is used for splitting ditch
The width of the photoresist that groove forms region is 0.1～5 micron, a length of 5～50 microns.
5. method according to claim 1, it is characterised in that the width of described first groove is 1～10 micron, the degree of depth
It is 10～100 microns；The width of described second groove is 0.4～4.5 micron, and the degree of depth is 7～80 microns.
6. method according to claim 1 or 5, it is characterised in that step 4) described two adjacent the second grooves it
Between the thickness of silicon epitaxy layer below 5 microns.
7. method according to claim 1, it is characterised in that the temperature of described thermal oxide is 800～1300 DEG C, pressure
For normal pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310145683.5A CN104124140B (en) | 2013-04-24 | 2013-04-24 | Form the method for alternately arranged p-type and N-type semiconductor thin layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310145683.5A CN104124140B (en) | 2013-04-24 | 2013-04-24 | Form the method for alternately arranged p-type and N-type semiconductor thin layer |
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| Publication Number | Publication Date |
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| CN104124140A CN104124140A (en) | 2014-10-29 |
| CN104124140B true CN104124140B (en) | 2016-11-02 |
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| CN201310145683.5A Active CN104124140B (en) | 2013-04-24 | 2013-04-24 | Form the method for alternately arranged p-type and N-type semiconductor thin layer |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114823531A (en) * | 2022-06-24 | 2022-07-29 | 北京芯可鉴科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS59112633A (en) * | 1982-12-18 | 1984-06-29 | Toshiba Corp | Semiconductor device |
| JPH05243536A (en) * | 1992-03-03 | 1993-09-21 | Rohm Co Ltd | Manufacture of soi structure |
| KR20030049783A (en) * | 2001-12-17 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of forming an isolation film in semiconductor device |
| US8187939B2 (en) * | 2009-09-23 | 2012-05-29 | Alpha & Omega Semiconductor Incorporated | Direct contact in trench with three-mask shield gate process |
| CN102254796B (en) * | 2010-05-20 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Method for forming alternative arrangement of P-type and N-type semiconductor thin layers |
| CN102412260B (en) * | 2010-09-25 | 2014-07-09 | 上海华虹宏力半导体制造有限公司 | Terminal protection structure of super-junction semiconductor device and fabrication method thereof |
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