CN104122441B - Frequency detecting device - Google Patents
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- CN104122441B CN104122441B CN201410353764.9A CN201410353764A CN104122441B CN 104122441 B CN104122441 B CN 104122441B CN 201410353764 A CN201410353764 A CN 201410353764A CN 104122441 B CN104122441 B CN 104122441B
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Abstract
A kind of frequency detecting device, including: periodic signal to be detected is carried out two divided-frequency and processes to produce the frequency-halving circuit of fractional frequency signal；Described fractional frequency signal is carried out delay process to produce the delay circuit of time delayed signal；Charge-discharge circuit, be suitable to when described time delayed signal is the first level, the outfan of described charge-discharge circuit is charged or discharge, when described time delayed signal is second electrical level and described fractional frequency signal is described first level, the outfan of described charge-discharge circuit resetted；Comparison circuit, is suitable to the output voltage comparing the first reference voltage and described charge-discharge circuit when described time delayed signal is described second electrical level to produce the first comparison signal, to compare the output voltage of the second reference voltage and described charge-discharge circuit to produce the second comparison signal；Described first comparison signal and described second comparison signal are carried out the RS latch of latch process.The frequency detecting device that technical solution of the present invention provides has saved the detection time.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly to a kind of frequency detecting device.
Background technology
For major part digital circuit and Digital Analog Hybrid Circuits, generally require the one or more tools of outside offer
There is the periodic signal of certain frequency.The frequency influence of periodic signal the duty of whole circuit, frequency
Too low or too high all may cause whole circuit cisco unity malfunction.For ensureing whole circuit reliably work
Make, it usually needs the frequency of periodic signal is detected, it is judged that whether the frequency of periodic signal is predetermined
Within frequency range.
In prior art, generally use the frequency of digital frequency detector detection periodic signal.Use numeral
When frequency detector detects the frequency of periodic signal, it is that periodic signal to be detected is joined known to frequency
Examine clock to compare.The frequency using digital frequency detector detection periodic signal is relatively simple, but
Needing the longer time just can complete detection, the detection time is several times of reference clock cycle.Specifically,
The detection time of digital frequency detector determines according to Tc=[Tmax ÷ (Tmax-Tmin)-0.5] × Tmax,
Wherein, Tc is the maximum time of digital frequency detector output comparative result, and Tmax is the cycle to be detected
Signal and the cycle of reference clock medium frequency smaller, Tmax is periodic signal to be detected and reference clock
The cycle of medium frequency the greater.
Summary of the invention
What the present invention solved is the long problem of frequency time of detection periodic signal.
For solving the problems referred to above, the present invention provides a kind of frequency detecting device, including:
Frequency-halving circuit, is suitable to that periodic signal to be detected carries out two divided-frequency and processes to produce fractional frequency signal；
Delay circuit, is suitable to described fractional frequency signal carry out delay process to produce time delayed signal；
Charge-discharge circuit, be suitable to when described time delayed signal is the first level described charge-discharge circuit is defeated
Go out end be charged or discharge, be second electrical level and described fractional frequency signal is described at described time delayed signal
During one level, the outfan to described charge-discharge circuit resets；
Comparison circuit, be suitable to compare when described time delayed signal is described second electrical level the first reference voltage and
The output voltage of described charge-discharge circuit is to produce the first comparison signal, to compare the second reference voltage and described
The output voltage of charge-discharge circuit is to produce the second comparison signal, and described first reference voltage is more than described the
Two reference voltages；
RS latch, is suitable to described first comparison signal and described second comparison signal are carried out latch process.
Optionally, described first level is high level, and described second electrical level is low level.
Optionally, described charge-discharge circuit include the first not circuit, AND circuit, charging current source,
PMOS transistor, nmos pass transistor and storage capacitor；
The input of described first not circuit is suitable to receive described time delayed signal, described first not circuit
Outfan connect the first input end of described AND circuit and the grid of described PMOS transistor；
Second input of described AND circuit is suitable to input described fractional frequency signal, described AND circuit defeated
Go out end and connect the grid of described nmos pass transistor；
First end of described charging current source is suitable to input supply voltage, the second end of described charging current source
Connect the source electrode of described PMOS transistor；
The drain electrode of described PMOS transistor connects the drain electrode of described nmos pass transistor and described storage capacitor
The first end and as the outfan of described charge-discharge circuit；
The source electrode of described nmos pass transistor and the second end of described storage capacitor are suitable to input reference potential.
Optionally, described charge-discharge circuit include the first not circuit, NAND gate circuit, discharge current source,
PMOS transistor, nmos pass transistor and storage capacitor；
The input of described first not circuit connects the grid of described nmos pass transistor and is suitable to receive institute
Stating time delayed signal, the outfan of described first not circuit connects the first input end of described NAND gate circuit；
Second input of described NAND gate circuit is suitable to receive described fractional frequency signal, described NAND gate circuit
Outfan connect described PMOS transistor grid；
The source electrode of described PMOS transistor is suitable to input supply voltage, the drain electrode of described PMOS transistor
Connect described nmos pass transistor drain electrode and described storage capacitor the first end and as described discharge and recharge electricity
The outfan on road；
The source electrode of described nmos pass transistor connects first end in described discharge current source；
Second end in described discharge current source and the second end of described storage capacitor are suitable to input reference potential.
Optionally, described reference potential is earth potential.
Optionally, described comparison circuit includes the first voltage comparator and the second voltage comparator；
The in-phase input end of described first voltage comparator is suitable to input described first reference voltage, and described
The inverting input of one voltage comparator connects the outfan of described charge-discharge circuit and described second voltage ratio
The in-phase input end of relatively device, the Enable Pin of described first voltage comparator connects described second voltage comparator
Enable Pin and be suitable to receive described time delayed signal, the outfan of described first voltage comparator be suitable to output
Described first comparison signal；
The inverting input of described second voltage comparator is suitable to input described second reference voltage, and described
The outfan of two voltage comparators is suitable to export described second comparison signal.
Optionally, described RS latch includes the first OR-NOT circuit, the second OR-NOT circuit, second non-
Gate circuit and the 3rd not circuit；
The first input end of described first OR-NOT circuit is suitable to receive described first comparison signal, and described
Second input of one OR-NOT circuit connects the outfan of described second OR-NOT circuit and described 3rd non-
The input of gate circuit, the outfan of described first OR-NOT circuit connects described second OR-NOT circuit
First input end and the input of described second not circuit；
Second input of described second OR-NOT circuit is suitable to receive described second comparison signal；
The outfan of described second not circuit as the first outfan of described RS latch, the described 3rd
The outfan of not circuit is as the second outfan of described RS latch.
Optionally, described frequency detecting device also includes being suitable to produce described first reference voltage and described
The reference voltage generating circuit of two reference voltages.
Optionally, described frequency detecting device also includes buffer, and described comparison circuit is by described buffering
Device receives the output voltage of described charge-discharge circuit；
The input of described buffer connects the outfan of described charge-discharge circuit, the output of described buffer
End connects described comparison circuit.
Compared with prior art, technical scheme has the advantage that
The frequency detecting device that the present invention provides, utilizes a cycle of periodic signal to be detected to fill
Electricity or electric discharge, the frequency of described periodic signal to be detected is converted into correspondence after charge or discharge terminate
Voltage, voltage corresponding after charge or discharge being terminated and two reference voltages compare, according to comparing
Result can know the relation of the frequency of described periodic signal to be detected and the frequency of two reference clocks.
Time owing to being charged or discharge is a cycle of described periodic signal to be detected, compares
Time be also cycle of described periodic signal to be detected, therefore, in the described cycle to be detected
Just can obtain testing result in three cycles of signal, save the detection time.
Further, comparison frequency is converted to compare voltage by the frequency detecting device that the present invention provides, described
The magnitude of voltage of two reference voltages is to be obtained by emulation, thus in circuit without necessarily referring to clock, joint
The about cost of described frequency detecting device.
Further, the comparison circuit in the frequency detecting device that the present invention provides, at cycle letter to be detected
Number two adjacent periods in, only in running order a cycle, quit work in another cycle,
Thus reduce the power consumption of described frequency detecting device.
In the alternative of the present invention, described frequency detecting device includes buffer, and described buffer can
Isolation charge-discharge circuit and comparison circuit, prevent charge-discharge circuit described in the voltage disturbance in comparison circuit
Output voltage, improves the accuracy of detection of described frequency detecting device.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of frequency detecting device that the embodiment of the present invention provides；
Fig. 2 is the structural representation of a kind of charge-discharge circuit that the embodiment of the present invention provides；
Fig. 3 is the working timing figure of the charge-discharge circuit shown in Fig. 2；
Fig. 4 is the structural representation of the another kind of charge-discharge circuit that the embodiment of the present invention provides；
Fig. 5 is the working timing figure of the charge-discharge circuit shown in Fig. 4；
Fig. 6 is the structural representation of the comparison circuit that the embodiment of the present invention provides；
Fig. 7 is the structural representation of the RS latch that the embodiment of the present invention provides；
Fig. 8 is the structural representation of the another kind of frequency detecting device that the embodiment of the present invention provides.
Detailed description of the invention
Technical solution of the present invention provides a kind of frequency detecting device, and described frequency detecting device is adapted to detect for week
Whether the frequency of phase square-wave signal is within scheduled frequency range.Fig. 1 is that the embodiment of the present invention provides
Planting the structural representation of frequency detecting device, described frequency detecting device includes frequency-halving circuit 11, time delay
Circuit 12, charge-discharge circuit 13, comparison circuit 14 and latch cicuit 15.
Specifically, described frequency-halving circuit 11 is suitable to carry out periodic signal Fin to be detected at two divided-frequency
Reason is to produce fractional frequency signal Fdi.As measured signal, described periodic signal Fin to be detected is that frequency is solid
Fixed square-wave signal, its dutycycle is random.Process through described two divided-frequency, described fractional frequency signal Fdi
The frequency that frequency is described periodic signal Fin to be detected 1/2nd, the most described fractional frequency signal Fdi
The twice in the cycle that the cycle is described periodic signal Fin to be detected, dutycycle is 50 percent.
Described delay circuit 12 is suitable to described fractional frequency signal Fdi is carried out delay process to produce time delayed signal
Fdl.Through described delay process, the rising edge of described time delayed signal Fdl lags behind described fractional frequency signal Fdi
Rising edge, the delayed time is the delay time of described delay process.It should be noted that it is described
The delay time of delay process can be configured according to the actual requirements, and this is not construed as limiting by the present invention.If institute
The dutycycle stating periodic signal Fin to be detected is less than or equal to 50 percent, prolonging of described delay process
Time the time less than the high level lasting time of described periodic signal Fin to be detected；If described week to be detected
The dutycycle of phase signal Fin is more than 50 percent, and the delay time of described delay process is less than described to be checked
The low duration of the periodic signal Fin surveyed.The frequency of described time delayed signal Fdl and described frequency dividing letter
The frequency of number Fdi is equal, and dutycycle is still 50 percent: in a cycle of described time delayed signal Fdl
In, high level and low level respectively account for the half period of described time delayed signal Fdl.
Described charge-discharge circuit 13 is suitable to when described time delayed signal Fdl is the first level described discharge and recharge
The outfan of circuit 13 is charged or discharges, and is second electrical level and described point at described time delayed signal Fdl
Frequently when signal Fdi is described first level, the outfan to described charge-discharge circuit 13 resets.Described
Time delayed signal Fdl only has high level and low level two states, described first level can be high level, phase
Answering described second electrical level is low level；Described first level can also be low level, the most described
Two level are high level, and this is not construed as limiting by the present invention.
Specifically, when described time delayed signal Fdl is the first level, i.e. at the half of described time delayed signal Fdl
In the individual cycle, its outfan is charged or discharges by described charge-discharge circuit 13, makes described discharge and recharge
The magnitude of voltage of the output voltage Vout of circuit 13 is raised and lowered to charging/discharging voltage value by initial voltage value；
When described time delayed signal Fdl is second electrical level and described fractional frequency signal Fdi is described first level, i.e. exist
Before described time delayed signal Fdl each cycle starts, its outfan is carried out multiple by described charge-discharge circuit 13
Position, makes the magnitude of voltage of the output voltage Vout of described charge-discharge circuit 13 be reduced by described charging/discharging voltage value
Or it is increased to described initial voltage value.
Described comparison circuit 14 is suitable to compare the first base when described time delayed signal Fdl is described second electrical level
The output end voltage of quasi-voltage Vref1 and described charge-discharge circuit 13 is to produce the first comparison signal C1, ratio
Letter is compared to produce second compared with the output end voltage of the second reference voltage V ref2 and described charge-discharge circuit 13
Number C2, described first reference voltage V ref1 is more than described second reference voltage V ref2.Specifically, described
Time delayed signal Fdl, as the enable signal of described comparison circuit 14, is described at described time delayed signal Fdl
During the first level, i.e. when its outfan is charged or discharges by described charge-discharge circuit 13, described
Comparison circuit 14 quits work；When described time delayed signal Fdl is described second electrical level, described comparison is electric
Output voltage Vout and two reference voltages of described charge-discharge circuit 13 are compared by road 14.
The magnitude of voltage of described first reference voltage V ref1 and described second reference voltage V ref2 can be by imitative
True acquisition.Specifically, corresponding first reference clock of described first reference voltage V ref1, described first reference
The frequency of clock is the first reference frequency；Corresponding second reference clock of described second reference voltage V ref2, institute
The frequency stating the second reference clock is the second reference frequency, described first reference frequency and described second benchmark
Frequency range between frequency is scheduled frequency range.
If the output to it when described time delayed signal Fdl is described first level of described charge-discharge circuit 13
End is charged, and described first reference frequency is less than described second reference frequency.During with described first reference
One cycle of clock carries out emulation charging to the outfan of described charge-discharge circuit 13, and charging is described after terminating
The magnitude of voltage of the outfan of charge-discharge circuit 13 is the magnitude of voltage of described first reference voltage V ref1；With
One cycle of described second reference clock carries out emulation charging to the outfan of described charge-discharge circuit 13,
The magnitude of voltage of the outfan that charging terminates rear described charge-discharge circuit 13 is described second reference voltage
The magnitude of voltage of Vref2.
If the output to it when described time delayed signal Fdl is described first level of described charge-discharge circuit 13
End discharges, and described first reference frequency is more than described second reference frequency.During with described first reference
One cycle of clock carries out emulation electric discharge to the outfan of described charge-discharge circuit 13, and electric discharge is described after terminating
The magnitude of voltage of the outfan of charge-discharge circuit 13 is the magnitude of voltage of described first reference voltage V ref1；With
One cycle of described second reference clock carries out emulation electric discharge to the outfan of described charge-discharge circuit 13,
The magnitude of voltage of the outfan that electric discharge terminates rear described charge-discharge circuit 13 is described second reference voltage
The magnitude of voltage of Vref2.
The magnitude of voltage of described first reference voltage V ref1 and the magnitude of voltage of described second reference voltage V ref2 are true
After Ding, can by described frequency detecting device external voltage source provide described first reference voltage V ref1 and
Described second reference voltage V ref2, it is also possible to produced by the internal circuit of described frequency detecting device.If by
The internal circuit of described frequency detecting device produces, and described frequency detecting device can also include reference voltage
Producing circuit, described reference voltage generating circuit is adapted to provide for described first reference voltage V ref1 and described the
Two reference voltage Vref2.
Output voltage Vout according to described charge-discharge circuit 13 and the relation of two reference voltages, can be true
The frequency of fixed described periodic signal Fin to be detected and the relation of two reference frequencies.With described discharge and recharge electricity
As a example by road 13 outfan to it when described time delayed signal Fdl is described first level is charged: if
The output voltage Vout of described charge-discharge circuit 13 be more than described first reference voltage V ref1, then described in treat
Second reference frequency described in first reference frequency ＜ described in frequency ＜ of the periodic signal Fin of detection；If it is described
The output voltage Vout of charge-discharge circuit 13 is less than described first reference voltage V ref1, described discharge and recharge electricity
The output voltage Vout on road 13 is more than described second reference voltage V ref2, the most described first reference frequency ＜
Second reference frequency described in frequency ＜ of described periodic signal Fin to be detected；If described charge-discharge circuit
The output voltage Vout of 13 is less than described second reference voltage V ref2, the most described first reference frequency ＜ institute
State the frequency of periodic signal Fin to be detected described in the second reference frequency ＜.
Described RS latch 15 is suitable to described first comparison signal C1 and described second comparison signal C2
Carry out latch process.Due to before described time delayed signal Fdl each cycle starts, described charge-discharge circuit
13 pairs of its outfans reset, and cause the output state of described comparison circuit 14 not keep.Therefore,
Described RS latch 15 is needed to latch described first comparison signal C1's and described second comparison signal C2
State.
The frequency detecting device that the embodiment of the present invention provides, utilizes the one of described periodic signal Fin to be detected
The outfan of described charge-discharge circuit 13 is charged or discharges by the individual cycle, described cycle letter to be detected
The frequency of number Fin is converted into the output voltage Vout of described charge-discharge circuit 13.By by described charge and discharge
Output voltage Vout and two reference voltages of electricity circuit 13 compare, and can know according to comparative result
The frequency of described periodic signal Fin to be detected and the relation of two reference frequencies.Owing to being charged or putting
In the cycle that time is described periodic signal Fin to be detected of electricity, the time compared is also for described
One cycle of periodic signal Fin to be detected, therefore, at the three of described periodic signal Fin to be detected
Just can obtain testing result in the individual cycle, save the detection time.
Further, comparison frequency is converted to compare voltage by the frequency detecting device that the embodiment of the present invention provides,
The magnitude of voltage of described first reference voltage V ref1 and the magnitude of voltage of described second reference voltage V ref2 can lead to
Cross emulation to determine, thus without necessarily referring to clock in described frequency detecting device, save described frequency
The cost of detection device.Further, described comparison circuit 14 is the two of described periodic signal Fin to be detected
In individual adjacent periods, only in running order a cycle, quit work in another cycle, thus
Reduce the power consumption of described frequency detecting device.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
In technical solution of the present invention, described frequency-halving circuit 11 can use existing frequency-halving circuit to tie
Structure, described delay circuit 12 can use existing delay circuit structure, and this is not construed as limiting by the present invention.
Described charge-discharge circuit 13 can have multiple implementation, with described first level as high level, described
As a example by two level are low level, Fig. 2 is a kind of described charge-discharge circuit 13 that the embodiment of the present invention provides
Structural representation.Described charge-discharge circuit 13 includes the first not circuit 21, AND circuit 22, charging
Current source 23, PMOS transistor P20, nmos pass transistor N20 and storage capacitor C20.
The input of described first not circuit 21 is suitable to receive described time delayed signal Fdl, described first non-
The outfan of gate circuit 21 connects the first input end of described AND circuit 22 and described PMOS transistor
The grid of P20.Second input of described AND circuit 22 is suitable to input described fractional frequency signal Fdi, described
The outfan of AND circuit 22 connects the grid of described nmos pass transistor N20.Described charging current source
First end of 23 is suitable to input supply voltage Vdd, and the second end of described charging current source 23 connects described
The source electrode of PMOS transistor P20.It is brilliant that the drain electrode of described PMOS transistor P20 connects described NMOS
The drain electrode of body pipe N20 and first end of described storage capacitor C20 defeated as described charge-discharge circuit 13
Go out end, i.e. produce described output voltage Vout.The source electrode of described nmos pass transistor N20 and described energy storage
Second end of electric capacity C20 is suitable to input reference potential.In the present embodiment, described reference potential is ground electricity
Position, the source electrode of the most described nmos pass transistor N20 and the second end ground connection of described storage capacitor C20.
Fig. 3 is the working timing figure of the charge-discharge circuit 13 shown in Fig. 2, below in conjunction with Fig. 2 and Fig. 3 pair
The operation principle of the charge-discharge circuit 13 of the embodiment of the present invention illustrates.Described first not circuit 21
Described time delayed signal Fdl is carried out anti-phase process, produces the inversion signal FdlB of described time delayed signal Fdl,
The inversion signal FdlB of described time delayed signal Fdl is as the control signal of described PMOS transistor.Described
AND circuit 22 the inversion signal FdlB and described fractional frequency signal Fdi of described time delayed signal Fdl are carried out with
Processing, produce reset signal Irst, described reset signal Irst is as described nmos pass transistor N20's
Control signal.
When described time delayed signal Fdl is described first level, it is i.e. high level at described time delayed signal Fdl
Time, the inversion signal FdlB of described time delayed signal Fdl is low level, and described reset signal Irst is low electricity
Flat.The inversion signal FdlB of described time delayed signal Fdl controls the conducting of described PMOS transistor P20, institute
Stating reset signal Irst and control described nmos pass transistor N20 cut-off, described charging current source 23 passes through
Described storage capacitor C20 is charged by described PMOS transistor P20, i.e. to described charge-discharge circuit
The outfan of 13 is charged, and makes described output voltage Vout constantly raise and is finally reached stably.
When described time delayed signal Fdl is described second electrical level, it is i.e. low level at described time delayed signal Fdl
Time, the inversion signal FdlB of described time delayed signal Fdl is high level, controls described PMOS transistor P20
Cut-off.Described time delayed signal Fdl controls described comparison circuit 14 and works, and described comparison circuit 14 is by described
Output voltage Vout and two reference voltages compare to produce described first comparison signal C1 and described
Second comparison signal C2.
It is described second electrical level and described fractional frequency signal Fdi is described first level at described time delayed signal Fdl
Time, i.e. when described time delayed signal Fdl is low level and described fractional frequency signal Fdi is high level, described in prolong
Time signal Fdl inversion signal FdlB be high level, described reset signal Irst is high level.Described prolong
Time signal Fdl inversion signal FdlB control described PMOS transistor P20 cut-off, described reset signal
Irst controls described nmos pass transistor N20 conducting, resets described storage capacitor C20, the most right
The outfan of described charge-discharge circuit 13 resets, and described output voltage Vout is reduced to initial voltage.
Charge-discharge circuit 13 shown in Fig. 2 is that the outfan to it is charged.Still with described first level
As a example by being low level for high level, described second electrical level, Fig. 4 is the another kind that the embodiment of the present invention provides
The structural representation of described charge-discharge circuit 13, described charge-discharge circuit 13 is that the outfan to it is carried out
Electric discharge.With reference to Fig. 4, described charge-discharge circuit 13 include the first not circuit 41, NAND gate circuit 42,
Discharge current source 43, PMOS transistor P40, nmos pass transistor N40 and storage capacitor C40.
The input of described first not circuit 41 connects the grid of described nmos pass transistor N20 and fits
In receiving described time delayed signal Fdl, the outfan of described first not circuit 41 connects described NAND gate electricity
The first input end on road 42.Second input of described NAND gate circuit 42 is suitable to receive described frequency dividing letter
Number Fdi, the outfan of described NAND gate circuit 42 connects the grid of described PMOS transistor P20.Institute
The source electrode stating PMOS transistor P20 is suitable to input supply voltage Vdd, described PMOS transistor P20
Drain electrode connect the drain electrode of described nmos pass transistor N20 and first end of described storage capacitor C20 and make
For the outfan of described charge-discharge circuit 13, i.e. produce described output voltage Vout.Described NMOS is brilliant
The source electrode of body pipe N20 connects first end in described discharge current source 43, the of described discharge current source 23
Second end of two ends and described storage capacitor C20 is suitable to input reference potential.In the present embodiment, described
Reference potential is earth potential, second end in the most described discharge current source 23 and the of described storage capacitor C20
Two end ground connection.
Fig. 5 is the working timing figure of the charge-discharge circuit 13 shown in Fig. 4, below in conjunction with Fig. 4 and Fig. 5 pair
The operation principle of the charge-discharge circuit 13 of the embodiment of the present invention illustrates.Described first not circuit 41
Described time delayed signal Fdl is carried out anti-phase process, produces the inversion signal FdlB of described time delayed signal Fdl.
The described NAND gate circuit 42 inversion signal FdlB and described fractional frequency signal Fdi to described time delayed signal Fdl
Carrying out and non-process, produce reset signal Irst, described reset signal Irst is as described nmos pass transistor
The control signal of N40.
When described time delayed signal Fdl is described first level, it is i.e. high level at described time delayed signal Fdl
Time, the inversion signal FdlB of described time delayed signal Fdl is low level, and described reset signal Irst is high electricity
Flat.Described time delayed signal Fdl controls described nmos pass transistor N40 conducting, described reset signal Irst
Controlling the cut-off of described PMOS transistor P40, described discharge current source 43 is by described NMOS crystal
Described storage capacitor C40 is discharged by pipe N40, i.e. carries out the outfan of described charge-discharge circuit 13
Electric discharge, makes described output voltage Vout constantly reduce and is finally reached stably.
When described time delayed signal Fdl is described second electrical level, it is i.e. low level at described time delayed signal Fdl
Time, described time delayed signal Fdl controls described nmos pass transistor N40 cut-off.Described time delayed signal Fdl
Controlling described comparison circuit 14 to work, described comparison circuit 14 is by described output voltage Vout and two bases
Quasi-voltage compares to produce described first comparison signal C1 and described second comparison signal C2.
It is described second electrical level and described fractional frequency signal Fdi is described first level at described time delayed signal Fdl
Time prolong described in when described time delayed signal Fdl is low level and described fractional frequency signal Fdi is high level
Time signal Fdl inversion signal FdlB be high level, described reset signal Irst is low level.Described prolong
Time signal Fdl control described nmos pass transistor N40 cut-off, described reset signal Irst controls described
PMOS transistor P40 turns on, and resets described storage capacitor C40, i.e. to described discharge and recharge electricity
The outfan on road 13 resets, and described output voltage Vout is increased to initial voltage.
The embodiment of the present invention provides the circuit structure of a kind of described comparison circuit 14, as shown in Figure 6, described
Comparison circuit 14 includes the first voltage comparator 61 and the second voltage comparator 62.Specifically, described
The in-phase input end of one voltage comparator 61 is suitable to input described first reference voltage V ref1, and described first
The inverting input of voltage comparator 61 connects the outfan of described charge-discharge circuit 13 and described second electricity
The in-phase input end of pressure comparator 62, Enable Pin EN1 of described first voltage comparator 61 connects described
Enable Pin EN2 of the second voltage comparator 62 is also suitable to receive described time delayed signal Fdl, described first electricity
The outfan of pressure comparator 61 is suitable to export described first comparison signal C1；Described second voltage comparator
The inverting input of 62 is suitable to input described second reference voltage V ref2, described second voltage comparator 62
Outfan be suitable to export described second comparison signal C2.
Described time delayed signal Fdl is as described first voltage comparator 61 and described second voltage comparator 62
Enable signal, its level state controls described first voltage comparator 61 and described second voltage comparator
Whether 62 work.When described time delayed signal Fdl is described first level, described first voltage comparator
61 and described second voltage comparator 62 do not work；When described time delayed signal Fdl is described second electrical level,
Defeated by described charge-discharge circuit 13 of described first voltage comparator 61 and described second voltage comparator 62
Go out voltage Vout to compare with reference voltage.
Specifically, if filling described in the first reference voltage V ref1 ＜ described in described second reference voltage V ref2 ＜
The output voltage Vout of discharge circuit 13, the most described first comparison signal C1 be low level, described second
Comparison signal C2 is high level；If charge-discharge circuit 13 is defeated described in described second reference voltage V ref2 ＜
Go out the first reference voltage V ref1 described in voltage Vout ＜, the most described first comparison signal C1 be high level,
Described second comparison signal C2 is high level；If the output voltage Vout ＜ institute of described charge-discharge circuit 13
Stating the first reference voltage V ref1 described in the second reference voltage V ref2 ＜, the most described first comparison signal C1 is
High level, described second comparison signal C2 are low level.
The embodiment of the present invention provides the circuit structure of a kind of described RS latch 15, as it is shown in fig. 7, institute
State RS latch 15 and include first OR-NOT circuit the 71, second OR-NOT circuit the 72, second not circuit
73 and the 3rd not circuit 74.Specifically, the first input end of described first OR-NOT circuit 71 is fitted
In receiving described first comparison signal C1, the second input of described first OR-NOT circuit 71 connects institute
State outfan and the input of described 3rd not circuit 74 of the second OR-NOT circuit 72, described first
The outfan of OR-NOT circuit 71 connects the first input end and described the of described second OR-NOT circuit 72
The input of two not circuits 73.Second input of described second OR-NOT circuit 71 is suitable to receive institute
State the second comparison signal C2.The outfan of described second not circuit 73 is as described RS latch 15
The first outfan, be suitable to produce the first latch signal S1；The outfan of described 3rd not circuit 74 is made
For the second outfan of described RS latch 15, be suitable to produce the first latch signal S2.Art technology
Personnel know the operation principle of described RS latch 15, do not repeat them here.
Fig. 8 is the structural representation of the another kind of frequency detecting device that the embodiment of the present invention provides, described frequency
Rate detection device include frequency-halving circuit 81, delay circuit 82, charge-discharge circuit 83, comparison circuit 84,
RS latch 85 and buffer 86, described comparison circuit 84 receives described by described buffer 86
The output voltage Vout of charge-discharge circuit 83.Described frequency-halving circuit 81, described delay circuit 82, institute
State charge-discharge circuit 83, described comparison circuit 84 and the concrete structure of described RS latch 85 and former
Managing the structure corresponding with Fig. 1 to be similar to, the input of described buffer 86 connects described charge-discharge circuit 73
Outfan, the outfan of described buffer 86 connects described comparison circuit 84.Through described buffer
The isolation of 86, prevents the voltage in described comparison circuit 84 from making the outfan of described charge-discharge circuit 83
Become interference, thus provide the accuracy of detection of described frequency detecting device.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (7)
1. a frequency detecting device, it is characterised in that including:
Frequency-halving circuit, is suitable to that periodic signal to be detected carries out two divided-frequency and processes to produce fractional frequency signal；
Delay circuit, is suitable to described fractional frequency signal carry out delay process to produce time delayed signal；
Charge-discharge circuit, be suitable to when described time delayed signal is the first level described charge-discharge circuit is defeated
Go out end be charged or discharge, be second electrical level and described fractional frequency signal is described at described time delayed signal
During one level, the outfan to described charge-discharge circuit resets；
Comparison circuit, be suitable to compare when described time delayed signal is described second electrical level the first reference voltage and
The output voltage of described charge-discharge circuit is to produce the first comparison signal, to compare the second reference voltage and described
The output voltage of charge-discharge circuit is to produce the second comparison signal, and described first reference voltage is more than described the
Two reference voltages；
RS latch, is suitable to described first comparison signal and described second comparison signal are carried out latch process；
Described first level is high level, and described second electrical level is low level；
Described charge-discharge circuit includes that the first not circuit, AND circuit, charging current source, PMOS are brilliant
Body pipe, nmos pass transistor and storage capacitor；
The input of described first not circuit is suitable to receive described time delayed signal, described first not circuit
Outfan connect the first input end of described AND circuit and the grid of described PMOS transistor；
Second input of described AND circuit is suitable to input described fractional frequency signal, described AND circuit defeated
Go out end and connect the grid of described nmos pass transistor；
First end of described charging current source is suitable to input supply voltage, the second end of described charging current source
Connect the source electrode of described PMOS transistor；
The drain electrode of described PMOS transistor connects the drain electrode of described nmos pass transistor and described storage capacitor
The first end and as the outfan of described charge-discharge circuit；
The source electrode of described nmos pass transistor and the second end of described storage capacitor are suitable to input reference potential.
2. frequency detecting device as claimed in claim 1, it is characterised in that described charge-discharge circuit includes the
One not circuit, NAND gate circuit, discharge current source, PMOS transistor, nmos pass transistor and
Storage capacitor；
The input of described first not circuit connects the grid of described nmos pass transistor and is suitable to receive institute
Stating time delayed signal, the outfan of described first not circuit connects the first input end of described NAND gate circuit；
Second input of described NAND gate circuit is suitable to receive described fractional frequency signal, described NAND gate circuit
Outfan connect described PMOS transistor grid；
The source electrode of described PMOS transistor is suitable to input supply voltage, the drain electrode of described PMOS transistor
Connect described nmos pass transistor drain electrode and described storage capacitor the first end and as described discharge and recharge electricity
The outfan on road；
The source electrode of described nmos pass transistor connects first end in described discharge current source；
Second end in described discharge current source and the second end of described storage capacitor are suitable to input reference potential.
3. require the frequency detecting device as described in 1 such as claim, it is characterised in that described reference potential is ground
Current potential.
4. frequency detecting device as claimed in claim 1, it is characterised in that described comparison circuit includes first
Voltage comparator and the second voltage comparator；
The in-phase input end of described first voltage comparator is suitable to input described first reference voltage, and described
The inverting input of one voltage comparator connects the outfan of described charge-discharge circuit and described second voltage ratio
The in-phase input end of relatively device, the Enable Pin of described first voltage comparator connects described second voltage comparator
Enable Pin and be suitable to receive described time delayed signal, the outfan of described first voltage comparator be suitable to output
Described first comparison signal；
The inverting input of described second voltage comparator is suitable to input described second reference voltage, and described
The outfan of two voltage comparators is suitable to export described second comparison signal.
5. frequency detecting device as claimed in claim 1, it is characterised in that described RS latch includes the
One OR-NOT circuit, the second OR-NOT circuit, the second not circuit and the 3rd not circuit；
The first input end of described first OR-NOT circuit is suitable to receive described first comparison signal, and described
Second input of one OR-NOT circuit connects the outfan of described second OR-NOT circuit and described 3rd non-
The input of gate circuit, the outfan of described first OR-NOT circuit connects described second OR-NOT circuit
First input end and the input of described second not circuit；
Second input of described second OR-NOT circuit is suitable to receive described second comparison signal；
The outfan of described second not circuit as the first outfan of described RS latch, the described 3rd
The outfan of not circuit is as the second outfan of described RS latch.
6. the frequency detecting device as described in any one of claim 1 to 5, it is characterised in that also include being suitable to
Produce described first reference voltage and the reference voltage generating circuit of described second reference voltage.
7. frequency detecting device as claimed in claim 6, it is characterised in that also include buffer, described ratio
Relatively circuit is by the output voltage of charge-discharge circuit described in described buffer inputs；
The input of described buffer connects the outfan of described charge-discharge circuit, the output of described buffer
End connects described comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410353764.9A CN104122441B (en) | 2014-07-23 | 2014-07-23 | Frequency detecting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410353764.9A CN104122441B (en) | 2014-07-23 | 2014-07-23 | Frequency detecting device |
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| CN104122441A CN104122441A (en) | 2014-10-29 |
| CN104122441B true CN104122441B (en) | 2016-08-24 |
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| CN201410353764.9A Active CN104122441B (en) | 2014-07-23 | 2014-07-23 | Frequency detecting device |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106918740B (en) * | 2015-12-28 | 2020-06-19 | 普源精电科技股份有限公司 | Equal-precision frequency measurement device and method |
| CN113890517A (en) * | 2021-09-29 | 2022-01-04 | 电子科技大学 | Analog frequency comparator |
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| CN103645379A (en) * | 2013-10-24 | 2014-03-19 | 重庆西南集成电路设计有限责任公司 | TTL signal frequency hopping monitoring system and method |
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| GB1440937A (en) * | 1972-04-14 | 1976-06-30 | Licentia Gmbh | Circuit arrangement for picking up a limit frequency of an alternating voltage network |
| CN1340717A (en) * | 2000-08-14 | 2002-03-20 | 日本电气株式会社 | Frequency judgement circuit for data processing unit |
| CN1514255A (en) * | 2002-12-25 | 2004-07-21 | 恩益禧电子股份有限公司 | Frequency detecting circuit and data processor |
| CN101610024A (en) * | 2008-06-20 | 2009-12-23 | 尼克森微电子股份有限公司 | The frequency generator of tool frequency jitter and PDM keyer |
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| CN104122441A (en) | 2014-10-29 |
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