CN104113308A - Multiplex pulse accumulating frequency divider used for pulse synthesis - Google Patents
Multiplex pulse accumulating frequency divider used for pulse synthesis Download PDFInfo
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- CN104113308A CN104113308A CN201410338624.4A CN201410338624A CN104113308A CN 104113308 A CN104113308 A CN 104113308A CN 201410338624 A CN201410338624 A CN 201410338624A CN 104113308 A CN104113308 A CN 104113308A
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Abstract
The invention discloses a multiplex pulse accumulating frequency divider used for pulse synthesis. The multiplex pulse accumulating frequency divider used for the pulse synthesis is composed of a signal conditioning circuit (2), a CPLD (3), a clock (4), a frequency division selecting circuit (6) and a power supply (9). Complex pulse signals f<1>, f<2>, ..., f<n> (0-2 MHz) to be measured are conditioned through the signal conditioning circuit (2) to obtain shaped pulse signals, the shaped pulse signals output from the signal conditioning circuit (2) are synthesized into one path of pulse signal f<c> (0-6 MHz) (5) through the CPLD (3), the frequency of the synthesized pulse signal f<c> (0-6 MHz) (5) is regulated through the frequency division selecting circuit (6), and an output drive circuit outputs the regulated pulse signal FORMULA (shown in the description) (0-6 MHz) (7). The output FORMULA (shown in the description) is compared with a standard signal to calculate an error so as to improve the test precision. The comprehensive and deep understanding for the complex pulse signals is reinforced through the pulse synthesis frequency divider, the time and vigor are reduced for the worker, and the operability and convenience are good. The multiplex pulse accumulating frequency divider used for the pulse synthesis guarantees the equity, scientificity and reliability of the test result.
Description
Technical field
The present invention relates to a kind of pulse signal and synthesize and detection technique, belong to pulse signal process field.
Background technology
In the research of external paired pulses synthetic technology, starting relatively early.Wiliam Henry Eccles in 1918 and Frank Wilfred Jordan are common bistable circuit, utilizes spike to trigger and forms rectangular pulse waveform, thereby started impulse waveform synthetic technology (adopting active type pulse-generating circuit).Between ensuing 20 years, the transistor circuit of take based on Triggered Oscillation principle is also enriched constantly and improves as basic impulse waveform synthetic technology, thereby established the synthetic technology basis of low frequency rectangular pulse waveform, and various countries scholar and researcher are still updating circuits for triggering structure up to now.Triggered Oscillation technology and shaping technique constantly merge, and have further promoted the development of pulse synthetic technology.External company's paired pulses synthetic technology is is also researched and developed a large amount of products, as Agilent and Tektronix Zhe Liang company in the research of Electronic Testing measuring instrument in absolute leading position.81100 series are Agilent company core products in pulse generator development.There are again the models such as 81130A, 81101A, 8114A, 81110A, 81104A, 8133A and 81141A this large series the inside, and each model exists the difference in index according to concrete application.Except Agilent and Tektronix Zhe Liang company, also have some foreign corporations to obtain good achievement.The product of these companies is difficult to see on market, need to be applied to some specific test occasions, the index of the several models of article in this article, and the research of paired pulses synthetic technology has higher reference value.The high repetition frequency that 9500 and 9600 series of pulses signal generators of Quantum Composers company achievement development can be realized is lower, only has 100MHz.But the maximum delay of pulse signal can reach 1000 seconds, the number of pulse train is 1 ~ 1000000.There are 8 passages that can independently programme and export.The CPDL-100A-020 type pulse generator of Colby Instruments company development, its time delay resolution is 0.5ps, and the maximum data rate of output data can reach 40Gb/s, and delay precision is 0.1% ± 0.20ps.In addition, also have Henghe, Amway, FLUKE, rock is rugged and there is very considerable strength in the company such as Aeroflex in pulse synthetic technology.Present stage, the company or the scientific research institution that are engaged at home the research of pulse synthetic technology mainly contain University of Electronic Science and Technology, the Ningbo second best plan, Chengdu Striker Electronics Instrument Ltd., Nantong Nan Feng electronics and Xin Lian electronics etc.Wherein, University of Electronic Science and Technology starts to walk early in the research of pulse signal generator, in relatively leading position.University of Electronic Science and Technology has developed certain type pulse generator in 2004, its maximum repetition pulse frequency reaches 100MHz, and minimum pulse width is 5ns, and the rise/fall time is less than 2ns, has multiple output of pulse signal pattern simultaneously.Therefore, aspect the research and development of pulse signal generator, mostly the electronics corporation of field tests and research and development institution are all also in stage of starting or ground zero not yet, existing most domestic pulse signal product-derived is all to copy superseded product of developed country, and the technology adopting also lags behind developed country greatly.
In universal test, measured signal becomes increasingly complex, and the synthetic change-over circuit of pulse signal need to be for equipment under test provides at a high speed, high-precision pulse signal.In pulsed test signal, multiplex pulse signal converts a road pulse and calibration pulse to and does error analysis and directly do error analysis with calibration pulse signal with multiplex pulse signal and compare, and the former test error analysis result wants much accurate.
Summary of the invention
Object of the present invention, being, by synthetic required, the controlled pulse signal of complicated pulse signal, provides a kind of synthetic multiplex pulse accumulation frequency divider of pulse that is applied to.
Be applied to the synthetic multiplex pulse accumulation frequency divider of pulse, the present invention includes allocator module and power supply, wherein the signal conditioning circuit in allocator module, CPLD, frequency division select circuit sequentially to connect, and clock is connected with CPLD; Power supply is connected with allocator module.
Signal conditioning circuit of the present invention comprises pulse shaper, positive-negative-positive triode switch and clamping protective circuit; Wherein, pulse shaper is comprised of precision resistance and electric capacity, and clamping protective circuit is comprised of precision resistance, clamper protection diode, 5V DC power supply; Pulse shaper, positive-negative-positive triode switch, clamping protective circuit sequentially connect to form Liao Yi road pulse signal modulate circuit, and some roads pulse signal modulate circuit has connected to form multiplex pulse signal modulate circuit with encoder respectively.
The pulse signal to be measured (0 ~ 2MHz) of complexity is obtained to shaped pulse signal by signal conditioning circuit, the shaped pulse signal of signal conditioning circuit output synthesizes a road pulse signal (0 ~ 6MHz) by CPLD, by frequency division, select circuit that the frequency of adjusting composite pulse signal (0 ~ 6MHz) is set, output driving circuit is by the output of pulse signal (0 ~ 6MHz) after adjusting.
The beneficial effect of the invention is:
(1) by pulse, synthesize frequency divider, the pulse signal that is not easy it to carry out directly testing of complexity can be converted to the standard signal that collecting device can be identified, and the pulse signal that frequency is adjustable, then carry out error calculating with standard signal, improved measuring accuracy;
(2) by pulse, synthesize frequency divider, strengthen the comprehensive and deep understanding of complicated pulse signal, for staff has reduced time and efforts, there is fine operability, convenience;
(3) by pulse, synthesize frequency divider, can realize and reduce complicated pulsed test signal error, guaranteed fairness, science and the reliability of test result.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is signal conditioning circuit schematic diagram of the present invention;
Fig. 3 is CPLD design principle figure of the present invention;
Fig. 4 is that frequency division of the present invention is selected circuit theory diagrams;
Fig. 5 is output driving circuit schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Be applied to the synthetic multiplex pulse accumulation frequency divider of pulse, the present invention includes allocator module 8 and power supply 9, wherein the signal conditioning circuit 2 in allocator module 8, CPLD 3, frequency division select circuit 6 sequentially to connect, and clock 4 is connected with CPLD 3; Power supply 9 is connected with allocator module 8.
Signal conditioning circuit 2 of the present invention comprises pulse shaper 11, positive-negative-positive triode switch 12 and clamping protective circuit 13; Wherein, pulse shaper 11 is comprised of precision resistance and electric capacity, and clamping protective circuit 13 is comprised of precision resistance, clamper protection diode, 5V DC power supply; Pulse shaper 11, positive-negative-positive triode switch 12, clamping protective circuit 13 sequentially connect to form Liao Yi road pulse signal modulate circuit 10, and some roads pulse signal modulate circuit 10 has connected to form multiplex pulse signal modulate circuit with encoder 14 respectively.
The present invention is by the pulse signal to be measured of complexity
(0 ~ 2MHz) 1 obtains shaped pulse signal by signal conditioning circuit 2, and the shaped pulse signal of signal conditioning circuit 2 outputs is by the synthetic road pulse signal of CPLD 3
(0 ~ 6MHz) 5, selects circuit 6 to arrange by frequency division and adjusts composite pulse signal
the frequency of (0 ~ 6MHz) 5, output driving circuit is by the output of pulse signal (0 ~ 6MHz) 7 after adjusting.
The present invention is a kind of pulse signal to be measured of complexity
(0 ~ 2MHz) converts by signal conditioning circuit the standard signal that collecting device can be identified to, for the ease of setting forth and representing signal conditioning circuit Yi San of the present invention road pulse signal
input shaper is example.
Pulse shaper 11 is comprised of three precision resistance R2, R3, R4 and capacitor C 1, C2 as shown in Figure 2; positive-negative-positive triode switch 12; clamping protective circuit 13 is comprised of precision resistance R1, clamper protection diode, 5V DC power supply; pulse shaper 11, positive-negative-positive triode switch 12, clamping protective circuit 13 sequentially connect to form 10, three pulse signal modulate circuits 10 of Liao Yi road pulse signal modulate circuit and have connected to form pulse signal with encoder 14 respectively
modulate circuit.
Diode clamp protective circuit in modulate circuit is to make the signal voltage of IO35 output not higher than 5V, guarantees that CPLD is not burned.
As shown in Figure 4, frequency division select circuit by+5V DC power supply 15,16,8 encoders 17 of multitool multithrow switch, link 19,8 encoders 18 of line end with CPLD and form.
Frequency division selects to select in circuit multitool multithrow switch 16 to select to be converted into by the signal frequency after shaping pulse the standard signal that collection, testing equipment can be identified, multitool multithrow switch 16 can be set to 256 kinds of states, such as the state such as frequency division, 10 frequency divisions, 100 frequency divisions not.
As shown in Figure 5, output driving circuit is comprised of electric capacity 20, precision resistance 21, precision resistance 22, PNP triode switch 23, precision resistance 24,25,4 encoders 26 of+5V DC power supply.
Claims (2)
1. one kind is applied to the synthetic multiplex pulse accumulation frequency divider of pulse, it is characterized in that, comprise allocator module (8) and power supply (9), signal conditioning circuit (2), the CPLD(3 in allocator module (8) wherein), frequency division selects circuit (6) sequentially to connect, clock (4) and CPLD(3) be connected; Power supply (9) is connected with allocator module (8).
2. a kind of synthetic multiplex pulse accumulation frequency divider of pulse that is applied to according to claim 1, is characterized in that, signal conditioning circuit (2) comprises pulse shaper (11), positive-negative-positive triode switch (12) and clamping protective circuit (13); Wherein, pulse shaper (11) is comprised of precision resistance and electric capacity, and clamping protective circuit (13) is comprised of precision resistance, clamper protection diode, 5V DC power supply; Pulse shaper (11), positive-negative-positive triode switch (12), clamping protective circuit (13) sequentially connect to form Liao Yi road pulse signal modulate circuit (10), and some road pulse signal modulate circuits (10) have connected to form multiplex pulse signal modulate circuit with encoder (14) respectively.
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| CN201410338624.4A CN104113308A (en) | 2014-07-16 | 2014-07-16 | Multiplex pulse accumulating frequency divider used for pulse synthesis |
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| CN201410338624.4A CN104113308A (en) | 2014-07-16 | 2014-07-16 | Multiplex pulse accumulating frequency divider used for pulse synthesis |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113376585A (en) * | 2021-05-21 | 2021-09-10 | 电子科技大学 | High-resolution pulse signal synthesizer |
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| US7076215B1 (en) * | 1999-03-12 | 2006-07-11 | Siemens Aktiengesellschaft | Transmitter-receiver |
| CN101087141A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Idle percent adjustable N-time frequency division circuit of pulse mixing mode |
| CN101539061A (en) * | 2009-04-24 | 2009-09-23 | 天津大学 | Internal-combustion engine electronic control development system based on industrial computer |
| CN202189462U (en) * | 2011-09-15 | 2012-04-11 | 长沙威胜信息技术有限公司 | Concentrator M-bus main machine |
| CN103269218A (en) * | 2013-04-19 | 2013-08-28 | 西安交通大学 | Implementation method for arbitrary fractional divider based on FPGA/CPLD |
| CN204119193U (en) * | 2014-07-16 | 2015-01-21 | 云南电力试验研究院（集团）有限公司电力研究院 | A kind of multiplex pulse accumulation frequency divider being applied to pulse combination |
-
2014
- 2014-07-16 CN CN201410338624.4A patent/CN104113308A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076215B1 (en) * | 1999-03-12 | 2006-07-11 | Siemens Aktiengesellschaft | Transmitter-receiver |
| CN101087141A (en) * | 2007-07-10 | 2007-12-12 | 中国人民解放军国防科学技术大学 | Idle percent adjustable N-time frequency division circuit of pulse mixing mode |
| CN101539061A (en) * | 2009-04-24 | 2009-09-23 | 天津大学 | Internal-combustion engine electronic control development system based on industrial computer |
| CN202189462U (en) * | 2011-09-15 | 2012-04-11 | 长沙威胜信息技术有限公司 | Concentrator M-bus main machine |
| CN103269218A (en) * | 2013-04-19 | 2013-08-28 | 西安交通大学 | Implementation method for arbitrary fractional divider based on FPGA/CPLD |
| CN204119193U (en) * | 2014-07-16 | 2015-01-21 | 云南电力试验研究院（集团）有限公司电力研究院 | A kind of multiplex pulse accumulation frequency divider being applied to pulse combination |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113376585A (en) * | 2021-05-21 | 2021-09-10 | 电子科技大学 | High-resolution pulse signal synthesizer |
| CN113376585B (en) * | 2021-05-21 | 2022-03-15 | 电子科技大学 | High-resolution pulse signal synthesizer |
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