CN104112696B - A kind of method for solving the problems, such as copper surface indentation after silicon hole layering and CMP - Google Patents
A kind of method for solving the problems, such as copper surface indentation after silicon hole layering and CMP Download PDFInfo
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- CN104112696B CN104112696B CN201310136082.8A CN201310136082A CN104112696B CN 104112696 B CN104112696 B CN 104112696B CN 201310136082 A CN201310136082 A CN 201310136082A CN 104112696 B CN104112696 B CN 104112696B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
The present invention provides a kind of scheme for solving the problems, such as copper surface indentation after silicon hole layering and CMP, including step：1）Silicon hole is formed in the silicon substrate that surface has stop-layer, in the silicon hole and surface of silicon deposition silica separation layer, in silica insulation surface formation barrier layer and Seed Layer；2）In the Seed Layer electroplating surface copper, the copper at least filling up the silicon hole is formed；3）Said structure is made annealing treatment, including：3‑1）With 0.5 ~ 5 DEG C/min from room temperature to 80 ~ 200 DEG C, 0 ~ 60min is incubated；3‑2）250 ~ 450 DEG C are warming up to 1 ~ 10 DEG C/min, 15 ~ 180min is incubated；3‑3）25 ~ 100 DEG C are cooled to 1 ~ 5 DEG C/min；4）It is polished using chemically mechanical polishing CMP, until exposing the stop-layer.The present invention effectively eliminates the lamination in silicon hole technique by improving the baking process to silicon substrate and the annealing process to copper, and solves the problems, such as copper depression in the surface after CMP, and method and step is simple, does not increase process costs, it is adaptable to industrial production.
Description
Technical field
The present invention relates to a silicon hole process integration scheme, more particularly to one solution through-silicon via sidewall plural layers
The scheme for the problem of copper surface is jagged after the lamination problem and CMP of structure or even is recessed.
Background technology
Chip is carried out three-dimensional stacked and by penetrating the perpendicular interconnection of Silicon Wafer or chip so that integrated circuit is surpassed
More Moore's Law and develop.Silicon hole (Through Silicon Via, TSV) is the core technology of interlayer perpendicular interconnection.Support
Two essential technologies of TSV technology are wafer thinning and binding.The main application direction of the three-dimensional stacked technology of chip
Including：1) three-dimensional packaging technology reduces the size of encapsulation, so as to reduce production cost；2) will be using different process difference lining
Bottom material even it is various sizes of it is heterogeneous it is chip-stacked together, constitute a complete microcircuit system；3) circuit of the same race
It can split and be stacked up, such as stack storage chip.Really it is designed to that 3D circuit is also developing.
TSV technology consists essentially of three kinds, first drills (Via-First), drill (Via-Last) and central bore afterwards
(Via-Middle).Via-First refer to TSV chip processing procedure most start make, followed by complete leading portion device (FEOL,
Front End of Line) and back segment interconnection (BEOL, Back End of Line) part.Via-Last refers in chip
FEOL and BEOL all after the completion of remanufacture TSV.Via-Middle then refers to that TSV processing procedures are inserted after FEOL is further continued for BEOL
Interconnection process.Via-Middle has become the processing procedure that three dimensional integrated circuits volume production is generally used.It is a major advantage that TSV not
, again can be using processing procedure compatible such as 400 degrees Celsius higher of BEOL with the high temperature process for being subjected to FEOL and being up to thousands of degree.
Via-Last processing procedures are because the processing procedure that existing BEOL structures TSV can be used must as little as 250 or even 200 degrees Celsius.
As shown in Fig. 1~Fig. 2, a kind of existing Via-Middle silicon holes process.It is carried out in FEOL Contact
Afterwards, then etch as stop-layer (Stop Layer) in surface of silicon deposited silicon nitride and form silicon hole.In silicon hole and
Deposition silica sinks again afterwards as dielectric isolation layer (Dielectric Isolation Layer) in surface of silicon
Ta./TaN is accumulated as stop and tack coat (Barrier and Adhesion Layer) and copper seed layer (Seed Layer),
Last electro-coppering filling silicon through holes.Copper surface topography has bulge-structure and sunk structure, as shown in A in figure and B.Electro-coppering it
After need to anneal to copper.The existing corresponding flow curve of copper Annealing Scheme is as shown in figure 3, its programming rate (Ramp-Up
Rate), cooling rate (Ramp-Down Rate) and annealing temperature (Anneal Temperature) are all higher.Because it is protected
Temperature (Standby Temperature) is located at 300 degrees centigrades, and silicon chip is sent directly into about 300 degrees Celsius from room temperature
In Chamber.Similar, annealing terminates again directly from about 300 degrees Celsius are retrieved room temperature.
After copper annealing, CMP is carried out to copper by surface rubbing, remove copper, barrier layer and the silica of silicon chip surface every
Absciss layer is until stop-layer.Etch away after stop-layer exposes Contact, you can to continue last part technology.
First problem is that occur breach (Pits) between copper and barrier layer after CMP, is also occurred in the TSV of silicon chip edge
The phenomenon of whole copper surface indentation and out-of-flatness.The metal level of deposition covering silicon hole is unable to uniformly continuous in last part technology
Ground protects silicon hole.If there is crack, the copper in silicon hole will be diffused out by crack, corrode the chemicals meeting of copper
By copper corrosion and it is extended to inside silicon hole, forms a cavity on the top of silicon hole, cause component failure.
Second Problem is each layer film of through-silicon via sidewall deposition because each thermal expansion is different, in successive process
There is layering (Delamination or Crack), cause fail-safe analysis to fail.
Therefore it provides copper surface gap and the scheme of depression problem are necessary after a kind of solution silicon hole layering and CMP.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide the process integration side of a silicon hole
Case, for solving the problem of through-silicon via sidewall multi-layer film structure in the prior art is layered with copper surface gap after CMP and depression.
In order to achieve the above objects and other related objects, the present invention provides copper table after a kind of solution silicon hole layering and CMP
The method of face depression problem, at least comprises the following steps：
1) silicon hole is formed in the silicon substrate that surface has stop-layer, in the silicon hole and surface of silicon deposition two
Silica deposits barrier layer and Seed Layer as separation layer in the silica insulation surface；
2) in the Seed Layer electroplating surface copper, the copper at least filling up the silicon hole is formed；
3) said structure is made annealing treatment, including：
80~200 DEG C 3-1) are warming up to 0.5~5 DEG C/min, 0~60min is incubated；
250~450 DEG C 3-2) are warming up to 1~10 DEG C/min, 15~180min is incubated；
3-3) 25~100 DEG C are cooled to 1~5 DEG C/min；
4) it is polished using CMP, until exposing the stop-layer.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Step 3-2) 250~300 DEG C are warming up to 1~10 DEG C/min, it is incubated 15~180min.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Step 3-3) it is cooled to more than 30 DEG C, step 3) also include step 3-4) to be down to 15~30 DEG C less than 10 DEG C/min.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Step 1) silica separation layer also includes the step toasted to two surfaces of the silicon substrate or single surface after being formed
Suddenly.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
The time of baking is 0~20min.When the foundation of selection baking time length is that silica exposure is aerial after depositing
Between.If standing time is long, need to increase the time toasted, to remove the steam wherein adsorbed.
Further, toasted if silica is just deposited, the time is 0~3min.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Toasted from the back side of the silicon substrate, the temperature of surface of silicon is 300~400 DEG C.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Baking is irradiated from the front of the silicon substrate, the temperature of surface of silicon is 150~250 DEG C.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
The material of the stop-layer is silicon nitride.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
The barrier layer for Ta/TaN laminations.
As a kind of preferred scheme for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention,
Step 4) comprise the following steps：4-1) copper is polished until exposing the barrier layer；Throwing 4-2) was carried out to copper；4-3) throw
Light exposes the stop-layer to remove the barrier layer and silica separation layer.
As described above, the present invention provides a kind of method for solving the problems, such as copper surface indentation after silicon hole layering and CMP, including
Step：1) silicon hole is formed in the silicon substrate that surface has stop-layer, in the silicon hole and surface of silicon deposition dioxy
SiClx separation layer, in silica insulation surface formation barrier layer and Seed Layer；2) in the Seed Layer electroplating surface
Copper, forms the copper at least filling up the silicon hole；3) said structure is made annealing treatment, including：3-1) with 0.5~5 DEG C/
Min is warming up to 80~200 DEG C, is incubated 0~60min；3-2) 250~450 DEG C are warming up to 1~10 DEG C/min, insulation 15~
180min；3-3) 25~100 DEG C are cooled to 1~5 DEG C/min；4) it is polished using CMP, until exposing the stop-layer.
The present invention effectively solves point in silicon hole technique by improving the baking process to silicon substrate and the annealing process to copper
Copper surface indentation problem after layer phenomenon and CMP, method and step is simple, does not increase process costs, it is adaptable to industrial production.
Brief description of the drawings
Fig. 1 is shown as structural representation of the silicon hole integrated process after electro-coppering in the prior art, and its surface has convex
The pattern for rising and being recessed.
Fig. 2 is shown as the structural representation of silicon hole integrated process after cmp in the prior art, in the range of total silicon piece,
Copper and barrier layer close to silicon hole top edge are separated, and breach is presented.Serious even can form ring-type breach.In silicon chip
There is copper and is integrally recessed in the silicon hole at edge.
Fig. 3 is shown as the temperature-time curve figure that existing silicon hole integrated process is annealed to electro-coppering.
Fig. 4 is shown as the flow signal for solving the problems, such as the method for copper surface indentation after silicon hole layering and CMP of the present invention
Figure.
Fig. 5 is shown as the method for solving the problems, such as copper surface indentation after silicon hole layering and CMP of the present invention after the copper plating
Annealing process schematic diagram.
Fig. 6 is shown as the method for solving the problems, such as copper surface indentation after silicon hole layering and CMP of the present invention after the copper plating
The temperature-time curve figure of annealing.
Component label instructions
S11~S14 steps 1)~step 4)
S131~S134 step 3-1)~step 3-4)
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 4~Fig. 6.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 4~Fig. 6, the present embodiment offer is a kind of to solve the problems, such as copper surface indentation after silicon hole layering and CMP
Method, the problem of solving copper surface indentation after silicon hole layering and CMP in the prior art for solution.
In order to achieve the above objects and other related objects, the present invention provides copper table after a kind of solution silicon hole layering and CMP
The method of face depression problem, at least comprises the following steps：
As shown in figure 4, carrying out step 1 first) S11, silicon hole is formed in the silicon substrate that surface has stop-layer, in institute
Silicon hole and surface of silicon deposition silica separation layer are stated, in silica insulation surface formation barrier layer and kind
Sublayer.
As example, also there is oxide layer between shown silicon substrate and the stop-layer.
As example, using chemical vapour deposition technique in the silicon hole and surface of silicon deposition silica isolation
Layer.
As example, silica separation layer also includes entering two surfaces of the silicon substrate or single surface after being formed
The step of row baking.
As example, the time of baking is 0~20min.The foundation of selection baking time length is titanium dioxide after deposition
Silicon exposes the aerial time.If standing time is long, need to increase the time toasted, to remove the water wherein adsorbed
Vapour.
Preferably, the time of baking is 0~3min.
As example, toasted from the back side of the silicon substrate, the temperature of surface of silicon is 300~400 DEG C.
As example, baking is irradiated from the front of the silicon substrate, the temperature of surface of silicon is 150~250 DEG C.
The roasting mode of contact is used due to being toasted to the silicon substrate back side, and front baking is then non-using making
The irradiation roasting mode of contact, therefore, relatively long to the time of front baking, the time of back side baking is then relatively short,
Better effect can be obtained.In a specific implementation process, to silicon substrate front baking 5min, the back side is dried
It is roasting 1 minute.
Certainly, in other implementation processes, it can be toasted using other roasting modes, however it is not limited to this place
That enumerates is several.
As example, the material of the stop-layer is silicon nitride.The stop-layer stops as subsequent CMP process polishing process
Signals layer only, in case device is by excessive polishing.Certainly, the material of the stop-layer can be selected according to process requirements,
It is not limited to one kind recited herein.
As example, the barrier layer for Ta/TaN laminations.The barrier layer can prevent copper in subsequent technique from
Son enters in silicon substrate, it is to avoid stability and performance during influence.Certainly, the material on the barrier layer can be according to technique need
Ask and selected, however it is not limited to one kind recited herein.
The present embodiment carries out the baking of short period to the silicon substrate, gets rid of the steam adsorbed in silicon dioxide layer,
The bonding between silicon dioxide layer and trapping layer is enhanced, so as to largely eliminate the lamination between this two layers.
But excessive baking can then bring opposite effect.
As shown in figure 4, then carrying out step 2) S12, in the Seed Layer electroplating surface copper, the silicon is at least filled up in formation
The copper of through hole.
As example, electroplated by electroplating technology in the silicon hole and surface of silicon, until being fully filled with institute
Silicon substrate is stated, now, the surface of silicon can also form one layer of copper, and due to the presence of silicon hole, in silicon hole correspondence
Region on, the projection and depression of copper can be formed.
As shown in Fig. 4~Fig. 6, step 3 is then carried out) S13, said structure is made annealing treatment, including：
As shown in figures 5 and 6,3-1 is carried out first) S131, A-B stages and B-C stages, it is warming up to 0.5~5 DEG C/min
80~200 DEG C, it is incubated 0~60min.In the present embodiment, using 1 DEG C/min from room temperature to 150 DEG C, it is incubated 15min.
As shown in figures 5 and 6,3-2 is then carried out) S132, C-D stages and D-E stages, it is warming up to 1~10 DEG C/min
250~450 DEG C, it is incubated 15~180min.
As example, 250~300 DEG C are warming up to 1~10 DEG C/min, 15~180min is incubated.In the present embodiment, with
3 DEG C/min is warming up to 300 DEG C, is incubated 30min.
As shown in figures 5 and 6,3-3 is then carried out) S133, in the E-F stages, 25~100 DEG C are cooled to 1~5 DEG C/min.
In the present embodiment, 100 DEG C are cooled to natural cooling.
As shown in figures 5 and 6, if step 3-3) more than 30 DEG C are cooled to, proceed 3-4) and S134, the F-G stages, with
15~30 DEG C are down to less than 10 DEG C/min, in the present embodiment, 20 DEG C is cooled to from 100 DEG C with 3 DEG C/min, that is, is down to room temperature.
Of course, it is possible in 3-3) in directly cool the temperature to room temperature, such as 25 DEG C, then can omit 3-4), save program.
After the annealing process by above-mentioned electro-coppering, the stress of electro-coppering has obtained more preferable release, silicon substrate it is curved
Curvature is half as large compared with what existing copper annealing process was obtained.Even if protrusion of surface and the larger situation of being recessed after the copper plating
Under, it can also obtain after cmp than smoother surface, so as to substantially reduce demand during electro-coppering to craft precision, drop
Low cost.The silicon hole surface at most silicon substrate centers is without breach.And the silicon hole of silicon chip edge is integrally recessed
Fall into, also obtained great alleviation.
After the above-mentioned annealing process to electro-coppering, copper hardness reduces, the removal rate of copper when causing CMP copper
(Remove Rate) adds 30% or so, therefore, the CMP processing procedures of copper is also required to be adjusted, such as the polishing velocity of copper
Can accordingly it reduce, crossing time consuming can also accordingly be reduced.Again because adding the above-mentioned baking process to silicon dioxide layer, silicon
The local stress of piece entirety and silicon hole is all changed, and the adjustment to technological parameter is also required to consider these factors.As showing
Example, this step include it is following step by step：4-1) polishing copper is employing the copper lehr attendant of this programme up to exposing the barrier layer
After skill, polishing dynamics reduces 30% compared with using the copper polishing dynamics after existing copper annealing process；Throwing 4-2) was carried out to copper,
The throwing time is spent compared with using the time reduction 30% after existing copper annealing process；4-3) polish to remove the barrier layer and two
Silica separation layer, exposes the stop-layer.After the copper method for annealing of invention is employed, by this polishing method, it can obtain
Obtain surfacing, the through-silicon via structure surface not being recessed substantially.
As shown in figure 4, finally carrying out step 4) S14, it is polished using CMP, until exposing the stop-layer.
Certainly, for general silicon hole technique, also including step 5), stop-layer is removed using wet etching method and exposed
Contact, and continue last part technology.
In summary, the present invention provides a kind of method for solving the problems, such as copper surface indentation after silicon hole layering and CMP, including
Step：1) silicon hole is formed in the silicon substrate that surface has stop-layer, in the silicon hole and surface of silicon deposition dioxy
SiClx separation layer, in silica insulation surface formation barrier layer and Seed Layer；2) in the Seed Layer electroplating surface
Copper, forms the copper at least filling up the silicon hole；3) said structure is made annealing treatment, including：3-1) with 0.5~5 DEG C/
Min is warming up to 80~200 DEG C, is incubated 0~60min；3-2) 250~450 DEG C are warming up to 1~10 DEG C/min, insulation 15~
180min；3-3) 25~100 DEG C are cooled to 1~5 DEG C/min；4) it is polished using CMP, until exposing the stop-layer.
5) stop-layer is etched away to expose Contact and continue last part technology.The present invention is by improving to the baking process of silicon substrate and right
The annealing process of copper, efficiently solves the problems, such as copper surface indentation after the lamination and CMP in silicon hole technique, method and step letter
It is single, do not increase process costs, it is adaptable to industrial production.So, the present invention effectively overcome various shortcoming of the prior art and
Has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of method for solving the problems, such as copper surface indentation after silicon hole layering and CMP, it is characterised in that at least including following step
Suddenly：
1) silicon hole is formed in the silicon substrate that surface has stop-layer, in the silicon hole and surface of silicon deposition titanium dioxide
Silicon separation layer, in silica insulation surface formation barrier layer and Seed Layer；
2) in the Seed Layer electroplating surface copper, the copper at least filling up the silicon hole is formed；
3) said structure is made annealing treatment, including：
80~200 DEG C 3-1) are warming up to 0.5~5 DEG C/min, 0~60min is incubated；
250~300 DEG C 3-2) are warming up to 1~10 DEG C/min, 15~180min is incubated；
3-3) 25~100 DEG C are cooled to 1~5 DEG C/min；
4) it is polished using CMP, until exposing the stop-layer.
5) stop-layer is etched away, exposes Contact, and continue last part technology.
2. the method according to claim 1 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：Step 3-3) if cooling stops at more than 30 DEG C, step 3) also include step 3-4) to be down to 15~30 less than 10 DEG C/min
℃。
3. the method according to claim 1 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：Step 1) silica separation layer also includes toasting two surfaces of the silicon substrate or single surface after being formed
Step.
4. the method according to claim 3 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：The time of baking is 0~20min.
5. the method according to claim 4 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：The time of baking is 0~3min.
6. the method according to claim 3 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：The temperature toasted from the back side of the silicon substrate is 300~400 DEG C.
7. the method according to claim 3 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：Baking is irradiated from the front of the silicon substrate, the temperature of surface of silicon is 150~250 DEG C.
8. the method according to claim 1 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：The material of the stop-layer is silicon nitride.
9. the method according to claim 1 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：The barrier layer for Ta/TaN laminations.
10. the method according to claim 1 for solving the problems, such as copper surface indentation after silicon hole layering and CMP, its feature exists
In：Step 4) comprise the following steps：
4-1) copper is polished until exposing the barrier layer；
Throwing 4-2) was carried out to copper；
4-3) polishing exposes the stop-layer to remove the barrier layer and silica separation layer.
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