CN104112471A - Memory device and method for reading data from same - Google Patents
Memory device and method for reading data from same Download PDFInfo
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- CN104112471A CN104112471A CN201310133839.8A CN201310133839A CN104112471A CN 104112471 A CN104112471 A CN 104112471A CN 201310133839 A CN201310133839 A CN 201310133839A CN 104112471 A CN104112471 A CN 104112471A
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Abstract
The invention provides a memory device and a method for reading data from the same. The method includes following steps: providing a first memory unit array which includes a plurality of first character lines, wherein first data is stored in the first memory unit array; providing a second memory unit array which includes a plurality of second character lines, wherein the second memory unit array is separated from the first memory unit array and second data is stored in the second memory unit array; selecting one from the first character lines and one from the second character lines in a same time or an overlapped time, interlacedly selecting a first address from the first memory unit array and a second address from the second memory unit array, thereby interlacedly reading a first corresponding part of the first data from the first memory unit array and a second corresponding part of the second data from the second memory unit array. A problem that a reading speed of a conventional memory device is limited is solved.
Description
Technical field
The invention relates to a kind of storage arrangement, particularly about thering is the storage arrangement of high speed read functions and the method by reading out data in storage arrangement.
Background technology
Fig. 1 is the schematic diagram that shows a traditional storage arrangement 100.Storage arrangement 100 comprises a memory cell array 110 and a sensing amplifier 160.Many data for example: bit group (byte) is also called byte 0-7, are to be stored in memory cell array 110.Memory cell array 110 comprises that many character lines (word lines) 111,112 and multiple bit lines are to select the address (address) of data.In an external device (ED) is wanted by memory cell array 110, when reading out data, in a sense period, only can select a character line, otherwise will make a mistake.For example, if character line 111,112 is selected at one time, cannot to differentiate reading out data be from bit group 0 or bit group 4 to sensing amplifier 160.Therefore, the reading speed of legacy memory devices 100 will be restricted.
Summary of the invention
The object of this invention is to provide a kind of storage arrangement of reading speed restriction and the method by reading out data in storage arrangement, problem being restricted to solve the reading speed of legacy memory devices of not being subject to.
For addressing the above problem, the invention provides a kind of storage arrangement and comprise: one first memory cell array, comprise multiple the first character lines and multiple the first bit line, wherein many first data are to be stored in this first memory cell array; One second memory cell array, separates with this first memory cell array, and comprises multiple the second character lines and multiple the second bit line, and wherein many second data are to be stored in this second memory cell array; One control logic circuit, allow in a same time or in an overlapping time, select the one of the plurality of the first character line and the one of the plurality of the second character line, and select alternately one first address of this first memory cell array and one second address of this second memory cell array, to read alternately one first corresponding part of these many first data and one second corresponding part of these many second data from this first memory cell array and this second memory cell array; One first sensing amplifier, is coupled to this first memory cell array via the plurality of the first bit line, and amplifies this first corresponding part of these many first data; And one second sensing amplifier, be coupled to this second memory cell array via the plurality of the second bit line, and amplify this second corresponding part of these many second data.
In addition, the invention provides a kind of method by reading out data in a storage arrangement, comprise the following steps: to provide one first memory cell array, wherein this first memory cell array comprises multiple the first character lines and multiple the first bit line, and many first data are to be stored in this first memory cell array; One second memory cell array is provided, wherein this second memory cell array comprises multiple the second character lines and multiple the second bit line, this second memory cell array separates with this first memory cell array, and many second data are to be stored in this second memory cell array; In a same time or select the one of the plurality of the first character line and the one of the plurality of the second character line in an overlapping time; Select alternately one first address of this first memory cell array and one second address of this second memory cell array, to read alternately one first corresponding part of these many first data and one second corresponding part of these many second data from this first memory cell array and this second memory cell array; And amplify this first corresponding part of these many first data and this second corresponding part of these many second data.
Useful technique effect of the present invention is: by the present invention, can make the reading speed of legacy memory devices be significantly improved, in the problem being restricted, provide reading speed faster in the reading speed that solves its legacy memory devices.
Brief description of the drawings
Fig. 1 is the schematic diagram that shows traditional storage arrangement;
Fig. 2 shows according to the schematic diagram of the storage arrangement described in one embodiment of the invention;
Fig. 3 A shows according to the schematic diagram of the first memory cell array described in one embodiment of the invention and the second memory cell array;
Fig. 3 B shows according to the schematic diagram of the first memory cell array described in another embodiment of the present invention and the second memory cell array;
Fig. 4 A shows according to the signal waveforms of the storage arrangement described in one embodiment of the invention;
Fig. 4 B shows according to the signal waveforms of the storage arrangement described in another embodiment of the present invention;
Fig. 5 shows according to the process flow diagram of the method by reading out data in storage arrangement described in one embodiment of the invention;
Fig. 6 A shows according to the schematic diagram of the first memory cell array described in one embodiment of the invention and the second memory cell array; And
Fig. 6 B shows according to the schematic diagram of the first memory cell array described in another embodiment of the present invention and the second memory cell array.
Reference numeral
100,200～storage arrangement;
110,210,220～memory cell array;
111,112,211,212,221,222～character line;
160,260,270～sensing amplifier;
215,216,225,226～bit line;
250～control logic circuit;
280～multiplexing data device;
290～displacement working storage;
CLK～clock pulse signal;
The corresponding part of S1, S2～data;
SA1, SA2,410-1,410-2 ..., 410-7～address;
SE1, SE2～sense enable signal;
SIN～input signal;
SOUT～output data;
T1, T2～sensing time.
Embodiment
Fig. 2 shows according to the schematic diagram of the storage arrangement 200 described in one embodiment of the invention.Storage arrangement 200 can be a NOR flash memory, but is not limited to this.As shown in Figure 2, storage arrangement 200 comprises: one first memory cell array 210, one second memory cell array 220, a control logic circuit 250, one first sensing amplifier 260, one second sensing amplifier 270, a multiplexing data device 280, and a displacement working storage 290.
The first memory cell array 210 is to separate with the second memory cell array 220.Many the first data (for example: bit group) are to be stored in the first memory cell array 210, and many second data (for example: bit group) are to be stored in the second memory cell array 220.These many first data and these many second data be combined as complete continuous data.But, in certain embodiments, be stored in the first memory cell array these many first data of 210 and these many second data that are stored in the second memory cell array 220 and be all discrete date.The first memory cell array 210 comprises many first character lines 211,212 and many first bit lines 215,216.The first sensing amplifier 260 is to be coupled to the first memory cell array 210 via the plurality of the first bit line.The second memory cell array 220 also comprises many second character lines 221,222 and many second bit lines 225,226.The second sensing amplifier 270 is to be coupled to the second memory cell array 220 via the plurality of the second bit line.Read in process one, aforesaid character line and bit line are the address for selecting arbitrary memory cell array.In order to simplify accompanying drawing, be not that all character lines and bit line are all shown in Fig. 2.It must be understood that, in the present embodiment, each memory cell array all can comprise more multiword unit's line and bit line.
Control logic circuit 250 is for reading these many first data from the first memory cell array 210, and reads these many second data from the second memory cell array 220.In certain embodiments, control logic circuit 250 receives an input signal SIN, and it indicates an initial address of arbitrary memory cell array, and control logic circuit 250 starts to carry out a fetch program from this initial address again.During this fetch program, control logic circuit 250 can allow in a same time or in an overlapping time, select the one of the plurality of the first character line and the one of the plurality of the second character line.For instance, the first character line 211 of the first memory cell array 210 and the second character line 221 of the second memory cell array 220 can be selected in the same time.Because the first memory cell array 210 is to separate with the second memory cell array 220, the selection of a first character line is separate with the selection of another the second character line, and sensing amplifier 260,270 can be differentiated reading out data without obscuring.In preferred embodiment, control logic circuit 250 is to select alternately one first address SA1 of the first memory cell array 210 and one second address SA2 of the second memory cell array 220, to read alternately one first corresponding part S1 of these many first data and one second corresponding part S2 of these many second data from the first memory cell array 210 and the second memory cell array 220.Must be noted that each corresponding part all can comprise one or many data.Next, the first sensing amplifier 260 amplifies the first corresponding part S1 having read, and the second sensing amplifier 270 amplifies the second corresponding part S2 having read.Multiplexing data device 280 is to be coupled to the first sensing amplifier 260 and the second sensing amplifier 270.Multiplexing data device 280 is optionally to transmit the first corresponding part S1 of amplification and the second corresponding part S2 of amplification to displacement working storage 290.Displacement working storage 290 produces many output data SOUT in order according to the first corresponding part S1 and the second corresponding part S2 again.
In more detail, control logic circuit 250 more receives a clock pulse signal CLK.After control logic circuit 250 receives the input signal SIN of this initial address of instruction, control logic circuit 250 transmits sense enable signal SE1, SE2 to start this fetch program.The detailed operating process of storage arrangement 200 will explain in the following example.
Fig. 3 A shows according to the first memory cell array 210 described in one embodiment of the invention and the schematic diagram of the second memory cell array 220.As shown in Figure 3A, these many first data that are stored in the first memory cell array 210 comprise discontinuous bit group 0,2,4,6, and these many second data that are stored in the second memory cell array 220 comprise discontinuous bit group 1,3,5,7.Each tuple all can be considered data.The combination of these many first data and these many second data can form partial data, and it comprises continuous bit group 0 to 7.In order to simplify accompanying drawing, Fig. 3 A does not show all bit groups, but it must be understood that, each memory cell array all can store more multidigit tuple.
Fig. 4 A shows according to the signal waveforms of the storage arrangement 200 described in one embodiment of the invention.Please also refer to Fig. 2, Fig. 3 A, and Fig. 4 A.If received after input signal SIN, producing before output data SOUT, must first expend several empty cycles (Dummy Cycles) with one fetch program of initialization.Address 410-0 to 410-7 (not showing whole address) in Fig. 4 A is the bit group 0 to 7 corresponding to respectively in Fig. 3 A.As shown in Figure 4 A, during this fetch program, control logic circuit 250 be select alternately the first memory cell array 210 the first address SA1 (for example: address 410-0, 410-2, 410-4, the one of 410-6) and the second address SA2 of the second memory cell array 220 is (for example: address 410-1, 410-3, 410-5, the one of 410-7), with the first corresponding part S1 of reading alternately these many first data from the first memory cell array 210 and the second memory cell array 220 (for example: bit group 0, 2, 4, 6 one) and the second corresponding part S2 of these many second data is (for example: bit group 1, 3, 5, 7 one).Even if it is discontinuous that these many first data that store and these many second data of storage are all, but output data SOUT can be complete and continuous data.In the present embodiment, for example, in the time that the first address SA1 (: address 410-2) is selected, the data bulk of the first corresponding part S1 (for example: bit group 2) reading is 1, for example, for example, and in the time that the second address SA2 (: address 410-3) is selected, the data bulk of the second corresponding part S2 (: bit group 3) reading is also 1.For instance, in Fig. 3 A, if select the first character line 211, the one of these many first data (for example: bit group 2) will be read; And if select the second character line 221, the one of these many second data (for example: bit group 3) will be read, wherein the first character line 211 and the second character line 221 can in a same time or in the overlapping time be selected.In the present embodiment, the first address SA1 and the second address SA2 are all every through increasing by 2 two clock cycles.One sensing time T 1 is for example, for reading the first corresponding part S1 (: bit group 2) or for example, for reading the second corresponding part S2 (: bit group 3), during initialization procedure, the maximal value of sensing time T 1 is two clock cycles.In comparison, the maximal value of a sensing time of the legacy memory devices 100 shown in Fig. 1 is a clock cycle.Therefore, the 2nd, the embodiment shown in 3A, 4A figure can provide reading speed faster, it is about the twice of traditional reading speed.
Fig. 3 B shows according to the first memory cell array 210 described in another embodiment of the present invention and the schematic diagram of the second memory cell array 220.As shown in Figure 3 B, these many first data that are stored in the first memory cell array 210 comprise discontinuous bit group 0,1,4,5, and these many second data that are stored in the second memory cell array 220 comprise discontinuous bit group 2,3,6,7.Each tuple all can be considered data.The combination of these many first data and these many second data can form partial data, and it comprises continuous bit group 0 to 7.In order to simplify accompanying drawing, Fig. 3 B does not show all bit groups, but it must be understood that, each memory cell array all can store more multidigit tuple.Fig. 3 B is similar to Fig. 3 A, and both difference is, in Fig. 3 B, the bit group (for example: bit group 0,1) of wantonly two vicinities that each memory cell array stores can be continuous data.This design can be accelerated the reading speed of storage arrangement 200 further.
Fig. 4 B shows according to the signal waveforms of the storage arrangement 200 described in another embodiment of the present invention.Please also refer to Fig. 2, Fig. 3 B, and Fig. 4 B.If received after input signal SIN, producing before output data SOUT, must first expend several empty cycles with one fetch program of initialization.Address 410-0 to 410-7 (not showing whole address) in Fig. 4 B is the bit group 0 to 7 corresponding to respectively in Fig. 3 B.As shown in Figure 4 B, during this fetch program, control logic circuit 250 be select alternately the first memory cell array 210 the first address SA1 (for example: address 410-0, the one of 410-4) and the second address SA2 of the second memory cell array 220 is (for example: address 410-2, the one of 410-6), with the first corresponding part S1 of reading alternately these many first data from the first memory cell array 210 and the second memory cell array 220 (for example: bit group 0, 1, or bit group 4, 5) and the second corresponding part S2 of these many second data (for example: bit group 2, 3, or bit group 6, 7).Even if it is discontinuous that these many first data that store and these many second data of storage are all, but output data SOUT can be complete and continuous data.In the present embodiment, for example, in the time that the first address SA1 (: address 410-4) is selected, the data bulk of the first corresponding part S1 (for example: bit group 4,5) reading is 2, for example, for example, and in the time that the second address SA2 (: address 410-6) is selected, the data bulk of the second corresponding part S2 (: bit group 6,7) reading is also 2.For instance, in Fig. 3 B, if select the first character line 212, these many first data continuous the two (for example: bit group 4,5) will be read together; And if select the second character line 222, these many second data continuous the two (for example: bit group 6,7) will be read together, wherein the first character line 212 and the second character line 222 can be in same times or selected in the overlapping time.In the present embodiment, the first address SA1 and the second address SA2 are all every through increasing by 4 four clock cycles.One sensing time T 2 is for example, for reading the first corresponding part S1 (: bit group 4,5) or for example, for reading the second corresponding part S2 (: bit group 6,7), during initialization procedure, the maximal value of sensing time T 2 is four clock cycles.In comparison, the maximal value of a sensing time of the legacy memory devices 100 shown in Fig. 1 is a clock cycle.Therefore, the embodiment shown in Fig. 2, Fig. 3 B, Fig. 4 B can provide reading speed faster, and it is about four times of traditional reading speed.
Fig. 5 shows according to the process flow diagram by the method for reading out data in a storage arrangement described in one embodiment of the invention.First, at step S510, provide one first memory cell array, wherein this first memory cell array comprises multiple the first character lines and multiple the first bit line, and many first data are to be stored in this first memory cell array.At step S520, one second memory cell array is provided, wherein this second memory cell array comprises multiple the second character lines and multiple the second bit line, and this second memory cell array separates with this first memory cell array, and many second data are to be stored in this second memory cell array.At step S530, in a same time or select the one of the plurality of the first character line and the one of the plurality of the second character line in an overlapping time.At step S540, select alternately one first address of this first memory cell array and one second address of this second memory cell array, to read alternately one first corresponding part of these many first data and one second corresponding part of these many second data from this first memory cell array and this second memory cell array.Finally, at step S550, amplify this first corresponding part of these many first data and this second corresponding part of these many second data.It should be noted that the order execution all successively of above method step.Fig. 2, Fig. 3 A, Fig. 3 B, Fig. 4 A, the embodiment that Fig. 4 B is relevant, its all detail characteristics all can be applied mechanically to the method shown in Fig. 5.
Although the above, in each memory cell array, each character line only corresponds to two bit groups, and the present invention is not limited to this.Fig. 6 A shows according to the first memory cell array 210 described in one embodiment of the invention and the schematic diagram of the second memory cell array 220.As shown in Figure 6A, in each memory cell array, each character line can correspond to four bit groups, and the design of Fig. 6 A can produce similar signal waveform to the embodiment of Fig. 4 A.Fig. 6 B shows according to the first memory cell array 210 described in another embodiment of the present invention and the schematic diagram of the second memory cell array 220.As shown in Figure 6B, in each memory cell array, each character line can correspond to four bit groups, and the design of Fig. 6 B can produce similar signal waveform to the embodiment of Fig. 4 B.It should be noted that the present invention more can apply mechanically to various various memory cell arrays, for example, its each character line corresponds to 2,4,8,16,32,64,128,256, the memory cell array of even more bit groups.
Ordinal number in this instructions and claim, for example " first ", " second ", " 3rd " etc., each other between the precedence relationship in order not, it only distinguishes two different elements with same name for indicating.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit scope of the present invention, any relevant technical staff in the field, do not departing from claim of the present invention, when doing a little change and retouching, therefore claim of the present invention is when defining and be as the criterion depending on above-mentioned claims.
Claims (20)
1. a storage arrangement, is characterized in that, described storage arrangement comprises:
One first memory cell array, comprises multiple the first character lines and multiple the first bit line, and wherein many first data are to be stored in described the first memory cell array;
One second memory cell array, separates with described the first memory cell array, and comprises multiple the second character lines and multiple the second bit line, and wherein many second data are to be stored in described the second memory cell array;
One control logic circuit, allow in a same time or in an overlapping time, select the one of described multiple the first character lines and the one of described multiple the second character lines, and select alternately one first address of described the first memory cell array and one second address of described the second memory cell array, to read alternately one first corresponding part of described many first data and one second corresponding part of described many second data from described the first memory cell array and described the second memory cell array;
One first sensing amplifier, is coupled to described the first memory cell array via described multiple the first bit lines, and amplifies the described first corresponding part of described many first data; And
One second sensing amplifier, is coupled to described the second memory cell array via described multiple the second bit lines, and amplifies the described second corresponding part of described many second data.
2. storage arrangement according to claim 1, is characterized in that, described storage arrangement also comprises:
One multiplexing data device; And
One displacement working storage, wherein said multiplexing data device is to be coupled to described the first sensing amplifier and described the second sensing amplifier, described multiplexing data device optionally transmits the described first corresponding part and extremely described displacement working storage of the described second corresponding part, and described displacement working storage is to produce in order multiple output data according to the described first corresponding part and the described second corresponding part.
3. storage arrangement according to claim 1, is characterized in that, described the first address and described the second address are all every through increasing by 2 two clock cycles.
4. storage arrangement according to claim 1, is characterized in that, the described sensing time is for reading described the first corresponding part or for reading the described second corresponding part, and the maximal value of described sensing time is two clock cycles.
5. storage arrangement according to claim 1, it is characterized in that, in the time that described the first address is selected, the data bulk of the described first corresponding part reading is 1, and in the time that described the second address is selected, the data bulk of the described second corresponding part reading is 1.
6. storage arrangement according to claim 1, is characterized in that, described the first address and described the second address are all every through increasing by 4 four clock cycles.
7. storage arrangement according to claim 1, is characterized in that, the described sensing time is for reading described the first corresponding part or for reading the described second corresponding part, and the maximal value of described sensing time is four clock cycles.
8. storage arrangement according to claim 1, it is characterized in that, in the time that described the first address is selected, the data bulk of the described first corresponding part reading is 2, and in the time that described the second address is selected, the data bulk of the described second corresponding part reading is 2.
9. storage arrangement according to claim 1, is characterized in that, is stored in described many first data in described the first memory cell array and described many second data of being stored in described the second memory cell array are all discrete date.
10. storage arrangement according to claim 1, is characterized in that, described many first data and described many second data be combined as complete continuous data.
11. 1 kinds of methods by reading out data in a storage arrangement, is characterized in that, the method for described reading out data comprises the following steps:
One first memory cell array is provided, and wherein said the first memory cell array comprises multiple the first character lines and multiple the first bit line, and many first data are to be stored in described the first memory cell array;
One second memory cell array is provided, wherein said the second memory cell array comprises multiple the second character lines and multiple the second bit line, described the second memory cell array separates with described the first memory cell array, and many second data are to be stored in described the second memory cell array;
In a same time or select the one of described multiple the first character lines and the one of described multiple the second character lines in an overlapping time;
Select alternately one first address of described the first memory cell array and one second address of described the second memory cell array, to read alternately one first corresponding part of described many first data and one second corresponding part of described many second data from described the first memory cell array and described the second memory cell array; And
Amplify the described first corresponding part of described many first data and the described second corresponding part of described many second data.
12. methods by reading out data in a storage arrangement according to claim 11, is characterized in that, the method for described reading out data also comprises:
By a multiplexing data device, optionally transmit the described first corresponding part of described many first data and the described second corresponding part of described many second data to a displacement working storage; And
By described displacement working storage, produce in order multiple output data according to the described first corresponding part and the described second corresponding part.
13. methods by reading out data in a storage arrangement according to claim 11, is characterized in that, described the first address and described the second address are all every through increasing by 2 two clock cycles.
14. methods by reading out data in a storage arrangement according to claim 11, it is characterized in that, one sensing time was for reading described the first corresponding part or for reading the described second corresponding part, and the maximal value of described sensing time is two clock cycles.
15. methods by reading out data in a storage arrangement according to claim 11, it is characterized in that, in the time that described the first address is selected, the data bulk of the described first corresponding part reading is 1, and in the time that described the second address is selected, the data bulk of the described second corresponding part reading is 1.
16. methods by reading out data in a storage arrangement according to claim 11, is characterized in that, described the first address and described the second address are all every through increasing by 4 four clock cycles.
17. methods by reading out data in a storage arrangement according to claim 11, it is characterized in that, one sensing time was for reading described the first corresponding part or for reading the described second corresponding part, and the maximal value of described sensing time is four clock cycles.
18. methods by reading out data in a storage arrangement according to claim 11, it is characterized in that, in the time that described the first address is selected, the data bulk of the described first corresponding part reading is 2, and in the time that described the second address is selected, the data bulk of the described second corresponding part reading is 2.
19. methods by reading out data in a storage arrangement according to claim 11, it is characterized in that, be stored in described many first data in described the first memory cell array and described many second data of being stored in described the second memory cell array are all discrete date.
20. methods by reading out data in a storage arrangement according to claim 11, is characterized in that, described many first data and described many second data be combined as complete continuous data.
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| US20010044875A1 (en) * | 1996-01-11 | 2001-11-22 | Jeffrey S. Mailloux | Method for switching between modes of operation |
| CN1471708A (en) * | 2000-10-27 | 2004-01-28 | 汤姆森许可贸易公司 | Method and apparatus for preliminarily erasing parts of a bit stream recorded on a storage medium |
| CN101911208A (en) * | 2008-01-22 | 2010-12-08 | 莫塞德技术公司 | Nand flash memory access with relaxed timing constraints |
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2013
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010044875A1 (en) * | 1996-01-11 | 2001-11-22 | Jeffrey S. Mailloux | Method for switching between modes of operation |
| CN1471708A (en) * | 2000-10-27 | 2004-01-28 | 汤姆森许可贸易公司 | Method and apparatus for preliminarily erasing parts of a bit stream recorded on a storage medium |
| CN101911208A (en) * | 2008-01-22 | 2010-12-08 | 莫塞德技术公司 | Nand flash memory access with relaxed timing constraints |
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