CN104103639B - NAND Flash storage unit, operating method and read method - Google Patents
NAND Flash storage unit, operating method and read method Download PDFInfo
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Abstract
The present invention provides a kind of NAND Flash storage unit, operating method and read method.This NAND Flash storage unit includes multiple grid layers, a channel layer, an electric charge capture layer, a conductor layer and one second dielectric layer.Include one first dielectric layer in these grid layers between two adjacent grid layers.Channel layer, electric charge capture layer, conductor layer and the second dielectric layer can run through these grid layers.Electric charge capture layer is disposed between channel layer and grid layer, and the second dielectric layer is disposed between conductor layer and channel layer.Therefore, speed of erasing can be elevated, and electric charge capture layer can be repaired, and the control ability of grid layer can be lifted.
Description
Technical field
The invention relates to a kind of flash memory cell, and in particular to a kind of NAND Flash storage unit, behaviour
Make method and read method.
Background technology
NAND structures are widely used in the design of nonvolatile memory device, to increase storage density.One NAND
Flash memory cell generally includes the multiple storage units being serially connected.With the micro of processing procedure, stored in NAND Flash
On can face many difficult and cause data reliability to reduce.It is single to propose many three-dimensional NAND Flash storages for industry in recent years
Member, is, for example, million cellular array transistors (Terabit Cell array to attempt to solve microtechnology problem often encountered
Transistor, TCAT), push away repeatedly memory array rowed transistor (Stacked Memory Array Transistor, SMArT)
Or extendible (Bit Cost Scalable, the BiCS) technology of bit cost.In some three dimensional NAND flash memory cells, it is
Data are stored with silicon nitride, but the data preservation (data retention) of this storage unit can not be simultaneous with speed of erasing
, once to increase speed of erasing, then data are preserved and will be deteriorated.Therefore, the speed of erasing of flash memory cell how is taken into account
Preserved with data, for this field technology personnel subject under discussion of concern.
The content of the invention
The present invention provides a kind of NAND Flash storage unit, corresponding operating method and read method, can be lifted and smeared
The speed of division operation, repairs electric charge capture layer, and increases the control ability of grid layer.
One example of the present invention embodiment proposes a kind of NAND Flash storage unit, including multiple grid layers, channel layer, electricity
Lotus trapping layer, conductor layer and the second dielectric layer.Include first dielectric layer between two wherein adjacent grid layers.Passage
Layer, electric charge capture layer, conductor layer and the second dielectric layer can run through the grid layer.Electric charge capture layer is disposed on channel layer and institute
Between stating grid layer, and the second dielectric layer is disposed between conductor layer and channel layer.
In an exemplary embodiment, above-mentioned electric charge capture layer includes oxide-nitride-oxide composite bed.
In an exemplary embodiment, the material of above-mentioned conductor layer includes metal.
In an exemplary embodiment, the material of above-mentioned conductor layer includes DOPOS doped polycrystalline silicon.
In an exemplary embodiment, above-mentioned NAND Flash storage unit further includes first choice grid layer and the second selection
Grid layer.First choice grid layer is disposed on the side of the grid layer, and the second selection gate layer is disposed on the grid
The opposite side of pole layer.Above-mentioned channel layer, electric charge capture layer, conductor layer and the second dielectric layer can run through first choice grid layer with
Second selection gate layer.
In an exemplary embodiment, the material of above-mentioned channel layer includes non-crystalline silicon, polysilicon, microcrystal silicon, monocrystalline silicon, nanometer
Crystal silicon, oxide semiconductor material, organic semiconducting materials or its combination.
For another angle, an exemplary embodiment of the invention proposes that one kind is used for above-mentioned NAND Flash storage unit
Read method.This read method includes：One reading voltage is put on into one of described grid layer；Pass through voltage by one
Put on the wherein another of the grid layer；One first voltage is put on to the side of conductor layer.Wherein read voltage
Level is one of a positive level and a negative level, and the level of first voltage for positive level and negative level wherein it
It is another.
In an exemplary embodiment, above-mentioned read method further includes：One second voltage is put on into first choice grid
Pole layer and the second selection gate layer, the wherein level of second voltage are added for system level and a critical level.
In an exemplary embodiment, above-mentioned read method further includes：The first end of above-mentioned channel layer is pre-charged to being
System level；And whether decline is had according to the level of the first end of channel layer, judge that the grid layer institute for being applied in reading voltage is right
Whether the transistor answered turns on.
For another angle, an exemplary embodiment of the invention proposes a kind of operation side of NAND Flash storage unit
Method.This NAND Flash storage unit includes multiple grid layers, a conductive structure and an electric charge capture layer.Conductive structure is caught with electric charge
Grid layer can be run through by obtaining layer, and electric charge capture layer is disposed between conductive structure and grid layer.This operating method includes：Will
One potential difference is applied between a first end of conductive structure and a second end of conductive structure, in conductive structure
Produce electric current and to heat electric charge capture layer.
In an exemplary embodiment, the material of above-mentioned conductive structure is DOPOS doped polycrystalline silicon.
In an exemplary embodiment, above-mentioned the step of being applied to potential difference between the first end second end of conductive structure, is also
Including：One voltage of erasing is applied on conductive structure.
In an exemplary embodiment, above-mentioned NAND Flash storage unit further includes a first choice grid layer and one
Second selection gate layer.First choice grid layer is disposed on the side of the grid layer, and the second selection gate layer is disposed on
The opposite side of the grid layer, wherein conductive structure can run through first choice grid layer and the second selection gate with electric charge capture layer
Layer.This operating method further includes：One reference voltage is put on into grid layer；And a tertiary voltage is put on into first choice
Grid layer and the second selection gate layer.The level of tertiary voltage is level, the level and one for voltage of erasing according to reference voltage
Produced by wearing the level of voltage then.
In an exemplary embodiment, above-mentioned the step of being applied to potential difference between the first end second end of conductive structure, is also
Including：One system voltage is applied to first choice grid layer and the second selection gate layer；And grid will be applied to by voltage
On the layer of pole.
In an exemplary embodiment, first end and the second end of above-mentioned conductive structure are a first ends positioned at conductor layer
With a second end.
In an exemplary embodiment, above-mentioned operating method further includes：One voltage of erasing is put on into one end of channel layer；
One reference voltage is put on into grid layer；And a tertiary voltage is put on into first choice grid layer and the second selection gate
Layer.The level of wherein tertiary voltage is produced according to the level of reference voltage, the level for voltage of erasing, with wearing the level of voltage then
It is raw.
In an exemplary embodiment, the first end of conductor layer and the level of second end are according to the level of reference voltage, smear
Except produced by the level of voltage and the level of an offset voltage, and there are above-mentioned between the first end and second end of conductor layer
Potential difference.
In an exemplary embodiment, above-mentioned operating method further includes：By grid layer, first choice grid layer, the second choosing
Select grid layer, the first end of channel layer and second end suspension joint.
In an exemplary embodiment, above-mentioned operating method further includes：By the level of the first end of conductor layer and second end
Parameter as a function inputs, and wherein function exports a numerical value, and this numerical value is between the first end and second end of conductor layer
Level between；The voltage for meeting numerical value is put on into the grid layer, first choice grid layer, the second selection gate layer, logical
The first end and second end of channel layer.
Based on NAND Flash storage unit, read method and operation side above-mentioned, proposed in exemplary embodiment of the present invention
In method, electric charge capture layer can be heated when erase operation, thus increase the speed for operation of erasing.Heat electric charge capture layer
It may also be used for repairing electric charge capture layer.In addition, the control ability of grid layer can be carried when reading NAND Flash storage unit
Rise.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make
Carefully it is described as follows.
Brief description of the drawings
Figure 1A is the schematic diagram that NAND Flash storage unit is shown according to an exemplary embodiment；
Figure 1B is the section that the NAND Flash storage unit in Figure 1A along P1-P2 sections is shown according to an exemplary embodiment
Schematic diagram；
Fig. 1 C are the circuit diagrams that NAND Flash storage unit is shown according to an exemplary embodiment；
Fig. 2 is the partial schematic diagram that NAND Flash storage unit module is shown according to an exemplary embodiment；
Fig. 3 is the top view that NAND Flash storage unit 100 is shown according to the first exemplary embodiment；
Fig. 4 is V diagram when showing erase operation according to the first exemplary embodiment；
Fig. 5 is to be shown to repair the V diagram of electric charge capture layer according to the first exemplary embodiment；
Fig. 6 A are the top views that NAND Flash storage unit 600 is shown according to the second exemplary embodiment；
Fig. 6 B are to be shown according to the second exemplary embodiment in Fig. 6 A along the NAND Flash storage unit 600 of P3-P4 sections
Diagrammatic cross-section；
Fig. 7 is V diagram when showing erase operation according to the second exemplary embodiment；
Fig. 8 is to be shown to repair the V diagram of electric charge capture layer according to the second exemplary embodiment.
Fig. 9 is to show the V diagram that is read according to the second exemplary embodiment；
Figure 10 A are to show the schematic diagram of voltage and electric current on grid layer 130a according to the second exemplary embodiment；
Figure 10 B are to show that storage unit is programmed the schematic diagram being respectively distributed afterwards according to the second exemplary embodiment；
Figure 10 C are the schematic diagrames that lifting control ability is shown according to the second exemplary embodiment；
Figure 11 is the flow chart that read method is shown according to the second exemplary embodiment.
Description of reference numerals：
100、210、220、600：NAND Flash storage unit；
110、140、212、214、222、224：Selection gate layer；
120a~120b, 620：Dielectric layer；
130a~130d：Grid layer；
150：Electric charge capture layer；
160：Conductive structure；
172、612、632：First end；
174、614、634：Second end；
176：Electric current；
180a~180f：Transistor；
310、330：Silicon oxide layer；
320：Silicon nitride layer；
340、610：Channel layer；
630：Conductor layer；
1010a~1010d：Distribution；
1020、1022：Level；
1032、1034、1036：The magnitude of current；
1042、1044、1052、1054：Curve；
1062、1064、1066、1068：Level；
1072、1074：Section；
S1102、S1104、S1106：Step.
Embodiment
Figure 1A is the schematic diagram that NAND Flash storage unit is shown according to an exemplary embodiment.Figure 1B is real according to an example
Apply the diagrammatic cross-section for exemplifying the NAND Flash storage unit in Figure 1A along P1-P2 sections.
Figure 1A and Figure 1B are refer to, NAND Flash storage unit 100 includes (also referred to as the first choosing of a selection gate layer 110
Select grid layer), multiple grid layer 130a~130d and selection gate layer 140 (also referred to as the second selection gate layer).Grid layer
130a~130d is to stack each other, and can include a dielectric layer (also referred to as first Jie between the adjacent grid layer of each two
Electric layer, is, for example, dielectric layer 120b).Selection gate layer 110 is disposed on the side of grid layer 130a~130d, and selection gate
Layer 140 is disposed on the opposite side of grid layer 130a~130d.It can include one between selection gate layer 110 and grid layer 130a
A dielectric layer 120a；An interface layer (not shown) can also be included between selection gate layer 140 and grid layer 130d.It is worth note
Meaning, goes out dielectric layer 120a, 120b, so that selection gate layer 110,140 and grid layer for simplicity, not shown in Figure 1B
Relation between 130a~130d becomes apparent from.NAND Flash storage unit 100 further includes electric charge capture layer 150 and conductive structure
160, and electric charge capture layer 150 can be through selection gate layer 110,140, dielectric layer 120a, 120b and grid with conductive structure 160
Pole layer 130a~130d.It is worth noting that, merely illustrate 4 grid layer 130a~130d, but this hair in Figure 1A and Figure 1B
It is bright and not subject to the limits.In other exemplary embodiments, NAND Flash storage unit 100 may include the more or fewer grids of number
Layer.
The material of dielectric layer 120a, 120b may include silica, phosphorosilicate glass (phosphosilicate glass, PSG)
Or other advanced low-k materials.The material of selection gate layer 110,140 and grid layer 130a~130d may include doped
Polysilicon or metal.In this exemplary embodiment, electric charge capture layer 150 is formed as combined by multiple dielectric layers.For example,
The material of electric charge capture layer 150 can include oxide-nitride-oxide composite bed.It is above-mentioned in another exemplary embodiment
Silicon nitride can also be replaced into doped Polysilicon floating gate (floating gate) layer or other are available
It is of the invention and not subject to the limits with stored electrons or the material in hole.Conductive structure 160 may include metal or doped polycrystalline
Silicon.Specifically, a potential difference can be applied between the first end 172 of conductive structure 160 and second end 174, to lead
An electric current 176 is produced in electric structure 160.In this exemplary embodiment, first end 172 is drain electrode end, and second end 174 is source electrode
End, that is to say, that electric current 176 is to flow to drain electrode end from source terminal.However, in other exemplary embodiments, first end 172 can be with
It is source terminal, second end 174 can be drain electrode end；Alternatively, electric current 176 can also flow to source terminal from drain electrode end, the present invention is simultaneously
It is not subject to the limits.Electric current 176 is to heat electric charge capture layer 150.In an exemplary embodiment, heating electric charge capture layer 150 can
With the speed for increasing the service life of NAND Flash storage unit 100 or increasing operation of erasing.Example reality will be lifted again below
Apply example detailed description.
Fig. 1 C are the circuit diagrams that NAND Flash storage unit is shown according to an exemplary embodiment.
Figure 1B and Fig. 1 C are refer to, selection gate layer 110,140, grid layer 130a~130d, electric charge capture layer 150 are with leading
The combination of electric structure 160 can be considered as transistor 180a~180f.Conductive structure 160 can include transistor 180a~180f
Passage.Selection gate layer 110,140 is respectively as the control gate of transistor 180a and 180f.Grid layer 130a~130d is to do
For the control gate of transistor 180b~180e.That is, on selection gate layer 110,140 and grid layer 130a~130d
Whether it to controlling transistor 180a~180f is conducting that voltage is.Transistor 180b~180e is referred to alternatively as storage unit again
(memory cell), and each storage unit can store one or more bits.
Fig. 2 is the partial schematic diagram that NAND Flash storage unit module is shown according to an exemplary embodiment.
NAND Flash storage unit 100 can be included in a NAND Flash storage module, and this NAND Flash
Storage module may also include other structures for being similar to NAND Flash storage unit 100.NAND Flash storage unit 100 and its
His similar structure can be combined into a physical blocks, and NAND Flash storage module may include multiple entity areas
Block.For example, as shown in Fig. 2, NAND Flash storage module 200 includes NAND Flash storage unit 100,210 and 220, it is common
Enjoy grid layer 130a~130d.Also conductive structure and electric charge capture layer can be included in NAND Flash storage unit 210 and 220.
NAND Flash storage unit 210 further includes selection gate layer 212 and 214.NAND Flash storage unit 220 further includes selection gate
Layer 222 and 224.Conductive structure in NAND Flash storage unit 100,210 and 220 can as bit line (bit line),
And each grid layer 130a~130d can regard a character line (word line).It is worth noting that, NAND Flash is deposited
The upper and lower ends of storage unit 100,210 and 220 are also connected to other structures (for example, another conductor), alternatively, selection gate
Layer 140,214,224 can be connected to each other, of the invention and not subject to the limits.
[the first exemplary embodiment]
Fig. 3 is the top view that NAND Flash storage unit 100 is shown according to the first exemplary embodiment.
Fig. 3 is refer to, in the first exemplary embodiment, electric charge capture layer 150 includes silicon oxide layer 310, silicon nitride layer 320
With silicon oxide layer 330.The conductive structure 160 of Figure 1A and Figure 1B is implemented as channel layer 340.The material of channel layer 340 includes warp
The polysilicon of doping.In this exemplary embodiment, channel layer 340 is by doped n+Type polysilicon is made.However, passage
Layer 340 can also be by doped p+Type polysilicon is made, of the invention and not subject to the limits.
Fig. 4 is V diagram when showing erase operation according to the first exemplary embodiment.
Refer to Figure 1B and Fig. 4, when erase operation, 0 volt of voltage can be applied in grid layer 130a~
On 130d；(Vera-VB2Bth) voltage of volt can be applied on selection gate layer 110,140；(Vera+ Δ V) volt voltage
Second end 174 can be applied in；And (Vera- Δ V) voltage can be applied in first end 172.Vera, Δ V and VB2BthFor reality
Number, but the present invention is not intended to limit Vera, Δ V and VB2BthNumerical value.VeraVoltage (the electricity of also referred to as erasing of (being, for example, 20) volt
Pressure) it is the data erased in NAND Flash storage unit 100 (it is stored in electric charge capture layer 150).And VB2BthVolt
Voltage (also referred to as wearing voltage then) be then intended to produce can interband tunneling effect (band to band tunneling
effect).Specifically, the potential difference between first end 172 and selection gate layer 110 is about VB2BthVolt so that electronics
First end 172 (or hole is moved to selection gate layer 110 from first end 172) can be moved to from selection gate layer 110.It is special
It is other to be, since a potential difference (2 Δ V) can be applied between the first end 172 of channel layer 340 and second end 174, thereby
Electric current can be produced in channel layer 340 to heat electric charge capture layer 150.Consequently, it is possible to the speed for operation of erasing can be increased.Herein
In exemplary embodiment, the voltage level of first end 172 is (Vera- Δ V) volt, and the voltage level of second end 174 is (Vera+
Δ V) volt.However, in other exemplary embodiments, the voltage level of first end 172 can be VeraVolt, and second end 174
Voltage level can be (Vera+ 2 Δ V) volt.Alternatively, the voltage level of first end 172 can be (Vera- 2 Δ V) volt,
And the voltage level of second end 174 can be VeraVolt.How the present invention applies a current potential and is worse than first end 172 if being not intended to limit
Between second end 174.
In this exemplary embodiment, the level on grid layer 130a~130d is 0 volt.However, implement in another example
In example, the level on grid layer 130a~130d can be an a reference value, at this time selection gate layer 110,140 and conductive structure
Level on 160 both ends can all be adjusted according to this reference value, such as plus this reference value.It is assumed herein that this reference value is 3,
Therefore a reference voltage can be applied in grid layer 130a~130d, and the level of reference voltage is 3 volts.One the 3rd electricity
Pressure can be applied in selection gate layer 110,140, and the level of this tertiary voltage is level, the voltage of erasing according to reference voltage
Level and produced by wearing the level of voltage then, be, for example, (3+Vera-VB2Bth) volt.In addition, the level in second end 174
It is (3+Vera+ Δ V) volt, and the level in first end 172 is (3+Vera- Δ V) volt.However, this reference value can be appointed
The real number of meaning, the present invention are not intended to limit this reference value is how many.
Fig. 5 is to be shown to repair the V diagram of electric charge capture layer according to the first exemplary embodiment.
Fig. 5 is refer to, in an exemplary embodiment, VpassThe voltage (also referred to as passing through voltage) of volt can be applied in
Grid layer 130a~130d；VccThe voltage (also referred to as system voltage) of volt can be applied in selection gate layer 110 and 140
On；0 volt of voltage can be applied in second end 174；And the voltage of V volts of Δ can be applied in first end 172.VpassWith Vcc
For real number, for example, VpassFor 6.5 and VccFor 3, but the present invention is not intended to limit VpassWith VccNumerical value.VpassThe voltage of volt
It is the transistor turns allowed corresponding to grid layer 130a~130d, and VccThe voltage of volt is to allow selection gate layer
110th, the transistor turns corresponding to 140.In this exemplary embodiment, if channel layer 340 is the n of doping+Type polysilicon or warp
The p of doping+Type polysilicon is made, then VpassThe voltage of volt can be 0.That is, whole channel layer 340 can be conducting
State, and a potential difference can be applied between first end 172 and second end 174 and heat charge-trapping to produce electric current
Layer 150.In other words, the electric current in channel layer 340 can be generated when erasing, and can also be produced at other any moment, this
Invent and not subject to the limits.Consequently, it is possible to which electric charge capture layer 150 can be repaired, therefore data are allowed to be not easy to lose (that is, increase
The service life of NAND Flash storage unit 100).
In the exemplary embodiment of Fig. 5, the level of second end 174 is 0 volt, and the level of first end 172 is Δ V volts
It is special.However, in other exemplary embodiments, the level of second end 174 can be arbitrary numerical value, and the level of first end 172
It can be a different numerical value, therefore potential difference is produced between first end 172 and second end 174.The present invention is not intended to limit
How this potential difference is produced.
[the second exemplary embodiment]
Fig. 6 A are the top views that NAND Flash storage unit 600 is shown according to the second exemplary embodiment.Fig. 6 B are according to
Two exemplary embodiments show the diagrammatic cross-section of the NAND Flash storage unit 600 along P3-P4 sections in Fig. 6 A.
Fig. 6 A and Fig. 6 B are refer to, in the second exemplary embodiment, electric charge capture layer 150 includes silicon oxide layer 310, nitridation
Silicon layer 320 and silicon oxide layer 330.Conductive structure 160 includes channel layer 610, dielectric layer 620 (also referred to as the second dielectric layer), with leading
Body layer 630.Channel layer 610 is arranged between dielectric layer 620 and silicon oxide layer 330, and dielectric layer 620 is disposed on channel layer
Between 610 and conductor layer 630.Channel layer 610, electric charge capture layer 150, selection gate layer 110,140 and grid layer 130a~
The combination of 130d can be considered as multiple transistors concatenated with one another.In this exemplary embodiment, the first end 612 of channel layer 610
For drain electrode end, second end 614 is source terminal.But in other exemplary embodiments, first end 612 or source terminal, and second
End 614 can be drain electrode end, of the invention and not subject to the limits.
The material of channel layer 610 includes non-crystalline silicon, polysilicon, microcrystal silicon, monocrystalline silicon, nanocrystal silicon, oxide semiconductor
The combination of material, organic semiconducting materials, other suitable materials or above-mentioned at least two kinds materials.In this exemplary embodiment,
Channel layer 610 is made of N-shaped polysilicon.However, channel layer 610 can also be as made by p-type, the present invention is simultaneously
It is not subject to the limits.The material of dielectric layer 620 include silica, phosphorosilicate glass (phosphosilicate glass, PSG) or its
His advanced low-k materials.And the material of conductor layer 630 may include metal or doped polysilicon.
Fig. 7 is V diagram when showing erase operation according to the second exemplary embodiment.
Fig. 6 B and Fig. 7 are refer to, 0 volt of voltage can be applied on grid layer 130a~130d.(Vera-VB2Bth) volt
Special voltage can be applied in selection gate layer 110 and 140.VeraThe voltage of volt can be applied in first end 612 and second end
614.Specifically, a potential difference can be applied between the both ends of conductor layer 630.For example, (Vera+ Δ V) volt voltage
Second end 634, (V can be applied inera- Δ V) voltage of volt can be applied in first end 632.Consequently, it is possible to smeared
During division operation, an electric current can be produced in conductor layer 630 so that electric charge capture layer 150 can be heated, therefore accelerate operation of erasing.
However, in another exemplary embodiment, VeraThe voltage of volt can be applied in first end 612 and second end 614 wherein it
One, and the other end can be then suspension joint (floating), it is of the invention and not subject to the limits.
With first embodiment similarly, the level on grid layer 130a~130d can be an a reference value, select at this time
Select grid layer 110,140, the level in first end 612 and second end 614 can all be adjusted according to this reference value, such as plus this
A reference value, it is no longer repeated herein.In an exemplary embodiment, first end 632 also can basis with the level in second end 634
Reference voltage and adjust (for example, adding a reference value).That is, first end 632 and the level of second end 634 are according to benchmark
Produced by the level of voltage, the level for voltage of erasing and the level of offset voltage (voltages that V volts of Δ), wherein first end 632
There is the potential difference of for example, V volts of 2 Δ between second end 634.How the present invention applies a current potential and is worse than if being not intended to limit
Between first end 632 and second end 634.
Fig. 8 is to be shown to repair the V diagram of electric charge capture layer according to the second exemplary embodiment.
It refer to Fig. 8, grid layer 130a~130d, selection gate layer 110 and 140, first end 612 and 614 meeting of second end
By suspension joint (floating).In other words, grid layer 130a~130d, selection gate layer 110 and 140, first end 612 and second
The level at end 614 can be arbitrary value, and can differ each other.One potential difference can be applied in the two of conductor layer 630
Between end.For example, 0 volt of voltage can be applied in second end 634, and the voltage of V volts of Δ can be applied in first end
632.In the same manner, the potential difference on 630 both ends of conductor layer is to produce an electric current to heat electric charge capture layer 150.Namely
Say, electric charge capture layer 150 can be heated in the random time beyond operation of erasing, therefore allow data to be not easy to lose.
, can be using ginseng of the first end 632 with the level in second end 634 as a function in another exemplary embodiment
Number input, and this function can export a numerical value.Grid layer 130a~130d, selection grid can be applied in by meeting the voltage of this numerical value
Pole layer 110,140, first end 612 and second end 614.The numerical value of this output can be between the level of first end 632 and second end 634
Between.For example, the level of first end 632 is 5 volts, and the level of second end 634 is 7 volts, and the numerical value of function output
It is 6.Consequently, it is possible to the state of sequencing can be entered to avoid NAND Flash storage unit 600.However, the present invention is not intended to limit
The numerical value of this output is how many.
In the exemplary embodiment of Fig. 8, the level of second end 634 is 0 volt, and the level of first end 632 is Δ V volts
It is special.However, in other exemplary embodiments, the level of second end 634 can be arbitrary numerical value, and the level of first end 632
It can be a different numerical value, therefore potential difference is produced between first end 632 and second end 634.The present invention is not intended to limit
How this potential difference is produced.
Fig. 9 is to show the V diagram that is read according to the second exemplary embodiment.
Fig. 6 B and Fig. 9 are refer to, it is assumed herein that to read the data stored by the transistor corresponding to grid layer 130a.
VreadThe voltage (also referred to as reading voltage) of volt can be applied in grid layer 130a.VpassThe voltage of volt can be applied in
Grid layer 130b~130d.(Vcc+Vt) voltage of volt can be applied in selection gate layer 110 and 140.0 volt of voltage meeting
It is applied in second end 614.VccThe voltage of volt can be applied in first end 612.Voltage (also referred to as first electricity of (- V) volt
Pressure) conductor layer 630 can be applied in.Vread、Vpass、Vcc、Vt, V be real number, but the present invention is not intended to limit its value is how many.According to
VreadNumerical value, the transistor corresponding to grid layer 130a may be switched on or be not turned on.VpassVoltage be to turn on
Transistor corresponding to grid layer 130b~130d.(Vcc+Vt) volt voltage be also turn on selection gate layer 110 with
Transistor corresponding to 140.VtAlso referred to as critical level, and the level on selection gate layer 110,140 can be VccWith Vt's
It is added.Therefore the potential difference between selection gate layer 110 and first end 612 can be critical level Vt, so VtIt is to turn on choosing
Select the transistor corresponding to grid layer 110.VccThe voltage of volt is then that the transistor tested corresponding to grid layer 130a is
It is no to be switched on, therefore read data stored in this transistor.Specifically, first end 612 can first be precharged (pre-
Charge) to VccVolt (also referred to as system level), corresponding to grid layer 130b~130d and selection gate layer 110 and 140
After transistor all turns on, if the voltage of first end 612 has decline, represent that the transistor corresponding to grid layer 130a is led
It is logical.In an exemplary embodiment, Vread、Vpass、VccWith the numerical value of V for just, and the level in conductor layer 630 is negative (that is, leads
The level of body layer 630 is less than the level of ground terminal (0V)).Consequently, it is possible to the electrons in channel layer 610 are close to grid layer
130a, therefore the control ability of grid layer 130a can be increased.
In another exemplary embodiment, the material of channel layer 610 is p-type polysilicon, reads the level (V of voltageread) meeting
Less than 0, and the level (- V) of first voltage can be more than 0, therefore allow the hole in channel layer 610 close to grid layer 130a.Change speech
It, if the level for reading voltage is positive level, the level of first voltage is negative level.If the level for reading voltage is negative electricity
Flat, then the level of first voltage is positive level (voltage for being more than ground terminal).
Figure 10 A are to show the schematic diagram of voltage and electric current on grid layer 130a according to the second exemplary embodiment.Figure 10 B are roots
Show that storage unit is programmed the schematic diagram being respectively distributed afterwards according to the second exemplary embodiment.
The transverse axis of Figure 10 A is the level on grid layer 130a, and the longitudinal axis is the size of electric current in channel layer 610.The horizontal stroke of Figure 10 B
Axis is the critical voltage of a storage unit, and the longitudinal axis is number of memory cells.Fig. 6 B, Figure 10 A and Figure 10 B are refer to, it is false herein
If two bits can be stored in a storage unit.Therefore, when the storage unit (transistor) corresponding to grid 130a is by journey
After sequence, the critical voltage of this transistor can be one of four distribution 1010a~1010d.For example, it is distributed
1010a represents bit " 11 ", and is distributed 1010d and represents bit " 00 ".If the critical voltage of this transistor is distribution 1010a, and
When level on grid layer 130a is level 1020, then this transistor can be fully on, that is, represents the ratio stored by this transistor
Spy is " 11 ".On the other hand, if the level on grid layer 130a is level 1022, this transistor meeting " part " conducting, passage
The size of electric current can be the magnitude of current 1034 on layer 610.In an exemplary embodiment, the magnitude of current 1032 and the magnitude of current 1036 be for
Judge the critical value whether transistor turns on.For example, when the electric current in channel layer 610 is more than the magnitude of current 1032, then it represents that right
The transistor answered is conducting.On the other hand, when the electric current in channel layer 610 is less than the magnitude of current 1036, then it represents that corresponding crystalline substance
Body pipe is not conducting.Therefore, the magnitude of current 1032 and the magnitude of current 1036 can be used for distinguishing this transistor be belong to distribution 1010a~
Which of 1010d.When it is to belong to which of distribution 1010a~1010d that transistor, which is easier to be distinguished out it, table
Show that the control ability of grid layer 130a is preferable.
Figure 10 C are the schematic diagrames that lifting control ability is shown according to the second exemplary embodiment.
Figure 10 A, Figure 10 B and Figure 10 C are refer to, curve 1042 and 1044 as shown in Figure 10 A, is represented when negative voltage adds
Voltage-current relation curve in conductor layer 630.However, curve 1052 and 1054 are when no negative voltage is added in conductor
Voltage-current relation curve during layer 630.First by taking curve 1042 and 1044 as an example, when a transistor is programmed for being distributed
During 1010a, the magnitude of current 1032 is corresponding to level 1062；When transistor is programmed for distribution 1010b, the magnitude of current 1036 is
Correspond to level 1064；That is, can't judge transistor is which distribution belonged to by accident in section 1072.With curve
Exemplified by 1052 and 1054, the magnitude of current 1032 is corresponding to level 1066, and the magnitude of current 1036 corresponds to level 1068；In area
Between can't judge transistor is which distribution belonged in 1074 by accident.However, it was found from Figure 10 C, the width in section 1072 can be big
Width in section 1074.That is, after negative voltage being applied to conductor layer 630, it is easier to which it is to belong to distinguish transistor
Which it is distributed in, i.e., the control ability of grid layer 130a can be lifted.
Figure 11 is the flow chart that read method is shown according to the second exemplary embodiment.
Figure 11 is refer to, each step of Figure 11 is the NAND Flash storage unit for Fig. 6 A and Fig. 6 B.In step S1102
In, voltage will be read and put on one of grid layer 130a~130d.In step S1104, electricity is read except being applied in
Beyond the grid layer of pressure, other grid layers in grid layer 130a~130d will be put on by voltage.In step S1106,
First voltage is put on to one end of conductor layer 630.The level for wherein reading voltage is one of positive level and negative level,
And the level of first voltage is wherein another for positive level and negative level.That is, if the level of voltage is read as just
Level, then the level of first voltage is negative level (level for being less than ground terminal).If the level for reading voltage is negative level, the
The level of one voltage is positive level (level for being more than ground terminal).
Each step can be implemented as multiple procedure codes and perform these procedure codes by a processor in Figure 11.Or
Person, each steps of Figure 11 can be implemented as one or more circuits, of the invention and not subject to the limits.
On the other hand, an of the invention exemplary embodiment is it is also proposed that a kind of operating method, be for the first exemplary embodiment or
It is the second exemplary embodiment.In this operating method, a potential difference can be applied to the first end of conductive structure and second end it
Between, to produce an electric current in conductive structure and to heat electric charge capture layer.However, this operating method has described in detail
As above, just repeat no more herein.
In conclusion the operating method proposed in exemplary embodiment of the present invention, read method and NAND Flash storage are single
In member, electric charge capture layer can be heated accelerate to erase operation or reparation electric charge capture layer.In addition, in an exemplary embodiment
In, since the voltage being applied in conductor layer is in contrast to voltage is read, the control ability of grid layer also can be elevated.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe is described in detail the present invention with reference to foregoing embodiments, it will be understood by those of ordinary skill in the art that：Its according to
Can so modify to the technical solution described in foregoing embodiments, either to which part or all technical characteristic into
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (9)
1. a kind of operating method of NAND Flash storage unit, it is characterised in that the NAND Flash storage unit includes multiple grid
Pole layer, a conductive structure and an electric charge capture layer, the conductive structure run through those grid layers, and the electricity with the electric charge capture layer
Lotus trapping layer is disposed between the conductive structure and those grid layers, wherein in those grid layers two adjacent grid layers it
Between include one first dielectric layer, which includes a channel layer, a conductor layer and one second dielectric layer, second dielectric layer
It is arranged between the channel layer and the conductor layer, a first end and a second end for the conductive structure is positioned at the conductor layer
One first end and a second end, wherein the NAND Flash storage unit further include：
One first choice grid layer, configures in the side of those grid layers；And
One second selection gate layer, configures the opposite side in those grid layers, wherein the channel layer, the conductor layer, second Jie
Electric layer runs through the first choice grid layer and the second selection gate layer with the electric charge capture layer,
The operating method includes：
One potential difference is applied between the first end of the conductive structure and the second end of the conductive structure, to be led at this
An electric current is produced in electric structure and to heat the electric charge capture layer, wherein the potential difference is applied to being somebody's turn to do for the conductive structure
The step of between the first end second end, includes：
When erase operation when, a voltage of erasing is put on into one end of the channel layer, and a reference voltage is put on
Those grid layers,
Wherein the first end of the conductor layer and the level of the second end are level, voltage of erasing according to the reference voltage
Produced by the level of level and an offset voltage, and there are the current potential between the first end and the second end of the conductor layer
Difference.
2. operating method according to claim 1, it is characterised in that the material of the channel layer includes DOPOS doped polycrystalline silicon.
3. operating method according to claim 2, it is characterised in that the NAND Flash storage unit further includes：
One first choice grid layer, configures in the side of those grid layers；And
One second selection gate layer, configures the opposite side in those grid layers, and wherein the conductive structure is passed through with the electric charge capture layer
The first choice grid layer and the second selection gate layer are worn,
Wherein the operating method further includes：
One reference voltage is put on into those grid layers；And
One tertiary voltage is put on into the first choice grid layer and the second selection gate layer, the wherein level of the tertiary voltage
It is according to produced by the level of the reference voltage, the level of the voltage of erasing and one wear the level of voltage then.
4. operating method according to claim 2, it is characterised in that the NAND Flash storage unit further includes one first choosing
Grid and one second selection gate are selected, which is disposed on the side of those grid layers, second selection grid
Pole layer is disposed on the opposite side of those grid layers, and the conductive structure runs through the first choice grid with the electric charge capture layer
Layer and the second selection gate layer, wherein the potential difference to be applied to the step between the first end of conductive structure second end
Suddenly further include：
When being operated without erasing, a system voltage is applied to the first choice grid layer and the second selection gate layer,
And one is applied on these grid layers by voltage；And
Apply respectively different voltage to the conductive structure the first end and the second end so that the conductive structure this first
There are the potential difference between end and the second end.
5. operating method according to claim 1, it is characterised in that further include：
One tertiary voltage is put on into the first choice grid layer and the second selection gate layer, the wherein level of the tertiary voltage
It is according to produced by the level of the reference voltage, the level of the voltage of erasing and one wear the level of voltage then.
6. operating method according to claim 1, it is characterised in that further include：
By those grid layers, the first choice grid layer, the second selection gate layer, the channel layer a first end and this lead to
One second end suspension joint of channel layer.
7. operating method according to claim 1, it is characterised in that further include：
Inputted the level of the first end of the conductor layer and the second end as the parameter of a function, wherein function output one
Numerical value, and the numerical value is between the first end of the conductor layer and the level of the second end；
By the voltage for meeting the numerical value puts on those grid layers, the first choice grid layer, the second selection gate layer, this leads to
One first end of channel layer and a second end of the channel layer.
8. operating method according to claim 1, it is characterised in that the material of the conductor layer includes a metal.
9. operating method according to claim 1, it is characterised in that the material of the conductor layer includes a DOPOS doped polycrystalline silicon.
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