CN104103639A - NAND quick-flash memory unit, operation method and read method - Google Patents
NAND quick-flash memory unit, operation method and read method Download PDFInfo
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- CN104103639A CN104103639A CN201310114288.0A CN201310114288A CN104103639A CN 104103639 A CN104103639 A CN 104103639A CN 201310114288 A CN201310114288 A CN 201310114288A CN 104103639 A CN104103639 A CN 104103639A
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Abstract
The invention provides an NAND quick-flash memory unit, an operation method and a read method. The NAND quick-flash memory unit comprises multiple grid electrode layers, a channel layer, a charge capture layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent grid electrode layers in the grid electrode layers. The channel layer, the charge capture layer, the conductor layer and the second dielectric layer penetrate through all the grid electrode layers. The charge capture layer is configured between the channel layer and the grid electrode layers, and the second dielectric layer is configured between the conductor layer and the channel layer. Therefore, erase speed can be enhanced, the charge capture layer can be restored and control capacity of the grid electrode layers can be enhanced.
Description
Technical field
The invention relates to a kind of flash memory cell, and relate to especially a kind of NAND flash memory cell, method of operation and read method.
Background technology
Enable nand gate is widely used in the design of nonvolatile memory device, to increase storage density.A NAND flash memory cell generally includes the multiple memory cell that are one another in series and connect.Along with the micro of processing procedure, in NAND flash, can face many difficulties and cause data reliability reduce.Industry has proposed the NAND flash memory cell of many three-dimensionals in recent years, to attempt solving the problem that microtechnology is encountered, be for example million cellular array transistors (Terabit Cell array transistor, TCAT), push away repeatedly memory array rowed transistor (Stacked Memory Array Transistor, or bit cost extendible (Bit Cost Scalable, BiCS) technology SMArT).In some three dimensional NAND flash memory cells, be to carry out storage data with silicon nitride, but the data of this memory cell are preserved (data retention) and the speed of erasing cannot get both, once will increase the speed of erasing, data preservation will variation.Therefore, how to take into account the speed of erasing and the data of flash memory cell and preserve, the subject under discussion that those skilled in the art are concerned about for this reason.
Summary of the invention
The invention provides a kind of NAND flash memory cell, corresponding method of operation and read method, can promote the speed of erase operation for use, repairs electric charge capture layer, and increase the control ability of grid layer.
One example of the present invention embodiment proposes a kind of NAND flash memory cell, comprises multiple grid layers, channel layer, electric charge capture layer, conductor layer and the second dielectric layer.Wherein between two adjacent grid layers, comprise first dielectric layer.Channel layer, electric charge capture layer, conductor layer and the second dielectric layer can run through described grid layer.Electric charge capture layer is to be configured between channel layer and described grid layer, and the second dielectric layer is to be configured between conductor layer and channel layer.
In an exemplary embodiment, above-mentioned electric charge capture layer comprises silica-silicon-nitride and silicon oxide composite bed.
In an exemplary embodiment, the material of above-mentioned conductor layer comprises metal.
In an exemplary embodiment, the material of above-mentioned conductor layer comprises doped polycrystalline silicon.
In an exemplary embodiment, above-mentioned NAND flash memory cell also comprises the first selection grid layer and the second selection grid layer.The first selection grid layer is a side that is configured in described grid layer, and the second selection grid layer is the opposite side that is configured in described grid layer.Above-mentioned channel layer, electric charge capture layer, conductor layer and the second dielectric layer can run through the first selection grid layer and second selects grid layer.
In an exemplary embodiment, the material of above-mentioned channel layer comprises amorphous silicon, polysilicon, microcrystal silicon, monocrystalline silicon, nanocrystal silicon, oxide semiconductor material, organic semiconducting materials or its combination.
With another one angle, the present invention's one exemplary embodiment proposes a kind of read method for above-mentioned NAND flash memory cell.This read method comprises: read voltage and put on one of them of described grid layer by one; Put on wherein another of described grid layer by one by voltage; First voltage is put on to a side of conductor layer.The level that wherein reads voltage is one of them of a positive level and a negative level, and the level of the first voltage is wherein another of positive level and negative level.
In an exemplary embodiment, above-mentioned read method also comprises: a second voltage is put on to the first selection grid layer and second and select grid layer, wherein the level of second voltage is the addition of a system level and a critical level.
In an exemplary embodiment, above-mentioned read method also comprises: the first end of the above-mentioned channel layer of precharge is to system level; And whether having decline according to the level of the first end of channel layer, judgement is applied in the whether conducting of the corresponding transistor of grid layer of reading voltage.
With another one angle, the present invention's one exemplary embodiment proposes a kind of method of operation of NAND flash memory cell.This NAND flash memory cell comprises multiple grid layers, a conductive structure and an electric charge capture layer.Conductive structure and electric charge capture layer can run through grid layer, and electric charge capture layer is to be configured between conductive structure and grid layer.This method of operation comprises: a potential difference is applied between first end and second end of conductive structure of conductive structure, in order to generation current in conductive structure and in order to heat electric charge capture layer.
In an exemplary embodiment, the material of above-mentioned conductive structure is doped polycrystalline silicon.
In an exemplary embodiment, the step between above-mentioned first end the second end that potential difference is applied to conductive structure also comprises: the voltage of erasing is applied on conductive structure.
In an exemplary embodiment, above-mentioned NAND flash memory cell also comprises that one first is selected grid layer and one second selection grid layer.The first selection grid layer is a side that is configured in described grid layer, and the second selection grid layer is the opposite side that is configured in described grid layer, and wherein conductive structure and electric charge capture layer can run through the first selection grid layer and the second selection grid layer.This method of operation also comprises: a reference voltage is put on to grid layer; And a tertiary voltage is put on to the first selection grid layer and the second selection grid layer.The level of tertiary voltage be according to the level of the level of reference voltage, the voltage of erasing, with one wear the then level of voltage and produce.
In an exemplary embodiment, the step between above-mentioned first end the second end that potential difference is applied to conductive structure also comprises: a system voltage is applied to the first selection grid layer and second and selects grid layer; And will be applied on grid layer by voltage.
In an exemplary embodiment, the first end of above-mentioned conductive structure and the second end are a first end and second ends that is positioned at conductor layer.
In an exemplary embodiment, above-mentioned method of operation also comprises: the voltage of erasing is put on to one end of channel layer; One reference voltage is put on to grid layer; And a tertiary voltage is put on to the first selection grid layer and the second selection grid layer.Wherein the level of tertiary voltage be according to the level of the level of reference voltage, the voltage of erasing, with wear the then level of voltage and produce.
In an exemplary embodiment, the level of the first end of conductor layer and the second end is to produce according to the level of the level of the level of reference voltage, the voltage of erasing and an offset voltage, and has above-mentioned potential difference between the first end of conductor layer and the second end.
In an exemplary embodiment, above-mentioned method of operation also comprises: select grid layer, second to select first end and the second end suspension joint of grid layer, channel layer grid layer, first.
In an exemplary embodiment, above-mentioned method of operation also comprises: the parameter input using the level of the first end of conductor layer and the second end as a function, and wherein function is exported a numerical value, and this numerical value is between the first end of conductor layer and the level of the second end; The voltage that meets numerical value is put on to described grid layer, first selects grid layer, second to select first end and second end of grid layer, channel layer.
Based on above-mentioned, in NAND flash memory cell, read method and the method for operation proposing in exemplary embodiment of the present invention, can in the time carrying out erase operation for use, heat electric charge capture layer, increase thus the speed of erase operation for use.Heating electric charge capture layer also can be used for repairing electric charge capture layer.In addition, in the time reading NAND flash memory cell, the control ability of grid layer can be raised.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Brief description of the drawings
Figure 1A is the schematic diagram that NAND flash memory cell is shown according to an exemplary embodiment;
Figure 1B illustrates in Figure 1A along the generalized section of the NAND flash memory cell of P1-P2 section according to an exemplary embodiment;
Fig. 1 C is the circuit diagram that NAND flash memory cell is shown according to an exemplary embodiment;
Fig. 2 is the part schematic diagram that NAND flash memory cell module is shown according to an exemplary embodiment;
Fig. 3 is the top view that NAND flash memory cell 100 is shown according to the first exemplary embodiment;
Fig. 4 illustrates the voltage schematic diagram while carrying out erase operation for use according to the first exemplary embodiment;
Fig. 5 illustrates according to the first exemplary embodiment the voltage schematic diagram of repairing electric charge capture layer;
Fig. 6 A is the top view that NAND flash memory cell 600 is shown according to the second exemplary embodiment;
Fig. 6 B illustrates in Fig. 6 A along the generalized section of the NAND flash memory cell 600 of P3-P4 section according to the second exemplary embodiment;
Fig. 7 illustrates the voltage schematic diagram while carrying out erase operation for use according to the second exemplary embodiment;
Fig. 8 illustrates according to the second exemplary embodiment the voltage schematic diagram of repairing electric charge capture layer.
Fig. 9 illustrates according to the second exemplary embodiment the voltage schematic diagram that carries out read operation;
Figure 10 A is the schematic diagram that the upper voltage of grid layer 130a and electric current are shown according to the second exemplary embodiment;
Figure 10 B illustrates according to the second exemplary embodiment the schematic diagram respectively distributing after memory cell is by sequencing;
Figure 10 C illustrates according to the second exemplary embodiment the schematic diagram that promotes control ability;
Figure 11 is the flow chart that read method is shown according to the second exemplary embodiment.
Description of reference numerals:
100,210,220,600:NAND flash memory cell;
110,140,212,214,222,224: select grid layer;
120a～120b, 620: dielectric layer;
130a～130d: grid layer;
150: electric charge capture layer;
160: conductive structure;
172,612,632: first end;
174,614,634: the second ends;
176: electric current;
180a～180f: transistor;
310,330: silicon oxide layer;
320: silicon nitride layer;
340,610: channel layer;
630: conductor layer;
1010a～1010d: distribute;
1020,1022: level;
1032,1034,1036: the magnitude of current;
1042,1044,1052,1054: curve;
1062,1064,1066,1068: level;
1072,1074: interval;
S1102, S1104, S1106: step.
Embodiment
Figure 1A is the schematic diagram that NAND flash memory cell is shown according to an exemplary embodiment.Figure 1B illustrates in Figure 1A along the generalized section of the NAND flash memory cell of P1-P2 section according to an exemplary embodiment.
Please refer to Figure 1A and Figure 1B, NAND flash memory cell 100 comprises that one is selected grid layer 110 (also claiming the first selection grid layer), multiple grid layer 130a～130d and a selection grid layer 140 (also claiming the second selection grid layer).Grid layer 130a～130d stacks each other, and between every two adjacent grid layers, can comprise a dielectric layer (also claiming the first dielectric layer, for example, is dielectric layer 120b).Selecting grid layer 110 is sides that are configured in grid layer 130a～130d, is the opposite sides that are configured in grid layer 130a～130d and select grid layer 140.Selecting can to comprise a dielectric layer 120a between grid layer 110 and grid layer 130a; Selecting also can to comprise an interface layer (not shown) between grid layer 140 and grid layer 130d.It should be noted that for simplicity, in Figure 1B not shown go out dielectric layer 120a, 120b so that select the relation between grid layer 110,140 and grid layer 130a～130d clearer.NAND flash memory cell 100 also comprises electric charge capture layer 150 and conductive structure 160, and electric charge capture layer 150 and conductive structure 160 can run through and select grid layer 110,140, dielectric layer 120a, 120b and grid layer 130a～130d.It should be noted that and in Figure 1A and Figure 1B, only show 4 grid layer 130a～130d, but the present invention not subject to the limits.In other exemplary embodiment, NAND flash memory cell 100 can comprise the grid layer that number is more or less.
The material of dielectric layer 120a, 120b can comprise silica, phosphorosilicate glass (phosphosilicate glass, PSG) or other advanced low-k materials.Select the material of grid layer 110,140 and grid layer 130a～130d can comprise polysilicon or the metal through doping.In this exemplary embodiment, electric charge capture layer 150 is combined by multiple dielectric layer.For example, the material of electric charge capture layer 150 can comprise silica-silicon-nitride and silicon oxide composite bed.In another exemplary embodiment, above-mentioned silicon nitride also can be replaced into a layer of the poly floating grid (floating gate) through doping or other can be in order to the material in stored electrons or hole, and the present invention is also not subject to the limits.Conductive structure 160 can comprise metal or the polysilicon through doping.Specifically, a potential difference can be applied between the first end 172 and the second end 174 of conductive structure 160, in order to produce an electric current 176 in conductive structure 160.In this exemplary embodiment, first end 172 is drain electrode end, and the second end 174 is source terminal, that is to say, electric current 176 is to flow to drain electrode end from source terminal.But in other exemplary embodiment, first end 172 can be source terminal, the second end 174 can be drain electrode end; Or electric current 176 also can flow to source terminal from drain electrode end, the present invention is also not subject to the limits.Electric current 176 is to heat electric charge capture layer 150.In an exemplary embodiment, heating electric charge capture layer 150 can increase the useful life of NAND flash memory cell 100 or increase the speed of erase operation for use.Below will lift exemplary embodiment describes in detail again.
Fig. 1 C is the circuit diagram that NAND flash memory cell is shown according to an exemplary embodiment.
Please refer to Figure 1B and Fig. 1 C, select grid layer 110,140, grid layer 130a～130d, electric charge capture layer 150 can be regarded as transistor 180a～180f with the combination of conductive structure 160.Conductive structure 160 can comprise the passage of transistor 180a～180f.Select grid layer 110,140 respectively as the control grid of transistor 180a and 180f.Grid layer 130a～130d is the control grid as transistor 180b～180e.That is to say, select voltage on grid layer 110,140 and grid layer 130a～130d is whether control transistor 180a～180f be conducting.Transistor 180b～180e can be called as again memory cell (memory cell), and each memory cell can store one or more bit.
Fig. 2 is the part schematic diagram that NAND flash memory cell module is shown according to an exemplary embodiment.
NAND flash memory cell 100 can be included in a NAND flash module, and this NAND flash module also can comprise that other are similar to the structure of NAND flash memory cell 100.NAND flash memory cell 100 can be combined into a physical blocks with other similar structures, and NAND flash module can comprise multiple physical blocks.For example, as shown in Figure 2, NAND flash module 200 comprises NAND flash memory cell 100,210 and 220, its shared grid layer 130a～130d.In NAND flash memory cell 210 and 220, also can comprise conductive structure and electric charge capture layer.NAND flash memory cell 210 also comprises selects grid layer 212 and 214.NAND flash memory cell 220 also comprises selects grid layer 222 and 224.Conductive structure in NAND flash memory cell 100,210 and 220 can be used as bit line (bit line), and each grid layer 130a～130d can regard a character line (word line).It should be noted that the two ends up and down of NAND flash memory cell 100,210 and 220 also can be connected to other structure (for example, another conductor), or selecting grid layer 140,214,224 can be to be connected to each other, the present invention is also not subject to the limits.
[the first exemplary embodiment]
Fig. 3 is the top view that NAND flash memory cell 100 is shown according to the first exemplary embodiment.
Please refer to Fig. 3, in the first exemplary embodiment, electric charge capture layer 150 comprises silicon oxide layer 310, silicon nitride layer 320 and silicon oxide layer 330.The conductive structure 160 of Figure 1A and Figure 1B is channel layer 340 by implementation.The material of channel layer 340 comprises the polysilicon through doping.In this exemplary embodiment, channel layer 340 is by the n through doping
+type polysilicon is made.But channel layer 340 can be also by the p through doping
+type polysilicon is made, and the present invention is also not subject to the limits.
Fig. 4 illustrates the voltage schematic diagram while carrying out erase operation for use according to the first exemplary embodiment.
Please refer to Figure 1B and Fig. 4, in the time carrying out erase operation for use, the voltage of 0 volt can be applied on grid layer 130a～130d; (V
era-V
b2Bth) voltage of volt can be applied in and select on grid layer 110,140; (V
era+ Δ V) volt voltage can be applied in the second end 174; And (V
era-Δ V) voltage can be applied in first end 172.V
era,Δ V and V
b2Bthfor real number, but the present invention does not limit V
era, Δ V and V
b2Bthnumerical value.V
erathe voltage (being also referred to as the voltage of erasing) of (being for example 20) volt is the data (it is stored in electric charge capture layer 150) of erasing in NAND flash memory cell 100.And V
b2Bththe voltage (be also referred to as and wear voltage then) of volt is can interband tunneling effect (band to band tunneling effect) in order to produce.Specifically, the potential difference between first end 172 and selection grid layer 110 is approximately V
b2Bthvolt, makes electronics to move to first end 172 (or hole moves to and selects grid layer 110 from first end 172) from selection grid layer 110.Specifically, because a potential difference (2 Δ V) can be applied between the first end 172 and the second end 174 of channel layer 340, in channel layer 340, understand by this generation current with heating electric charge capture layer 150.Thus, can increase the speed of erase operation for use.In this exemplary embodiment, the voltage level of first end 172 is (V
era-Δ V) volt, and the voltage level of the second end 174 is (V
era+ Δ V) volt.But in other exemplary embodiment, the voltage level of first end 172 can be V
eravolt, and the voltage level of the second end 174 can be (V
era+ 2 Δ V) volt.Or the voltage level of first end 172 can be (V
era-2 Δ V) volt, and the voltage level of the second end 174 can be V
eravolt.The present invention does not limit and how to apply a current potential and be worse than between first end 172 and the second end 174.
In this exemplary embodiment, the level on grid layer 130a～130d is 0 volt.But in another exemplary embodiment, the level on grid layer 130a～130d can be a fiducial value, now select the level on the two ends of grid layer 110,140 and conductive structure 160 all can adjust according to this fiducial value, for example add this fiducial value.Suppose that at this this fiducial value is 3, therefore a reference voltage can be applied in grid layer 130a～130d, and the level of reference voltage is 3 volts.A tertiary voltage can be applied in selects grid layer 110,140, produce and the level of this tertiary voltage is according to the level of the level of reference voltage, the voltage of erasing and wear the level of voltage then, and be for example (3+V
era-V
b2Bth) volt.In addition, the level on the second end 174 is (3+V
era+ Δ V) volt, and level on first end 172 is (3+V
era-Δ V) volt.But this fiducial value can be real number arbitrarily, the present invention does not limit this fiducial value for how many.
Fig. 5 illustrates according to the first exemplary embodiment the voltage schematic diagram of repairing electric charge capture layer.
Please refer to Fig. 5, in an exemplary embodiment, V
passthe voltage (be also referred to as and pass through voltage) of volt can be applied in grid layer 130a～130d; V
ccthe voltage (being also referred to as system voltage) of volt can be applied in to be selected on grid layer 110 and 140; The voltage of 0 volt can be applied in the second end 174; And the voltage of Δ V volt can be applied in first end 172.V
passwith V
ccfor real number, for example, V
passbe 6.5 and V
ccbe 3, but the present invention does not limit V
passwith V
ccnumerical value.V
passthe voltage of volt is to allow the corresponding transistor turns of grid layer 130a～130d, and V
ccthe voltage of volt is to allow select grid layer 110,140 corresponding transistor turns.In this exemplary embodiment, if channel layer 340 is the n of doping
+type polysilicon or the p through adulterating
+type polysilicon is made, V
passthe voltage of volt can be 0.That is to say, whole channel layer 340 can be the state of conducting, and a potential difference can be applied between first end 172 and the second end 174 and heats electric charge capture layer 150 with generation current.In other words, the electric current in channel layer 340 can be produced in the time erasing, and also can produce in other any moment, and the present invention is also not subject to the limits.Thus, can repair electric charge capture layer 150, therefore allow data be not easy to lose (useful life that, increases NAND flash memory cell 100).
In the exemplary embodiment of Fig. 5, the level of the second end 174 is 0 volt, and the level of first end 172 is Δ V volts.But in other exemplary embodiment, the level of the second end 174 can be numerical value arbitrarily, and the level of first end 172 can be a different numerical value, therefore between first end 172 and the second end 174, produces potential difference.The present invention does not limit how to produce this potential difference.
[the second exemplary embodiment]
Fig. 6 A is the top view that NAND flash memory cell 600 is shown according to the second exemplary embodiment.Fig. 6 B illustrates in Fig. 6 A along the generalized section of the NAND flash memory cell 600 of P3-P4 section according to the second exemplary embodiment.
Please refer to Fig. 6 A and Fig. 6 B, in the second exemplary embodiment, electric charge capture layer 150 comprises silicon oxide layer 310, silicon nitride layer 320 and silicon oxide layer 330.Conductive structure 160 comprise channel layer 610, dielectric layer 620 (also claiming the second dielectric layer), with conductor layer 630.Channel layer 610 is to be disposed between dielectric layer 620 and silicon oxide layer 330, and dielectric layer 620 is to be configured between channel layer 610 and conductor layer 630.Channel layer 610, electric charge capture layer 150, selection grid layer 110,140 can be considered as multiple transistors that are connected in series each other with the combination of grid layer 130a～130d.In this exemplary embodiment, the first end 612 of channel layer 610 is drain electrode end, and the second end 614 is source terminal.But in other exemplary embodiment, first end 612 also can be source terminal, and the second end 614 can be drain electrode end, the present invention is also not subject to the limits.
The material of channel layer 610 comprises the combination of amorphous silicon, polysilicon, microcrystal silicon, monocrystalline silicon, nanocrystal silicon, oxide semiconductor material, organic semiconducting materials, other suitable material or above-mentioned at least two kinds of materials.In this exemplary embodiment, channel layer 610 is to be made up of N-shaped polysilicon.But channel layer 610 can be to be also made up of p-type polysilicon, the present invention is also not subject to the limits.The material of dielectric layer 620 comprises silica, phosphorosilicate glass (phosphosilicate glass, PSG) or other advanced low-k materials.And the material of conductor layer 630 can comprise metal or the polysilicon through doping.
Fig. 7 illustrates the voltage schematic diagram while carrying out erase operation for use according to the second exemplary embodiment.
Please refer to Fig. 6 B and Fig. 7, the voltage of 0 volt can be applied on grid layer 130a～130d.(V
era-V
b2Bth) volt voltage can be applied in select grid layer 110 and 140.V
erathe voltage of volt can be applied in first end 612 and the second end 614.Specifically, a potential difference can be applied between the two ends of conductor layer 630.For example, (V
era+ Δ V) volt voltage can be applied in the second end 634, (V
era-Δ V) volt voltage can be applied in first end 632.Thus, in the time carrying out erase operation for use, in conductor layer 630, can produce an electric current, electric charge capture layer 150 can be heated, therefore accelerate erase operation for use.But, in another exemplary embodiment, V
erathe voltage of volt can be applied in one of them of first end 612 and the second end 614, and the other end can be suspension joint (floating), and the present invention is also not subject to the limits.
With the first embodiment be similarly, level on grid layer 130a～130d can be a fiducial value, now select the level on grid layer 110,140, first end 614 and the second end 614 all can adjust according to this fiducial value, for example, add this fiducial value, at this, it is no longer repeated.In an exemplary embodiment, the level on first end 632 and the second end 634 also can be adjusted according to reference voltage (for example, adding fiducial value).That is to say, the level of first end 632 and the second end 634 is to produce according to the level of the level of the level of reference voltage, the voltage of erasing and offset voltage (voltage of Δ V volt), and wherein between first end 632 and the second end 634, existing is for example the potential difference of 2 Δ V volts.The present invention does not limit and how to apply a current potential and be worse than between first end 632 and the second end 634.
Fig. 8 illustrates according to the second exemplary embodiment the voltage schematic diagram of repairing electric charge capture layer.
Please refer to Fig. 8, grid layer 130a～130d, selection grid layer 110 and 140, first end 612 and the second end 614 can be by suspension joint (floating).In other words, the level of grid layer 130a～130d, selection grid layer 110 and 140, first end 612 and the second end 614 can be arbitrary value, and each other can be not identical.A potential difference can be applied between the two ends of conductor layer 630.For example, the voltage of 0 volt can be applied in the second end 634, and the voltage of Δ V volt can be applied in first end 632.In the same manner, the potential difference on conductor layer 630 two ends is to produce an electric current to heat electric charge capture layer 150.That is to say, electric charge capture layer 150 can the random time beyond erase operation for use be heated, and therefore allows data be not easy to lose.
In another exemplary embodiment, can the parameter using the level on first end 632 and the second end 634 as a function input, and this function can be exported a numerical value.The voltage that meets this numerical value can be applied in grid layer 130a～130d, select grid layer 110,140, first end 612 and the second end 614.The numerical value of this output can be between first end 632 and the level of the second end 634.For instance, the level of first end 632 is 5 volts, and the level of the second end 634 is 7 volts, and the numerical value of function output is 6.Thus, can avoid NAND flash memory cell 600 to enter the state of sequencing.But the numerical value that the present invention does not limit this output is how many.
In the exemplary embodiment of Fig. 8, the level of the second end 634 is 0 volt, and the level of first end 632 is Δ V volts.But in other exemplary embodiment, the level of the second end 634 can be numerical value arbitrarily, and the level of first end 632 can be a different numerical value, therefore between first end 632 and the second end 634, produces potential difference.The present invention does not limit how to produce this potential difference.
Fig. 9 illustrates according to the second exemplary embodiment the voltage schematic diagram that carries out read operation.
Please refer to Fig. 6 B and Fig. 9, will read the stored data of the corresponding transistor of grid layer 130a in this hypothesis.V
readthe voltage (be also referred to as and read voltage) of volt can be applied in grid layer 130a.V
passthe voltage of volt can be applied in grid layer 130b～130d.(V
cc+ V
t) volt voltage can be applied in select grid layer 110 and 140.The voltage of 0 volt can be applied in the second end 614.V
ccthe voltage of volt can be applied in first end 612.The voltage (also claiming the first voltage) of (V) volt can be applied in conductor layer 630.V
read, V
pass, V
cc, V
t, V is real number, but the present invention does not limit its value for how many.According to V
readnumerical value, the corresponding transistor of grid layer 130a may be switched on or not conducting.V
passvoltage be in order to the corresponding transistor of turn-on grid electrode layer 130b～130d.(V
cc+ V
t) voltage of volt is also to select grid layer 110 and 140 corresponding transistors in order to conducting.V
tbeing also referred to as critical level, can be V and select the level on grid layer 110,140
ccwith V
taddition.Therefore selecting the potential difference between grid layer 110 and first end 612 can be critical level V
tso, V
tto select the corresponding transistor of grid layer 110 in order to conducting.V
ccwhether the voltage of volt is to test the corresponding transistor of grid layer 130a to be switched on, and therefore reads data stored in this transistor.Specifically, first end 612 can first be precharged (pre-charge) to V
ccvolt (also claiming system level), grid layer 130b～130d with select grid layer 110 and 140 corresponding transistors all after conducting, if the voltage of first end 612 has decline, the corresponding transistor of expression grid layer 130a is switched on.In an exemplary embodiment, V
read, V
pass, V
ccfor just, and level on conductor layer 630 is (, the level of conductor layer 630 is less than the level of earth terminal (0V)) born with the numerical value of V.Thus, the electrons in channel layer 610, near grid layer 130a, therefore can increase the control ability of grid layer 130a.
In another exemplary embodiment, the material of channel layer 610 is P type polysilicon, reads the level (V of voltage
read) can be less than 0, and the level of the first voltage (V) can be greater than 0, therefore allows hole in channel layer 610 near grid layer 130a.In other words, be positive level if read the level of voltage, the level of the first voltage is negative level.If reading the level of voltage is negative level, the level of the first voltage is positive level (being greater than the voltage of earth terminal).
Figure 10 A is the schematic diagram that the upper voltage of grid layer 130a and electric current are shown according to the second exemplary embodiment.Figure 10 B illustrates according to the second exemplary embodiment the schematic diagram respectively distributing after memory cell is by sequencing.
The transverse axis of Figure 10 A is the level on grid layer 130a, and the longitudinal axis is the size of electric current in channel layer 610.The transverse axis of Figure 10 B is the critical voltage of a memory cell, and the longitudinal axis is number of memory cells.Please refer to Fig. 6 B, Figure 10 A and Figure 10 B, in a memory cell of this hypothesis, can store two bits.Therefore,, after the corresponding memory cell of grid 130a (transistor) is by sequencing, this transistorized critical voltage can be one of them of four distribution 1010a～1010d.For instance, distribution 1010a represents bit " 11 ", and distribution 1010d represents bit " 00 ".If this transistorized critical voltage is distribution 1010a, and level on grid layer 130a is while being level 1020, and this transistor can complete conducting, represents that the stored bit of this transistor is " 11 ".On the other hand, if the level on grid layer 130a is level 1022, this transistor meeting " part " conducting, on channel layer 610, the size of electric current can be the magnitude of current 1034.In an exemplary embodiment, the magnitude of current 1032 and the magnitude of current 1036 are for judging the whether critical value of conducting of transistor.For example, in the time that the electric current in channel layer 610 is greater than the magnitude of current 1032, represent that corresponding transistor is conducting.On the other hand, in the time that the electric current in channel layer 610 is less than the magnitude of current 1036, represent that corresponding transistor is not conducting.Therefore, can be used for distinguishing this transistor be to belong to which in distribution 1010a～1010d for the magnitude of current 1032 and the magnitude of current 1036.More easily being distinguished it when transistor is while belonging to which in distribution 1010a～1010d, represents that the control ability of grid layer 130a is better.
Figure 10 C illustrates according to the second exemplary embodiment the schematic diagram that promotes control ability.
Please refer to Figure 10 A, Figure 10 B and Figure 10 C, curve 1042 and 1044, as shown in Figure 10 A, is the voltage-to-current relation curve representing in the time that negative voltage is added in conductor layer 630.But 1052 and 1054 of curves are the voltage-to-current relation curves in the time not having negative voltage to be added in conductor layer 630.First, taking curve 1042 and 1044 as example, in the time that a transistor is turned to distribution 1010a by program, the magnitude of current 1032 is to correspond to level 1062; In the time that transistor is turned to distribution 1010b by program, the magnitude of current 1036 is to correspond to level 1064; That is to say, in interval 1072, can't judge transistor by accident is to belong to which distribution.Taking curve 1052 and 1054 as example, the magnitude of current 1032 is to correspond to level 1066, and the magnitude of current 1036 is corresponding to level 1068; In interval 1074, can't judge transistor by accident is to belong to which distribution.But from Figure 10 C, interval 1072 width can be greater than interval 1074 width.That is to say, after negative voltage is applied to conductor layer 630, more easily distinguishing transistor is which to belong to distribute, and the control ability of grid layer 130a can promote.
Figure 11 is the flow chart that read method is shown according to the second exemplary embodiment.
Please refer to Figure 11, each step of Figure 11 is the NAND flash memory cell for Fig. 6 A and Fig. 6 B.In step S1102, put on one of them of grid layer 130a～130d by reading voltage.In step S1104, except being applied in the grid layer that reads voltage, other grid layer will be put on by voltage in grid layer 130a～130d.In step S1106, the first voltage is put on to one end of conductor layer 630.The level that wherein reads voltage is one of them of positive level and negative level, and the level of the first voltage is wherein another of positive level and negative level.That is to say, be positive level if read the level of voltage, and the level of the first voltage is negative level (being less than the level of earth terminal).If reading the level of voltage is negative level, the level of the first voltage is positive level (being greater than the level of earth terminal).
In Figure 11, each step can implementation be multiple procedure codes and carry out these procedure codes by a processor.Or the each step of Figure 11 can implementation be one or more circuit, the present invention is also not subject to the limits.
On the other hand, the present invention's one exemplary embodiment also proposes a kind of method of operation, is for the first exemplary embodiment or the second exemplary embodiment.In this method of operation, a potential difference can be applied between the first end and the second end of conductive structure, in order to produce an electric current and in order to heat electric charge capture layer in conductive structure.But this method of operation has described in detail as above, just repeats no more at this.
In sum, the method for operation proposing in exemplary embodiment of the present invention, in read method and NAND flash memory cell, can heat electric charge capture layer and accelerate erase operation for use or repair electric charge capture layer.In addition,, in an exemplary embodiment, owing to being applied to voltage on conductor layer in contrast to reading voltage, therefore the control ability of grid layer also can be raised.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (21)
1. a NAND flash memory cell, is characterized in that, comprising:
Multiple grid layers, wherein comprise one first dielectric layer between adjacent two grid layers in those grid layers; And
One channel layer, runs through those grid layers;
One electric charge capture layer, runs through those grid layers, is configured between this channel layer and those grid layers;
One conductor layer, runs through those grid layers; And
One second dielectric layer, runs through those grid layers, and wherein this second dielectric layer is to be configured between this conductor layer and this channel layer.
2. NAND flash memory cell according to claim 1, is characterized in that, this electric charge capture layer comprises silica-silicon-nitride and silicon oxide composite bed.
3. NAND flash memory cell according to claim 1, is characterized in that, the material of this conductor layer comprises a metal.
4. NAND flash memory cell according to claim 1, is characterized in that, the material of this conductor layer comprises a doped polycrystalline silicon.
5. according to the NAND flash memory cell described in claim 1, it is characterized in that, also comprise:
One first selects grid layer, is configured in a side of those grid layers; And
One second selects grid layer, is configured in the opposite side of those grid layers, and wherein this channel layer, this electric charge capture layer, this conductor layer and this second dielectric layer run through this first selection grid layer and this second selection grid layer.
6. NAND flash memory cell according to claim 1, is characterized in that, the material of this channel layer comprises amorphous silicon, polysilicon, microcrystal silicon, monocrystalline silicon, nanocrystal silicon, oxide semiconductor material, organic semiconducting materials or its combination.
7. for a read method for NAND flash memory cell as claimed in claim 1, it is characterized in that, comprising:
Read voltage and put on one of them of those grid layers by one;
Put on wherein another of those grid layers by one by voltage;
One first voltage is put on to a side of this conductor layer,
Wherein this level that reads voltage be a positive level and a negative level one of them, and the level of this first voltage is wherein another of this positive level and this negative level.
8. according to the read method described in claims 7, it is characterized in that, this NAND flash memory cell also comprises:
One first selects grid layer, is configured in a side of those grid layers; And
One second selects grid layer, is configured in the opposite side of those grid layers, and wherein this channel layer, this electric charge capture layer, this conductor layer and this second dielectric layer run through this first selection grid layer and this second selection grid layer,
Wherein this read method also comprises:
One second voltage is put on to this first selection grid layer and this second selection grid layer, and wherein the level of this second voltage is the addition of a system level and a critical level.
9. according to the read method described in claims 8, it is characterized in that, also comprise:
One first end of this channel layer of precharge is to this system level; And
Whether have decline according to the level of this first end of this channel layer, judgement is applied in the whether conducting of the corresponding transistor of this this grid layer that reads voltage.
10. the method for operation of a NAND flash memory cell, it is characterized in that, this NAND flash memory cell comprises multiple grid layers, a conductive structure and an electric charge capture layer, this conductive structure and this electric charge capture layer run through those grid layers, and this electric charge capture layer is to be configured between this conductive structure and those grid layers, and this method of operation comprises:
One potential difference is applied between a first end of this conductive structure and one second end of this conductive structure, in order to produce an electric current and in order to heat this electric charge capture layer in this conductive structure.
11. methods of operation according to claim 10, is characterized in that, the material of this conductive structure is doped polycrystalline silicon.
12. methods of operation according to claim 11, is characterized in that, the step this potential difference being applied between this second end of this first end of this conductive structure also comprises:
One voltage of erasing is applied on this conductive structure.
13. methods of operation according to claim 12, is characterized in that, this NAND flash memory cell also comprises:
One first selects grid layer, is configured in a side of those grid layers; And
One second selects grid layer, is configured in the opposite side of those grid layers, and wherein this conductive structure and this electric charge capture layer run through this first selection grid layer and this second selection grid layer,
Wherein this method of operation also comprises:
One reference voltage is put on to those grid layers; And:
One tertiary voltage is put on to this and first selects grid layer and this second to select grid layer, wherein the level of this tertiary voltage be according to the level of the level of this reference voltage, this voltage of erasing, with one wear and satisfy the level of voltage and produce.
14. methods of operation according to claim 11, it is characterized in that, this NAND flash memory cell also comprises that one first selects grid and one second to select grid, this the first selection grid layer is a side that is configured in those grid layers, this the second selection grid layer is the opposite side that is configured in those grid layers, and this conductive structure and this electric charge capture layer run through this first selects grid layer and this second selection grid layer, and the step wherein this potential difference being applied between this second end of this first end of this conductive structure also comprises:
One system voltage is applied to this first selection grid layer and this second selection grid layer; And
Be applied on these grid layers by voltage one.
15. methods of operation according to claim 10, it is characterized in that, in those grid layers, between adjacent two grid layers, comprise one first dielectric layer, this conductive structure comprises a channel layer, a conductor layer and one second dielectric layer, this second dielectric layer is to be disposed between this channel layer and this conductor layer, this first end of this conductive structure and this second end are a first end and one second ends that is positioned at this conductor layer
Wherein this NAND flash memory cell also comprises:
One first selects grid layer, is configured in a side of those grid layers; And
One second selects grid layer, is configured in the opposite side of those grid layers, and wherein this channel layer, this conductor layer, this second dielectric layer and this electric charge capture layer run through this first selection grid layer and this second selection grid layer.
16. methods of operation according to claim 15, is characterized in that, also comprise:
One voltage of erasing is put on to one end of this channel layer;
One reference voltage is put on to those grid layers; And
One tertiary voltage is put on to this and first selects grid layer and this second to select grid layer, wherein the level of this tertiary voltage be according to the level of the level of this reference voltage, this voltage of erasing, with one wear and satisfy the level of voltage and produce.
17. methods of operation according to claim 16, it is characterized in that, this first end of this conductor layer and the level of this second end are to produce according to the level of the level of the level of this reference voltage, this voltage of erasing and an offset voltage, and have this potential difference between this first end of this conductor layer and this second end.
18. methods of operation according to claim 15, is characterized in that, also comprise:
By those grid layers, this first selection grid layer, this second selection grid layer, a first end of this channel layer and one second end suspension joint of this channel layer.
19. methods of operation according to claim 15, is characterized in that, also comprise:
Parameter input using the level of this first end of this conductor layer and this second end as a function, wherein this function is exported a numerical value, and this numerical value is between this first end of this conductor layer and the level of this second end;
The voltage that meets this numerical value is put on to those grid layers, this first selection grid layer, this second selection grid layer, a first end of this channel layer and one second end of this channel layer.
20. methods of operation according to claim 15, is characterized in that, the material of this conductor layer comprises a metal.
21. methods of operation according to claim 15, is characterized in that, the material of this conductor layer comprises a doped polycrystalline silicon.
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