CN104103590A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104103590A CN104103590A CN201310130298.3A CN201310130298A CN104103590A CN 104103590 A CN104103590 A CN 104103590A CN 201310130298 A CN201310130298 A CN 201310130298A CN 104103590 A CN104103590 A CN 104103590A
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- oxide layer
- silicon oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
The invention provides a semiconductor device manufacturing method. The method comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate comprises a PMOS region and an NMOS region; a PMOS gate is formed on the PMOS region; a first silicon oxide layer is formed on the side wall of the PMOS gate; a first silicon nitride layer is formed on the first silicon oxide layer; a second silicon oxide layer is formed on the first silicon nitride layer; a second silicon nitride layer is formed on the second silicon oxide layer; etching is carried out in the PMOS region to for a depression; a SiGe stress layer is formed in the depression; and the second silicon oxide layer and the second silicon nitride layer are removed, wherein the thickness of the first silicon oxide layer is greater than 40 angstrom. In the semiconductor device manufacturing method provided by the invention, the thickness of the first silicon oxide layer is increased, the SiGe stress layer can be ensured not to be exposed during the technological process, reaction between the SiGe stress layer and a stripping liquid can be avoided and the SiGe stress layer can be prevented from being damaged.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of semiconductor device.
Background technology
Along with day by day dwindling of dimensions of semiconductor devices, rely on the method for traditional attenuate gate oxide thickness can not meet growth requirement.So people have to improve device performance by other method, such as stress strengthens technology.Stress enhancing technology, by channel region stress application, improves the mobility of charge carrier.At present, in semiconductor manufacture, adopt germanium silicon (SiGe) as compression material, to improve the performance of PMOS.Common way is to replace traditional silicon (Si) with germanium silicon (SiGe), in source/drain region of PMOS, by selective epitaxial growth, forms germanium silicon (SiGe) stressor layers.
Germanium silicon (SiGe) is the semiconductor alloy material that silicon (Si) and germanium (Ge) form, and wherein, the atomic radius of germanium (Ge) is larger than the atom of silicon (Si), and after germanium (Ge) mixes in silicon (Si), source-drain area can produce compression.For raceway groove, can be subject to the impact of compression.The hole of PMOS is under the effect of compression, and mobility can be accelerated greatly, thereby improves device performance.Along with the development of germanium silicon (SiGe) technology, in germanium silicon (SiGe), the content of germanium (Ge) also improves thereupon.Germanium (Ge) content of the germanium silicon (SiGe) that integrated circuit adopts in manufacturing is also more and more higher, and germanium (Ge) content of currently used germanium silicon (SiGe) surpasses 40%.
But, in fabrication of semiconductor device, find, often there is damage in various degree in germanium silicon (SiGe) stressor layers of selective epitaxial growth, germanium (Ge) content in germanium silicon (SiGe) stressor layers is higher, and the damage of germanium silicon (SiGe) stressor layers is more serious.Once germanium silicon (SiGe) stressor layers is damaged, and can make the stress in raceway groove weaken, and affects transistorized performance.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of semiconductor device, to solve the problem of existing semiconductor device germanium silicon stressor layers damage in manufacture process.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of semiconductor device, the manufacture method of described semiconductor device comprises the following steps:
Semiconductor substrate is provided, and described Semiconductor substrate comprises PMOS region and territory, nmos area, and described PMOS is formed with PMOS grid on region;
On the sidewall of described PMOS grid, form the first silicon oxide layer;
On described the first silica, form the first silicon nitride layer;
On described the first silicon nitride layer, form the second silicon oxide layer;
On described the second silicon oxide layer, form the second silicon nitride layer;
In described PMOS region, form depression, in described depression, form germanium silicon stressor layers;
Remove the second silicon oxide layer and the second silicon nitride layer;
Wherein, the thickness of described the first silicon oxide layer is greater than 40 dusts.
Preferably, in the manufacture method of described semiconductor device, described the first silicon oxide layer comprises several silica sublayers, and the quantity of silica sublayer is 2 layers or 3 layers.
Preferably, in the manufacture method of described semiconductor device, described the first silicon oxide layer comprises two-layer silica sublayer, wherein, thick than the silica sublayer of close PMOS grid away from the silica sublayer of PMOS grid.
Preferably, in the manufacture method of described semiconductor device, near the thickness of the silica sublayer of PMOS grid, be 20 dust～30 dusts, away from the thickness of the silica sublayer of PMOS grid, be 20 dust～50 dusts.
Preferably, in the manufacture method of described semiconductor device, described the first silicon oxide layer forms by thermal oxidation and chemical vapor deposition method.
Preferably, in the manufacture method of described semiconductor device, described germanium silicon stressor layers forms by epitaxial growth technology.
Preferably, in the manufacture method of described semiconductor device, further comprise: after forming described germanium silicon stressor layers, in described germanium silicon stressor layers, form cap layer.
Preferably, in the manufacture method of described semiconductor device, further comprise: after removing the second silicon oxide layer, carry out LDD and inject.
Preferably, in the manufacture method of described semiconductor device, the material that described PMOS grid adopts is amorphous silicon.
Inventor finds, cause the germanium silicon stressor layers damage reason of existing semiconductor device to be, in manufacture process, repeatedly use stripper, the silicon oxide layer hiding in stripper corrosion germanium silicon (SiGe) stressor layers, germanium silicon (SiGe) stressor layers is directly come out, germanium silicon (SiGe) stressor layers can with subsequent technique in stripper react, cause germanium silicon (SiGe) stressor layers damage.In the manufacture method of semiconductor device provided by the invention, increased the thickness of the first silicon oxide layer, can guarantee can not expose in technical process germanium silicon (SiGe) stressor layers, and then avoid germanium silicon (SiGe) stressor layers and stripper to react, cause the damage of germanium silicon (SiGe) stressor layers.
Accompanying drawing explanation
Fig. 1 is the structural representation of semiconductor device after germanium and silicon epitaxial growth in prior art;
Fig. 2 is the structural representation of semiconductor device after LDD injects in prior art;
Fig. 3 is the process chart of manufacture method of the semiconductor device of the embodiment of the present invention;
Fig. 4 is the semiconductor device of the embodiment of the present invention structural representation after germanium and silicon epitaxial growth;
Fig. 5 is the semiconductor device of the embodiment of the present invention structural representation after LDD injects.
Embodiment
The manufacture method of semiconductor device the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
In the manufacture process of existing semiconductor device, germanium silicon stressor layers is impaired, causes device performance to decline.Inventor conducts in-depth research this, discovery causes existing semiconductor device impaired reason of germanium silicon stressor layers in manufacture process to be, after semiconductor device forms germanium silicon (SiGe) stressor layers, also need to peel off through acid solution repeatedly, in acid solution stripping process, stripper corrodes the silicon oxide layer in germanium silicon (SiGe) stressor layers gradually, germanium silicon (SiGe) stressor layers is come out directly to be contacted with stripper, stripper and germanium silicon (SiGe) react, and cause the damage of germanium silicon (SiGe) stressor layers.
Please refer to Fig. 1, it is the structural representation of semiconductor device after germanium and silicon epitaxial growth in prior art, and as shown in Figure 1, Semiconductor substrate comprises PMOS region and territory, nmos area, is formed with PMOS grid 10 on PMOS region.The first silicon oxide layer 11 and the first silicon nitride layer 12 on the sidewall of PMOS grid 10, have been formed successively, the second silicon oxide layer 13 and the second silicon nitride layer 14 on the first silicon nitride layer 12, have been formed successively afterwards, wherein, the thickness of the first silicon oxide layer 11 is generally 20 dust～30 dusts.Afterwards, in PMOS region, by etching, form depression, in depression, by selective epitaxial growth, formed germanium silicon (SiGe) stressor layers 15.After forming germanium silicon (SiGe) stressor layers 15, in described germanium silicon stressor layers 15, form cap layer 16, described cap layer 16 and the first silicon oxide layer 11 hide on germanium silicon (SiGe) stressor layers 15.
Then, remove successively the second silicon nitride layer 14 and the second silicon oxide layer 13.While removing the second silicon nitride layer 14, need to use high temperature phosphoric acid (H
3pO
4) and standard cleaning liquid (SC1), high temperature phosphoric acid (H
3pO
4) and standard cleaning liquid (SC1) the first silicon oxide layer 11 and the second silicon oxide layer 13 that can corrosion germanium silicon (SiGe) stressor layers 15 hide above, germanium silicon (SiGe) stressor layers 10 is come out.While removing the second silicon oxide layer 13 with the hydrofluoric acid (HF) diluting and standard cleaning liquid (SC1) afterwards, germanium silicon (SiGe) stressor layers 15 will directly contact hydrofluoric acid (HF) and standard cleaning liquid (SC1), and react with hydrofluoric acid (HF) and standard cleaning liquid (SC1), corrode.
After removing the second silicon nitride layer 14 and the second silicon oxide layer 13, carry out LDD injection technology.In LDD injection technology, can adopt SPM or Ozone Water (DIO3) and standard cleaning liquid (SC1) to remove photoresist, now germanium silicon (SiGe) stressor layers 10 also can be reacted with stripper, causes germanium silicon (SiGe) stressor layers 15 further to be damaged.As shown in Figure 2, after LDD injects, germanium silicon (SiGe) stressor layers 15 of close cap layer 16 both sides has been corroded.
In order to address the above problem, the application has proposed following technical scheme:
Please refer to Fig. 3, it is the process chart of the manufacture method of embodiment of the present invention semiconductor device.As shown in Figure 3, the manufacture method of described semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises PMOS region and territory, nmos area, and described PMOS is formed with PMOS grid 20 on region;
On the sidewall of described PMOS grid 20, form the first silicon oxide layer 21;
On described the first silicon oxide layer, form the first silicon nitride layer 22;
On described the first silicon nitride layer 22, form the second silicon oxide layer 23;
On described the second silicon oxide layer 23, form the second silicon nitride layer 24;
In described PMOS region, form depression, in described depression, form germanium silicon stressor layers 25;
Remove the second silicon oxide layer 23 and the second silicon nitride layer 24;
Wherein, the thickness of described the first silicon oxide layer is greater than 40 dusts.
Concrete, Semiconductor substrate comprises PMOS region and territory, nmos area, is formed with PMOS grid 20 on PMOS region, the material that PMOS grid 20 adopts is amorphous silicon.First, on the sidewall of PMOS grid 20, by thermal oxidation and chemical vapor deposition method, form the first silicon oxide layer 21, the defect causing to repair amorphous etching.Then, on the first silicon oxide layer 21, form the first silicon nitride layer 22, on the first silicon nitride layer 22, form the second silicon oxide layer 23, on the second silicon oxide layer 23, form the second silicon nitride layer 24.Afterwards, in described PMOS region etching, form depression, by selective epitaxial growth process, in depression, form germanium silicon (SiGe) stressor layers 25.Finally, remove successively the second silicon nitride layer 24 and the second silicon oxide layer 23.
Wherein, the first silicon oxide layer 21 comprises several silica sublayers, preferably 2 layers or 3 layers of the quantity of silica sublayer.In the present embodiment, the first silicon oxide layer 21 comprises two-layer silica sublayer, concrete, comprise ground floor silica sublayer 30 and second layer silica sublayer 40, wherein, described ground floor silica sublayer 30 is formed on the sidewall of described PMOS grid 20, and thickness is 20 dust～30 dusts.Described second layer silica sublayer 40 is formed on described ground floor silica sublayer 30, and thickness is 20 dust～50 dusts.Visible, second layer silica sublayer 40 is thicker than ground floor silica sublayer 30, and the thickness of the first silicon oxide layer 21 surpasses 40 dusts.
The formation technique of the first silicon oxide layer 21 can adopt any prior art well known to those skilled in the art, preferably thermal oxidation and chemical vapor deposition method.In the present embodiment, ground floor silica sublayer 30 adopts identical technique with second layer silica sublayer 40, all by thermal oxidation and chemical vapor deposition method, forms.
In other embodiments of the invention, the first silicon oxide layer 21 can be independent one deck silicon oxide layer, also can comprise more multi-layered silica sublayer, for example, comprises three layers of silica sublayer, four layers of silica sublayer or five layers of silica sublayer.As long as the thickness of the first silicon oxide layer 21 is enough thick, surpass 40 dusts.
The manufacture method of the semiconductor device providing in the embodiment of the present invention further comprises: after forming described germanium silicon stressor layers 25, in described germanium silicon stressor layers 25, form cap layer 26.After forming cap layer 26, by wet etching mode, remove successively the second silicon nitride layer 24 and the second silicon oxide layer 23.Wherein, the stripper adopting while removing the second silicon nitride layer 24 is the H3PO4 of 150 ℃ to 170 ℃ and the standard cleaning liquid SC1 of 30 ℃ to 40 ℃, wherein, the component ratio of standard cleaning liquid SC1 is 1 part of ammoniacal liquor, the hydrogen peroxide of 1 to 4 times, the water of 5 to 200 times, about 2～5 minutes of splitting time.The stripper of removing the second silicon oxide layer 23 is hydrofluoric acid (HF) and the standard cleaning liquid SC1 of dilution, about 2～5 minutes of splitting time.
The manufacture method of the semiconductor device providing in the embodiment of the present invention further comprises: after removing the second silicon oxide layer 23, carry out LDD and inject.In LDD injection technology process, adopt the standard cleaning liquid SC1 of the SPM of 120 ℃～130 ℃ or Ozone Water (DIO3) and 30 ℃～40 ℃ to remove photoresist, wherein, the component ratio of SPM is 1 part of hydrogen peroxide, the sulfuric acid of 5 to 6 times, and splitting time is 2～5 minutes.
Then, complete the manufacture of whole semiconductor device by subsequent technique, subsequent technique is identical with traditional technique.
Please continue to refer to Fig. 4, it is the semiconductor device of the embodiment of the present invention structural representation after germanium and silicon epitaxial growth, as shown in Figure 4, the first silicon oxide layer 21, the first silicon nitride layer 22, the second silicon oxide layer 23 and the second silicon nitride layer 24 on the sidewall of PMOS grid 20, have been formed successively.Wherein, the first silicon oxide layer 21 is comprised of ground floor silica sublayer 30 and second layer silica sublayer 40, and the thickness of the first silica sublayer 30 is 20 dust～30 dusts, and the thickness of second layer silica sublayer 40 is 20 dust～50 dusts.As can be seen here, the thickness of the first silicon oxide layer 21 is 40 dust～80 dusts.General 20 dust～30 dusts of the first silicon oxide layer 11 thickness in prior art on PMOS grid 10 sidewalls, and the thickness of the first silicon oxide layer 21 on PMOS grid 20 sidewalls is 40 dust～80 dusts in the embodiment of the present invention, the thickness that hides the first silicon oxide layer 21 in germanium silicon (SiGe) stressor layers 25 has increased greatly.
During the second silicon nitride layer 24 wet etching, high temperature phosphoric acid ((H
3pO
4although) and standard cleaning liquid SC1 can react with the first silicon oxide layer 21, because the first silicon oxide layer 21 is thicker, can not exposed germanium silicon (SiGe) stressor layers 25 by corrosion completely.Wet-cleaned in follow-up the second silicon oxide layer 23 wet etchings and LDD injection technology, can not corrode the first silicon oxide layer 21 completely yet.Please continue to refer to Fig. 5; it is the semiconductor device of the embodiment of the present invention structural representation after LDD injects; as shown in Figure 5; after LDD injection technology completes; the first silicon oxide layer 21 still cover germanium silicon (SiGe) stressor layers 25 above; cap layer 26 and the first silicon oxide layer 21 can be protected germanium silicon (SiGe) stressor layers 25, and it is not contacted with stripper.
To sum up, in the manufacture method of the semiconductor device providing in the embodiment of the present invention, the silicon oxide layer of covering in germanium silicon (SiGe) stressor layers is thicker, silicon oxide layer described in technical process can not corroded completely, and then avoid germanium silicon (SiGe) stressor layers to come out reacting with stripper, cause the damage of germanium silicon (SiGe) stressor layers, thereby improved the performance of semiconductor device.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (9)
1. a manufacture method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises PMOS region and territory, nmos area, and described PMOS is formed with PMOS grid on region;
On the sidewall of described PMOS grid, form the first silicon oxide layer;
On described the first silica, form the first silicon nitride layer;
On described the first silicon nitride layer, form the second silicon oxide layer;
On described the second silicon oxide layer, form the second silicon nitride layer;
In described PMOS region, form depression, in described depression, form germanium silicon stressor layers;
Remove the second silicon oxide layer and the second silicon nitride layer;
Wherein, the thickness of described the first silicon oxide layer is greater than 40 dusts.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described the first silicon oxide layer comprises several silica sublayers, and the quantity of silica sublayer is 2 layers or 3 layers.
3. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, described the first silicon oxide layer comprises two-layer silica sublayer, wherein, thick than the silica sublayer of close PMOS grid away from the silica sublayer of PMOS grid.
4. the manufacture method of semiconductor device as claimed in claim 3, is characterized in that, near the thickness of the silica sublayer of PMOS grid, is 20 dust～30 dusts, away from the thickness of the silica sublayer of PMOS grid, is 20 dust～50 dusts.
5. the manufacture method of the semiconductor device as described in claim 1 to 4 any one, is characterized in that, described the first silicon oxide layer forms by thermal oxidation and chemical vapor deposition method.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described germanium silicon stressor layers forms by epitaxial growth technology.
7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, further comprises: after forming described germanium silicon stressor layers, in described germanium silicon stressor layers, form cap layer.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, further comprises: after removing the second silicon oxide layer, carry out LDD and inject.
9. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the material that described PMOS grid adopts is amorphous silicon.
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| WO2022227324A1 (en) * | 2021-04-30 | 2022-11-03 | 长鑫存储技术有限公司 | Semiconductor device and fabrication method therefor |
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