CN104103575B - The forming method of copper interconnecting line - Google Patents
The forming method of copper interconnecting line Download PDFInfo
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- CN104103575B CN104103575B CN201310124031.3A CN201310124031A CN104103575B CN 104103575 B CN104103575 B CN 104103575B CN 201310124031 A CN201310124031 A CN 201310124031A CN 104103575 B CN104103575 B CN 104103575B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
Abstract
The invention discloses a kind of forming method of copper interconnecting line, including：Substrate is provided；Multiple spaced figures are formed on substrate, the first figure is comprised at least in multiple figures；Interconnection line layer of feed stock material is formed on substrate and figure；Interconnection line layer of feed stock material carve, side wall is formed in the both sides of figure, the first figure is then removed successively, carries out quick thermal annealing process so as to form copper interconnecting line；Or quick thermal annealing process is carried out so that the material of interconnection line layer of feed stock material is converted into copper metal layer, copper metal layer carve, the remaining copper metal layer composition copper interconnecting line of figure both sides, then removes the first figure.This method can utilize SADP and make annealing treatment technology forms copper interconnecting line in the both sides of figure, and the spacing being smaller than between figure between copper interconnecting line, the spacing between copper interconnecting line is set no longer to be limited and can not further reduced by photoetching process, and copper interconnecting line density is improved.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of forming method of copper interconnecting line.
Background technology
With the development of semiconductor technology, the integrated level of VLSI chip is up to several hundred million or even tens
The scale of hundred million devices, more than two layers of multiple layer metal interconnection technique widely use.Traditional metal interconnecting wires are by aluminum metal
It is made, but with the continuous diminution of device feature size in IC chip, the current density in metal interconnection structure is continuous
Increase, it is desirable to response time constantly reduce, traditional aluminum interconnecting can not meet to require, process be less than 130nm with
Afterwards, copper interconnection technology instead of aluminium interconnection technique.Compared with aluminium, the resistivity of copper is lower, and copper interconnecting line can reduce mutually
The resistance capacitance of line（RC）Delay, improve electromigration, improve the reliability of device.
A kind of existing forming method of copper interconnecting line is briefly described with reference to Fig. 1 to Fig. 3：
As shown in Figure 1, there is provided Semiconductor substrate 1, formed with dielectric layer 2 in Semiconductor substrate 1, formed on dielectric layer 2
Graphical photoresist layer 3, it is that mask performs etching to dielectric layer 2 with graphical photoresist layer 3, it is more to be formed in dielectric layer 2
Individual groove 4（In figure by taking two grooves as an example）.
With reference to shown in Fig. 1 and Fig. 2, graphical photoresist layer 3 is removed, copper metal layer 5, copper metal are formed on dielectric layer 2
Layer 5 fills up groove 4.
With reference to shown in Fig. 2 and Fig. 3, cmp is carried out to copper metal layer 5（CMP）Processing, to remove unnecessary copper
Metal level 5, form copper interconnecting line 6.
From the foregoing, be that groove 4 is first formed in the dielectric layer 2 in the forming method of existing copper interconnecting line, then again to
Filling copper metal layer in groove 4, to form copper interconnecting line 6.Wherein, the position on semiconductor substrate 1 of groove 4 and width dimensions
W is defined using graphical photoresist layer 3, the spacing between two neighboring groove 4（Equal to groove width with it is two neighboring
Dielectric layer width sum between groove）Size can be used as judging the standard of lithographic capabilities.Due to the limitation of factors,
Forming groove using photoetching process has minimum spacing（minimum pitch）.But with integrated circuit to size more
Direction small, that density is higher is developed, and photoetching process can limit the further diminution of spacing between two neighboring groove, thus limit
The further diminution of spacing, also limit the further diminution of copper interconnecting line density between two neighboring copper interconnecting line.
The content of the invention
It is an object of the invention to provide a kind of forming method of copper interconnecting line, this method can further reduce two neighboring copper
Spacing, the density of raising copper interconnecting line between interconnection line.
To reach above-mentioned purpose, the invention provides a kind of forming method of copper interconnecting line, including：
Semiconductor substrate is provided；
Multiple spaced figures are formed over the substrate, and first figure is comprised at least in multiple figures
Shape；
Interconnection line layer of feed stock material is formed on the substrate and figure, the material of the interconnection line layer of feed stock material is the change of copper
Compound；
The interconnection line layer of feed stock material carve, side wall is formed in the both sides of the figure, then removes described the
One figure, quick thermal annealing process is carried out, the quick thermal annealing process makes the material of the side wall be converted into copper so as to be formed
Copper interconnecting line；
Or quick thermal annealing process is carried out so that the material of the interconnection line layer of feed stock material is converted into copper metal layer, it is right
The copper metal layer carve, and the remaining copper metal layer of the figure both sides forms copper interconnecting line, then removes described first
Figure.
Optionally, multiple figures are first figure.
Optionally, also include at least one second graph in multiple figures, the material of first figure with it is described
The material of second graph differs, and the material of the second graph is the compound of copper or the copper；When the second graph
When material is the compound of copper, the quick thermal annealing process makes the material of the second graph be converted to copper.
Optionally, the substrate includes the first dielectric layer positioned at surface, links in first dielectric layer formed with mutual
Structure；The copper interconnecting line is located on the first dielectric layer.
Optionally, formed and be provided with barrier layer between the copper interconnecting line and the first dielectric layer of the first figure both sides.
Optionally, forming the method for multiple spaced figures over the substrate includes：
The second dielectric layer is formed over the substrate；
Graphical photoresist layer is formed on second dielectric layer；
Second dielectric layer is performed etching as mask using the graphical photoresist layer, in second dielectric layer
A groove is at least formed, the groove exposes the first dielectric layer；
After removing the graphical photoresist layer, second graph material layer is filled into the groove, with described in formation
Second graph；
Form the second graph and remove second dielectric layer afterwards；
After removing second dielectric layer, the first graphic material is formed on first dielectric layer and second graph
Layer, the first graphic material layer surface flush with the second graph surface；
Processing is patterned to the first graphic material layer, forms first figure.
Optionally, forming the method for multiple spaced figures over the substrate includes：
The barrier layer, the second dielectric layer on barrier layer are formed on first dielectric layer, is situated between positioned at second
Graphical photoresist layer in electric layer；
Second dielectric layer and barrier layer are performed etching as mask using the graphical photoresist layer, with described the
A groove is at least formed in two dielectric layers and barrier layer, the groove exposes first dielectric layer；
After removing the graphical photoresist layer, second graph material layer is filled into the groove, with described in formation
Second graph；
Form the second graph and remove second dielectric layer afterwards；
After removing second dielectric layer, the first graphic material layer, institute are formed on the barrier layer and second graph
The first graphic material layer surface is stated to flush with the second graph surface；
Processing is patterned to the first graphic material layer, to form first figure.
Optionally, the material on the barrier layer comprises at least one kind in SiN, SiC, SiCN.
Optionally, it is described to remove first figure, carry out in the step of quick thermal annealing process, first remove described first
Figure, quick thermal annealing process is carried out again；Or first carry out quick thermal annealing process, remove first figure again.
Optionally, the material of first figure is photoresist or amorphous carbon.
Optionally, the interconnection line layer of feed stock material is formed using Atomic layer deposition method.
Optionally, the compound of the copper is copper nitride.
Optionally, the quick thermal annealing process is carried out in vacuum environment, and annealing temperature is 100 DEG C -300 DEG C, is moved back
The fiery time is 5min-1h.
Optionally, the quick thermal annealing process is to carry out in the hydrogen gas atmosphere, and parameter and annealing includes：Annealing temperature
For 150 DEG C -300 DEG C, annealing time 5min-30min, pressure 1Torr-10Torr.
Optionally, the annealing is carried out in the mixed-gas environment of hydrogen and inert gas, annealing process ginseng
Number includes：Annealing temperature is 150 DEG C -300 DEG C, annealing time 5min-30min, pressure 1Torr-10Torr.
Compared with prior art, the present invention has advantages below：
By forming multiple spaced figures on substrate, the change that material is copper is then formed on substrate and figure
The interconnection line layer of feed stock material of compound, then carry out quick thermal annealing process and return to carve, make the step of the quick thermal annealing process
The material of interconnection line layer of feed stock material is converted into copper, cause to form side wall in the both sides of figure the step of quarter for described time, so as to
The both sides of figure are respectively formed copper interconnecting line.Therefore, present invention comprehensive utilization SADP（self-aligned double pattern）
Copper interconnecting line is formed with quick thermal annealing process technology, overcomes the spacing between two neighboring copper interconnecting line in the prior art
The defects of being limited and can not further being reduced by photoetching process, and make formed copper interconnecting line density be the two of pattern density
Again, the density of copper interconnecting line is improved.
Further, the present invention another technical scheme in, in multiple figures in Semiconductor substrate except including
Outside first figure, in addition to second graph, so, copper-connection can be respectively formed in the both sides of the first figure and second graph simultaneously
Line.If the copper interconnecting line of the first figure both sides is the first copper interconnecting line, when the material of second graph is copper, second graph
The second copper interconnecting line is collectively formed with the copper interconnecting line of second graph both sides；When the material of second graph is the compound of copper,
During carrying out quick thermal annealing process to interconnection line layer of feed stock material, the material of second graph can be converted into copper simultaneously, this
Sample, the copper interconnecting line of second graph and second graph both sides after annealing collectively form the second copper interconnecting line.Therefore, utilize
The technical scheme can form the copper interconnecting line that width differs simultaneously, and it is mutual to be more than the first bronze medal for the specially width of the second copper interconnecting line
The width of line, to adapt to the demand of some semiconductor device applications.
Further, when the interconnection line layer of feed stock material is using Atomic layer deposition method formation so that interconnection line is former
Material layer has preferable Step Coverage ability, and then the width of copper interconnecting line is well controlled.
Brief description of the drawings
Fig. 1 to Fig. 3 be in a kind of existing copper interconnecting line forming method copper interconnecting line in the profile of each production phase；
Fig. 4 to Figure 10 be in embodiments of the invention one copper interconnecting line in the profile of each production phase；
Figure 11 to Figure 12 be in embodiments of the invention two copper interconnecting line in the profile of each production phase；
Figure 13 to Figure 23 be in embodiments of the invention three copper interconnecting line in the profile of each production phase；
Figure 24 to Figure 25 be in embodiments of the invention four copper interconnecting line in the profile of each production phase；
Figure 26 to Figure 35 be in embodiments of the invention five copper interconnecting line in the profile of each production phase；
Figure 36 to Figure 37 be in embodiments of the invention six copper interconnecting line in the profile of each production phase.
Embodiment
Due to SADP technologies have further reduce between two neighboring figure spacing, improve figure density it is excellent
Point, in consideration of it, inventor considers further to be reduced the spacing between two neighboring copper interconnecting line using SADP technologies, improved copper
The density of interconnection line, specific scenario are as follows：Multiple spaced figures are formed on substrate；On substrate and figure
Copper metal layer is formed, and copper metal layer is covered in the side wall and top of figure；Copper metal layer carve, it is remaining
Positioned at figure both sides copper metal layer form copper interconnecting line, thus come reduce the spacing between two neighboring copper interconnecting line, improve
The density of copper interconnecting line.
But found during actual fabrication, the method for existing deposited copper metal layer（Including plating, physical vapor
Deposition）Do not ensure that copper metal layer is covered in the side wall and top of figure well, cause above-mentioned scenario actually
It can not implement.
In consideration of it, inventor has made further improvement again：Multiple spaced figures are formed on substrate；Serving as a contrast
Interconnection line layer of feed stock material is formed on bottom and figure, the material of the interconnection line layer of feed stock material is the compound of copper, can be preferably
It is covered in the side wall and top of figure；Then carry out quick thermal annealing process and return to carve, the quick thermal annealing process
Step make it that the material of interconnection line layer of feed stock material is converted into copper, causes to form side wall in the both sides of figure the step of quarter for described time,
So as to form copper interconnecting line in the both sides of figure, and further reduce the spacing between two neighboring copper interconnecting line, improve
The density of copper interconnecting line.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
The technical scheme of the present embodiment is described in detail with reference to Fig. 4 to Figure 10.
As shown in figure 4, step S1 is first carried out：Semiconductor substrate 100 is provided.
Substrate 100 can be body silicon（bulk silicon）Substrate or silicon-on-insulator（SOI）The conventional substrate such as substrate, lining
Have been formed with forming the active device of circuit on bottom 100（It is not shown such as transistor）And/or passive device（Such as electric capacity, do not scheme
Show）.
Substrate 100 also includes the first dielectric layer positioned at surface（It is not shown）.First dielectric layer can be low k（Dielectric
Constant）Dielectric layer, such as silica, silicon oxide carbide（SiOC）Deng, or the first dielectric layer can be high k dielectric layer, the first dielectric layer
It can be made up of one dielectric layer or be formed by stacking by multilayer dielectric layer.First dielectric layer covers established device on substrate 100
Cover, and the first dielectric layer has been internally formed interconnection structure（Such as metal interconnecting wires and/or conductive plunger）（It is not shown）.
With continued reference to shown in Fig. 4, step S2 is then performed：Multiple spaced figures are formed on the substrate 100, it is multiple
Figure is the first figure 120.
In figure by taking three figures 120 as an example.In one embodiment, the material of the first figure 120 is photoresist, Duo Ge
The forming method of one figure 120 includes：Photoresist layer is formed on the substrate 100（It is not shown）；Light is carried out to the photoresist layer
Carve, to form multiple first figures 120.
In another embodiment, the material of the first figure 120 is amorphous carbon（amorphous carbon）, Duo Ge
The forming method of one figure 120 includes：Amorphous carbon layer is formed on the substrate 100（It is not shown）；On the amorphous carbon layer
Form graphical photoresist layer（It is not shown）；The amorphous carbon layer is carved as mask using the graphical photoresist layer
Erosion, to form multiple first figures 120, then removes the graphical photoresist layer.
Certainly, the forming method of the material of the first figure 120 and the first figure 120 can not be limited only to cited
Embodiment, other materials for suitably forming the first figure 120 and suitably forms the method for the first figure 120 also in the guarantor of the present invention
Within the scope of shield.
In the present embodiment, formed with barrier layer 110 between the first figure 120 and the first dielectric layer of substrate 100.
In the step of etching forms the first figure 120, barrier layer 110 can be used as etching barrier layer（etch stop
layer）.The material on barrier layer 110 comprises at least one kind in SiN, SiC, SiCN.
With reference to shown in Fig. 4 and Fig. 5, step S3 is then performed：It is former that interconnection line is formed on the figure 120 of substrate 100 and first
Material layer 130, the material of interconnection line layer of feed stock material 130 are the compound of copper.
In the present embodiment, the material of interconnection line layer of feed stock material 130 is copper nitride（Cu3N）.Using ald
（ALD）Method forms interconnection line layer of feed stock material 130, to obtain interconnection line layer of feed stock material 130 in uniform thickness；Moreover, utilize original
Sublayer deposition process forms interconnection line layer of feed stock material 130, can cause interconnection line layer of feed stock material 130 that there is preferable step to cover
Lid performance.
Specifically, can be using Cu as target and N2As reacting gas to form copper nitride layer（As interconnection line layer of feed stock material
130）.
With reference to shown in Fig. 5 to Fig. 8, step S4 is then performed：Interconnection line layer of feed stock material 130 carve, in the first figure
The both sides of shape 120 form side wall 131, then remove the first figure 120, carry out quick thermal annealing process again, so that side wall 131
Material is converted into copper so as to form copper interconnecting line 140.
With reference to shown in Fig. 5 and Fig. 6, in the present embodiment, such as Cl is utilized2, the elemental gas containing halogen family such as HBr carry out etch nitride
Layers of copper（As interconnection line layer of feed stock material 130）.In the step of etching forms side wall 131, barrier layer 110 can be used as etch stopper
Layer.
With reference to shown in Fig. 6 and Fig. 7, the first figure 120 is removed so that between existing between two side walls 131 of arbitrary neighborhood
Gap G.When the material of the first figure 120 is photoresist, the first figure 120 is removed using developer solution；When the first figure 120
When material is amorphous carbon, the first figure 120 is removed using the method for ashing.In the step of removing the first figure 120, resistance
Barrier 110 can be used as etching barrier layer.
Compare Fig. 7 and Fig. 4 to understand, the density of side wall 131 is twice of the density of the first figure 120, two neighboring side wall 131 it
Between spacing（Equal to the gap length sum between the width and two neighboring side wall 131 of side wall 131）Less than two neighboring
Spacing between one figure 120（Equal to the gap length between the width of the first figure 120 and two neighboring first figure 120
Sum）.In the present embodiment, spacing of the spacing between two neighboring side wall 131 between two neighboring first figure 120
Half.
With reference to shown in Fig. 7 and Fig. 8, rapid thermal annealing is carried out（Rapid Thermal Annealing, abbreviation RTA）Processing,
Side wall 131 chemically reacts during annealing so that and the material of side wall 131 is converted into copper by copper nitride, so as to
Form copper interconnecting line 140.
In one embodiment, the quick thermal annealing process is carried out in vacuum environment, wherein, annealing temperature is
100 DEG C -300 DEG C, annealing time 5min-1h.Due to copper nitride, property is highly unstable under cryogenic, is readily decomposed to
Cu and N2, therefore through may be such that the material of side wall 131 is converted into copper by copper nitride after annealing after a while, so as to
So that side wall 131 is converted into copper interconnecting line 140.
In another embodiment, the quick thermal annealing process is to carry out in the hydrogen gas atmosphere, wherein, make annealing treatment work
Skill parameter includes：Annealing temperature is 150 DEG C -300 DEG C, annealing time 5min-30min, pressure 1Torr-10Torr.Moving back
In fiery processing procedure, on the one hand, copper nitride can be reduced into copper in the presence of hydrogen, and on the other hand, copper nitride can occur point
Solve and generate copper, so that copper nitride can be fully converted into copper.Annealing temperature can not be too high in annealing process, otherwise passes through
The formed copper interconnecting line surface of annealing can form copper protrusion defect（Cu hillock）, copper projection is likely to result in short circuit
Etc the defects of, so as to influence yield；But annealing temperature again can not be too low, otherwise may result in side wall 131 can not be complete
It is converted into copper.On the basis of this embodiment, also inert gas can be added into annealing environment（Such as nitrogen）, i.e., fast speed heat moves back
Fire processing is carried out in the gaseous environment that hydrogen mixes with inert gas, in a specific embodiment, inert gas body
Product accounts for the 5%-20% of mixed gas.
The quick thermal annealing process step can be carried out in chemical vapor deposition chamber, so as to carry out this step S4 it
After subsequent step S5 can be directly carried out in same reaction chamber（That is dielectric layer or coating）, save transport shape
Into the time for the substrate 100 for having copper interconnecting line 140, and avoid the substrate 100 formed with copper interconnecting line 140 and be exposed to air
In.
Compare Fig. 8 and Fig. 4 and understand that the density of copper interconnecting line 140 is twice of the density of the first figure 120, and two neighboring copper is mutual
Spacing between line 140（Equal to the gap length sum between the width of copper interconnecting line 140 and two neighboring copper interconnecting line 140）
Less than the spacing between two neighboring first figure 120, the spacing between two neighboring copper interconnecting line 140 is set to be no longer limited to light
The limitation of carving technology and can not further reduce, improve the density of copper interconnecting line 140.In the present embodiment, two neighboring copper
The half of spacing of the spacing between two neighboring first figure 120 between interconnection line 140.In the present embodiment, tie
Close shown in Fig. 5, because the interconnection line layer of feed stock material 130 for forming copper interconnecting line 140 is formed using Atomic layer deposition method,
The thickness of interconnection line layer of feed stock material 130 is uniform, therefore can cause the width of copper interconnecting line 140（Copper interconnecting line level side in figure
Upward size）It is uniform.
It should be noted that as shown in figure 5, the material of interconnection line layer of feed stock material 130 can not be limited only to copper nitride, when
The material of interconnection line layer of feed stock material 130 is the compound of other copper, and passes through quick thermal annealing process（In annealing process
The reacting gas that can be reacted with the compound of copper can be added）The compound of the copper can chemically react afterwards（Decompose
Reaction or reduction reaction）And when generating copper, meet the interconnection line layer of feed stock material 130 of this condition also in protection scope of the present invention
Within.
For example, the material of interconnection line layer of feed stock material 130 is cupric oxide（CuO）, then it is available in this step S4 to contain halogen family
The gas of element etches interconnection line layer of feed stock material 130 to form side wall 131, then in hydrogen environment（Or hydrogen and inertia
The mixed-gas environment of gas）It is middle to carry out the quick thermal annealing process, work of the cupric oxide in hydrogen in annealing process
Copper is reduced under, so as to form copper interconnecting line.
In the above-described embodiments, it is first to remove the first figure 120, then carries out quick thermal annealing process so that side wall 131
Material is converted into copper so as to form copper interconnecting line 140.In other embodiments, first can also carry out quick thermal annealing process so that
The material of side wall 131 is converted into copper so as to form copper interconnecting line 140, then removes the first figure 120 again.
Then step S5 is performed：With reference to shown in Fig. 8 and Fig. 9, dielectric layer is formed on substrate 100 and copper interconnecting line 140
150；Or with reference to shown in Fig. 8 and Figure 10, shape on the space G between copper interconnecting line 140 and two neighboring copper interconnecting line 140
Into coating 160.
In one embodiment, after performing above-mentioned steps S4, with reference to shown in Fig. 8 and Fig. 9, in substrate 100 and copper-connection
Dielectric layer 150 is formed on line 140, then, planarization process is carried out to dielectric layer 150, exceeds the upper table of copper interconnecting line 140 to remove
The dielectric layer 150 in face.In one embodiment, dielectric layer 150, the planarization process are formed using chemical gaseous phase depositing process
Technique is cmp.
The material of dielectric layer 150 can be low k（Dielectric constant）Dielectric layer, such as silica, silicon oxide carbide（SiOC）Deng, or
Dielectric layer 150 can be high k dielectric layer.It is shorter to obtain in order to reduce the coupled capacitor between two neighboring copper interconnecting line 140
RC retardation ratio, it is preferable that dielectric layer 150 is high k dielectric layer.
In order to prevent copper to be diffused into dielectric layer 150, and it is attached between increase copper interconnecting line 140 and dielectric layer 150
Put forth effort, before dielectric layer 150 is formed, as shown in figure 9, also including being formed in the side wall of copper interconnecting line 140 and top stopping
The step of layer 170.The material on barrier layer 170 can be tantalum（Ta）, tantalum nitride（TaN）Or tantalum silicon nitrogen（TaSiN）.
In another embodiment, after performing above-mentioned steps S4, with reference to shown in Fig. 8 and Figure 10, in copper interconnecting line 140 and
Coating 160, two neighboring copper interconnecting line 140 and coating 160 are formed on space G between two neighboring copper interconnecting line 140
Air is filled with the space limited, to form air-gap（air gap）S, so, between two neighboring copper interconnecting line 140
Insulated by air-gap S.The material of coating 160 can be silicon nitride（SiN）Or fire sand（SiCN）, so, coating 160
Also act as the etching barrier layer of subsequent etching processes（ESL）.In a specific embodiment, coating 160 utilizes chemistry
CVD method is formed.
Barrier layer 110 can prevent copper to be diffused into the first dielectric layer of the lower section of barrier layer 110, it is therefore prevented that under device performance
Drop.
Embodiment two
Step S4 in step S1 in embodiment one to step S5 is replaced with into step S4 ＇ can obtain the skill of the present embodiment
Art scheme, that is, perform execution step S4 ＇ after the step S3 in embodiment one：Quick thermal annealing process is carried out so that interconnection line is former
The material of material layer is converted into copper metal layer, and copper metal layer carve, and the remaining copper metal layer composition copper of figure both sides is mutual
Line, then remove the first figure.
In step S4 ＇, with reference to shown in Fig. 5 and Figure 11, first interconnection line layer of feed stock material 130 is carried out at rapid thermal annealing
Reason, the material of interconnection line layer of feed stock material 130 changes so as to form copper metal layer 141, specifically after annealing
Annealing steps are referred to the step S4 in embodiment one, will not be repeated here；Then, with reference to shown in Figure 11 and Figure 12, to copper
Metal level 141 carve, and the remaining copper metal layer 141 of the both sides of the first figure 120 forms copper interconnecting line 140；Then, the is removed
One figure 120.In the step of etching forms copper interconnecting line 140, barrier layer 110 can be used as etching barrier layer.
In a specific embodiment, such as Cl of the gas containing halogen element is utilized2, HBr etc. to copper metal layer carve.
The width of the multiple copper interconnecting lines obtained using the technical scheme of above-described embodiment one and embodiment two is identical
, but in some integrated circuits require it is relatively larger with some copper interconnecting line width in semi-conductive substrate and certain
A little copper interconnecting line width are relatively smaller.On the basis of this inventive concept, to the technical scheme of embodiment one and embodiment two
On the basis of make improvements, and provide the technical scheme of following embodiments three and example IV.
Embodiment three
The technical scheme of the present embodiment is described in detail with reference to Figure 13 to Figure 23.
As shown in figure 13, step S11 is first carried out：Semiconductor substrate 200 is provided, substrate 200 includes the positioned at surface
One dielectric layer 210.
The material and structure of first dielectric layer 210 may be referred to the step S1 in embodiment one, will not be repeated here.
As shown in figure 17, step S12 is then performed：Multiple spaced figures, multiple figures are formed on the substrate 100
Including at least one first figure 230 and second graph 240, the material of the first figure 230 and second graph 240 differs,
Wherein, the material of second graph 240 is the compound of copper or copper.
In the present embodiment, forming the method for multiple spaced figures on the substrate 100 includes：
As shown in figure 13, the second dielectric layer 212 is formed on the first dielectric layer 210, figure is formed on the second dielectric layer 212
Shape photoresist layer 220, it is that mask performs etching to the second dielectric layer 212 with graphical photoresist layer 220, with the second dielectric
Groove 211 is formed in layer 212, the quantity of groove 211 is at least one（In figure by taking a groove as an example）；
Then, with reference to shown in Figure 13 and Figure 14, graphical photoresist layer 220 is removed, then fills second into groove 211
Graphic material layer,, can be in the second dielectric layer 212 and groove 211 in a specific embodiment to form second graph 240
Upper formation second graph material layer, the second graph material layer fill up groove 211, then carry out cmp processing
To remove unnecessary second graph material layer, the remaining second graph material layer being filled in groove 211 forms second graph
240, the upper surface of second graph 240 almost flushes with the second dielectric layer 212；
Then, with reference to shown in Figure 14 and Figure 15, remaining second dielectric layer 212 is removed；
Then, as shown in figure 16, the first graphic material layer 231, the first graphic material layer are formed on the first dielectric layer 210
231 surfaces almost flush with the surface of second graph 240, can be in the first dielectric layer 210 and second in a specific embodiment
The first graphic material layer is formed on figure 240, then carries out cmp processing to remove the first unnecessary graphic material
Layer, the first graphic material layer is the first graphic material layer 231 after cmp, and the surface of the first graphic material layer 231
Almost flushed with the surface of second graph 240；
Then, with reference to shown in Figure 16 and Figure 17, processing is patterned to the first graphic material layer 231, to form first
Figure 230, the quantity of the first figure 230 are at least one（In figure by taking two the first figures 230 as an example）, it is specific real at one
Apply in example, graphical photoresist layer can be formed on the first graphic material layer 231 and second graph 240, then with the figure
It is that mask performs etching to the first graphic material layer 231 to change photoresist layer, to form the first figure 230.
In the present embodiment, the material of the first figure 230 is photoresist or amorphous carbon, but the material of the first figure 230
Material can not be limited only to embodiment cited in the present embodiment, and other materials for suitably forming the first figure 230 also exist
Within protection scope of the present invention.
In the present embodiment, the material of second graph 240 is copper.
As shown in figure 18, step S13 is then performed：Formed on substrate 100, the first figure 230 and second graph 240 mutual
Line layer of feed stock material 250.
In the present embodiment, the material of interconnection line layer of feed stock material 250 is copper nitride（Cu3N）.
As shown in Figure 18 to Figure 21, step S14 is then performed：Interconnection line layer of feed stock material 250 carve, the first figure
The remaining interconnection line layer of feed stock material 250 of 230 both sides forms side wall 251, the remaining interconnection line layer of feed stock material of the both sides of second graph 240
250 form side wall 252, then remove the first figure 230, carry out quick thermal annealing process again, so that side wall 251 and side wall 252
Material be converted into copper so as to form copper interconnecting line 261.
With reference to shown in Figure 18 and Figure 19, interconnection line layer of feed stock material 250 carve, with the both sides of the first figure 230
Side wall 251 is formed, side wall 252 is formed in the both sides of second graph 240.
With reference to shown in Figure 19 and Figure 20, the first figure 230 is removed so that between two neighboring side wall 251 or adjacent side
Clearance G be present between wall 251 and side wall 252.
With reference to shown in Figure 20 and Figure 21, after annealing, the material of side wall 251 and side wall 252 be converted into copper from
And form copper interconnecting line 261.
The both sides of first figure 230 and second graph 240 are each formed with copper interconnecting line 261.In the present embodiment, shape is defined
It is the first copper interconnecting line 261 into the copper interconnecting line 261 in the side wall of the first figure 230；Define second graph 240 and second graph
Copper interconnecting line 261 on 240 two sides collectively forms the second copper interconnecting line 262.It follows that the width of the second copper interconnecting line 262
Width of the degree more than the first copper interconnecting line 261.
It should be noted that as shown in figure 14, the material of second graph 240 should not be limited only to copper, when second graph 240
Material be copper compound, during such as copper nitride or cupric oxide, the material of second graph 240 in the annealing process of this step
Material can be converted into copper, thus the copper interconnecting line 261 on the two side of second graph 240 can be with the second graph after annealing
240 collectively form the second copper interconnecting line 262.
Certainly, the material of second graph 240 can not be limited only to copper, copper nitride or cupric oxide, when second graph 240
Material be other copper compound, and pass through quick thermal annealing process（Can be added in annealing process can be with the change of copper
The reacting gas that compound reacts）The compound of the copper can chemically react afterwards（Decomposition reaction or reduction reaction）And
When generating copper, meet the second graph 240 of this condition also within protection scope of the present invention.
Separately it should be noted that, as shown in figure 18, the material of interconnection line layer of feed stock material 250 can not be limited only to nitrogenize
Copper, other alternative materials of interconnection line layer of feed stock material 250 may be referred to embodiment one, will not be repeated here.
Then step S15 is performed：With reference to shown in Figure 21 and Figure 22, the first dielectric layer 210, the first copper interconnecting line 261 and
Dielectric layer 270 is formed on second copper interconnecting line 262；Or with reference to shown in Figure 21 and Figure 23, in the first copper interconnecting line 261, second
Coating 280 is formed on space G between copper interconnecting line 262 and two neighboring copper interconnecting line.
More specifically the method for formation dielectric layer 270 and coating 280 may be referred to the step S5 in embodiment one, herein
Repeat no more.
, can also be in the first dielectric layer 210, the first copper interconnecting line before dielectric layer 270 is formed as embodiment one
261 and second barrier layer B2 is formed on copper interconnecting line 262.
It is emphasized that because the technical scheme of the present embodiment is further to improve to obtain on the basis of embodiment one
, therefore the technical scheme of above-mentioned the present embodiment merely depict some important improvements, it is other unspecified
Interior perhaps alternative can refer to embodiment one, repeat no more in the present embodiment.
Example IV
Step S14 in step S11 in embodiment three to step S15 is replaced with into step S14 ＇ can obtain the present embodiment
Technical scheme, that is, perform and perform step S14 ＇ after the step S13 in embodiment three：Quick thermal annealing process is carried out so that mutually
The material of line layer of feed stock material is converted into copper metal layer, copper metal layer carve, the remaining copper metal layer structure of figure both sides
Into copper interconnecting line, the first figure is then removed.
In step S14 ＇, with reference to shown in Figure 18 and Figure 24, first interconnection line layer of feed stock material 250 is carried out at rapid thermal annealing
Reason, the material of interconnection line layer of feed stock material 250 changes after annealing specifically moves back so as to form copper metal layer 260
Fiery step is referred to the step S4 in embodiment one, will not be described here；Then, with reference to shown in Figure 24 and Figure 25, to copper metal
Layer 260 carve, and the remaining copper metal layer 260 of the first figure 230 and the both sides of second graph 240 forms copper interconnecting line 261.
It is the first copper interconnecting line 261 to define the copper interconnecting line 261 in the side wall of the first figure 230.When the material of second graph 240
Expect for copper when, the copper interconnecting line 261 on second graph 240 and the two side of second graph 240 collectively forms the second copper interconnecting line
262；When the material of second graph 240 is the compound of copper, second graph 240 is also converted to copper after annealing, so,
Second graph 240 after the copper interconnecting line 261 and annealing of the both sides of second graph 240 collectively forms the second copper interconnecting line 262.
It is emphasized that because the technical scheme of the present embodiment is further to improve to obtain on the basis of embodiment three
, therefore the technical scheme of above-mentioned the present embodiment merely depict some important improvements, it is other unspecified
Interior perhaps alternative can refer to embodiment one, embodiment two and embodiment three, repeat no more in the present embodiment.
In the technical scheme of above-described embodiment three and example IV, the width of the first copper interconnecting line 261 is mutual less than the second bronze medal
The width of line 262, and the first copper interconnecting line 261 directly connects with the interconnection structure in the first dielectric layer 210.
The first relatively small copper interconnecting line 261 of width can be used as the copper interconnecting line of functional areas circuit in integrated circuit, wide
Spend the copper interconnecting line that the second relatively large copper interconnecting line 262 can be used as peripheral circuit in integrated circuit.
When interconnection structure electrical connection of the first relatively small copper interconnecting line 261 of width directly and in the first dielectric layer 210
When, because the width of the first copper interconnecting line 261 is typically smaller, density is bigger, easily there is short circuit.Asked to solve this
Topic, following embodiments five and embodiment six have made following improvement on the basis of embodiment three and example IV：Width is relative
Less first copper interconnecting line second copper interconnecting line relatively large with the width positioned at same layer connects, and the second copper interconnecting line
Directly electrically connected with the interconnection structure in the first dielectric layer.Because the width of the second copper interconnecting line is bigger, density is also smaller,
It is easier to realize that the second copper interconnecting line directly electrically connects with the interconnection structure in the first dielectric layer.
Embodiment five
The technical scheme of the present embodiment is described in detail with reference to Figure 26 to Figure 35.
As shown in figure 30, step S21 is first carried out：Semiconductor substrate 300 is provided, substrate 300 includes the positioned at surface
One dielectric layer 310.
As shown in figure 30, step S22 is then performed：Multiple spaced figures, multiple figures are formed on the substrate 100
Include at least one first figure 330 and second graph 340, formed with resistance between the first figure 330 and the first dielectric layer 310
The material of barrier B1, the first figure 330 and second graph 340 differs, wherein, the material of second graph 340 is copper or copper
Compound.
In the present embodiment, barrier layer B1 material comprises at least one kind in SiN, SiC, SiCN.
In the present embodiment, forming the method for multiple spaced figures on the substrate 100 includes：
As shown in figure 26, barrier layer B1 is formed on the first dielectric layer 310, the second dielectric layer is formed on the B1 of barrier layer
312, graphical photoresist layer 320 is formed on the second dielectric layer 312, is that mask is situated between to second with graphical photoresist layer 320
Electric layer 312 and barrier layer B1 are performed etching, and to form groove 311 in the second dielectric layer 312 and barrier layer B1, groove 311 is sudden and violent
Expose the first dielectric layer 310 of lower section, the quantity of groove 311 is at least one（In figure by taking a groove as an example）；
Then, with reference to shown in Figure 26 and Figure 27, graphical photoresist layer 320 is removed, then fills second into groove 311
Graphic material layer, to form second graph 340, second graph 340 contacts with the first dielectric layer 310 below；
Then, with reference to shown in Figure 27 and Figure 28, the second dielectric layer 312 is removed, in the step of removing the second dielectric layer 312
Barrier layer B1 is used as etching barrier layer；
Then, as shown in figure 29, the first graphic material layer 331, the table of the first graphic material layer 331 are formed on the B1 of barrier layer
Face almost flushes with the surface of second graph 340；
Then, with reference to shown in Figure 29 and Figure 30, processing is patterned to the first graphic material layer 331, to form first
Figure 330, the quantity of the first figure 330 are at least one（In figure by taking two the first figures 330 as an example）, in graphical treatment
Barrier layer B1 is used as etching barrier layer in the step of one graphic material layer 331.
In the present embodiment, the material of second graph 340 is copper.
As shown in figure 31, step S23 is then performed：Formed on substrate 100, the first figure 330 and second graph 340 mutual
Line layer of feed stock material 350, the material of interconnection line layer of feed stock material 350 are the compound of copper.
In the present embodiment, the material of interconnection line layer of feed stock material 350 is copper nitride（Cu3N）.
As shown in Figure 31 to Figure 34, step S24 is then performed：Interconnection line layer of feed stock material 350 carve, the first figure
The remaining interconnection line layer of feed stock material 350 of 330 both sides forms side wall 351, the remaining interconnection line layer of feed stock material of the both sides of second graph 340
350 form side wall 352, then remove the first figure 330, carry out quick thermal annealing process again, so that side wall 351 and side wall 352
Material be converted into copper so as to form copper interconnecting line 361.
With reference to shown in Figure 31 and Figure 32, barrier layer B1 is used as etching resistance in the step of etching interconnection line layer of feed stock material 350
Barrier.
With reference to shown in Figure 32 and Figure 33, the first figure 330 is removed so that between two neighboring side wall 351 or adjacent side
Clearance G be present between wall 351 and side wall 352.Barrier layer B1 is used as etching barrier layer in the step of removing the first figure 330.
With reference to shown in Figure 33 and Figure 34, after annealing, the material of side wall 351 and side wall 352 be converted into copper from
And form copper interconnecting line 361.The both sides of first figure 330 and second graph 340 are each formed with copper interconnecting line 361.In this implementation
In example, the copper interconnecting line 361 that definition is formed in the side wall of the first figure 330 is the first copper interconnecting line 361；Define second graph
340 and the two side of second graph 340 on copper interconnecting line 361 collectively form the second copper interconnecting line 362.It follows that the second bronze medal
The width of interconnection line 362 is more than the width of the first copper interconnecting line 361.
Figure 34 is the profile in the AA sections along Figure 35, with reference to shown in Figure 34 and Figure 35, one in the second copper interconnecting line 362
Part copper interconnecting line electrically connects with the interconnection structure in the first dielectric layer 310, the second bronze medal of the first copper interconnecting line 361 and same layer
Interconnection line 362 connects, and is blocked a layer B1 between the first copper interconnecting line 361 and the first dielectric layer 310 and separates, therefore, the first bronze medal
Interconnection line 361 is electrically connected by the interconnection structure in the second copper interconnecting line 362 and the first dielectric layer 310.
Then step S25 is performed：The second dielectric layer is formed in Semiconductor substrate and copper interconnecting line；Or in copper-connection
Coating is formed on space between line and two neighboring copper interconnecting line.
It is emphasized that because the technical scheme of the present embodiment is further to improve to obtain on the basis of embodiment three
, therefore the technical scheme of above-mentioned the present embodiment merely depict some important improvements, it is other unspecified
Interior perhaps alternative can refer to above three embodiments, repeat no more in the present embodiment.
Embodiment six
Step S24 in step S21 in embodiment five to step S25 is replaced with into step S24 ＇ can obtain the present embodiment
Technical scheme, that is, perform and perform step S24 ＇ after the step S23 in embodiment five：Quick thermal annealing process is carried out so that mutually
The material of line layer of feed stock material is converted into copper metal layer, copper metal layer carve, the remaining copper metal layer structure of figure both sides
Into copper interconnecting line, the first figure is then removed.
In step S14 ＇, with reference to shown in Figure 30 and Figure 36, first interconnection line layer of feed stock material 350 is carried out at rapid thermal annealing
Reason, the material of interconnection line layer of feed stock material 350 changes so as to form copper metal layer 360 after annealing, and when the
When the material of two figures 340 is the compound of copper, second graph 340 is also converted to copper, such copper metal layer after annealing
360 form an entirety with second graph 340, and specific annealing steps are referred to the step S4 in embodiment one, herein not
Repeat；Then, with reference to shown in Figure 36 and Figure 37, copper metal layer 360 carve, 340 liang of the first figure 330 and second graph
The remaining copper metal layer 360 of side forms copper interconnecting line 361, and second graph 340 and the copper interconnecting line 361 of its both sides collectively form copper
Interconnection line 362；Then, the first figure 330 is removed.
It is emphasized that because the technical scheme of the present embodiment is further to improve to obtain on the basis of embodiment five
, therefore the technical scheme of above-mentioned the present embodiment merely depict some important improvements, it is other unspecified
Interior perhaps alternative can refer to above five embodiments, repeat no more in the present embodiment.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
- A kind of 1. forming method of copper interconnecting line, it is characterised in that including：Semiconductor substrate is provided；Multiple spaced figures are formed over the substrate, and first figure is comprised at least in multiple figures；Interconnection line layer of feed stock material is formed on the substrate and figure, the material of the interconnection line layer of feed stock material is the chemical combination of copper Thing；The interconnection line layer of feed stock material carve, side wall is formed in the both sides of the figure, then removes first figure Shape, quick thermal annealing process is carried out, it is mutual so as to form copper that the quick thermal annealing process makes the material of the side wall be converted into copper Line；Or quick thermal annealing process is carried out so that the material of the interconnection line layer of feed stock material is converted into copper metal layer, to described Copper metal layer carve, and the remaining copper metal layer of the figure both sides forms copper interconnecting line, then removes first figure；Also include at least one second graph, the material of first figure and the material of the second graph in multiple figures Material differs, and the material of the second graph is the compound of copper or the copper；When the material of the second graph is the compound of copper, the quick thermal annealing process makes the material of the second graph Be converted to copper.
- 2. the forming method of copper interconnecting line according to claim 1, it is characterised in that multiple figures are described One figure.
- 3. the forming method of copper interconnecting line according to claim 1, it is characterised in that the substrate is included positioned at surface First dielectric layer, first dielectric layer are interior formed with interconnection structure；The copper interconnecting line is located on the first dielectric layer.
- 4. the forming method of copper interconnecting line according to claim 3, it is characterised in that formed in the first figure both sides Copper interconnecting line and the first dielectric layer between be provided with barrier layer.
- 5. the forming method of copper interconnecting line according to claim 3, it is characterised in that form multiple over the substrate Include every the method for the figure of arrangement：The second dielectric layer is formed over the substrate；Graphical photoresist layer is formed on second dielectric layer；Second dielectric layer is performed etching as mask using the graphical photoresist layer, in second dielectric layer at least A groove is formed, the groove exposes the first dielectric layer；After removing the graphical photoresist layer, second graph material layer is filled into the groove, to form described second Figure；Form the second graph and remove second dielectric layer afterwards；After removing second dielectric layer, the first graphic material layer, institute are formed on first dielectric layer and second graph The first graphic material layer surface is stated to flush with the second graph surface；Processing is patterned to the first graphic material layer, forms first figure.
- 6. the forming method of copper interconnecting line according to claim 4, it is characterised in that form multiple over the substrate Include every the method for the figure of arrangement：The barrier layer, the second dielectric layer on barrier layer are formed on first dielectric layer, positioned at the second dielectric layer On graphical photoresist layer；Second dielectric layer and barrier layer are performed etching as mask using the graphical photoresist layer, to be situated between described second A groove is at least formed in electric layer and barrier layer, the groove exposes first dielectric layer；After removing the graphical photoresist layer, second graph material layer is filled into the groove, to form described second Figure；Form the second graph and remove second dielectric layer afterwards；After removing second dielectric layer, the first graphic material layer is formed on the barrier layer and second graph, described One graphic material layer surface flushes with the second graph surface；Processing is patterned to the first graphic material layer, to form first figure.
- 7. the forming method of copper interconnecting line according to claim 4, it is characterised in that the material on the barrier layer at least wraps Include one kind in SiN, SiC, SiCN.
- 8. the forming method of copper interconnecting line according to claim 1, it is characterised in that it is described remove first figure, In the step of carrying out quick thermal annealing process, first remove first figure, carry out quick thermal annealing process again；It is or advanced Row quick thermal annealing process, first figure is removed again.
- 9. the forming method of copper interconnecting line according to claim 1, it is characterised in that the material of first figure is light Photoresist or amorphous carbon.
- 10. the forming method of copper interconnecting line according to claim 1, it is characterised in that utilize Atomic layer deposition method shape Into the interconnection line layer of feed stock material.
- 11. the forming method of copper interconnecting line according to claim 1, it is characterised in that the compound of the copper is nitridation Copper.
- 12. the forming method of copper interconnecting line according to claim 11, it is characterised in that the quick thermal annealing process is Carried out in vacuum environment, annealing temperature is 100 DEG C -300 DEG C, annealing time 5min-1h.
- 13. the forming method of copper interconnecting line according to claim 11, it is characterised in that the quick thermal annealing process is Carry out in the hydrogen gas atmosphere, parameter and annealing includes：Annealing temperature is 150 DEG C -300 DEG C, annealing time 5min-30min, Pressure is 1Torr-10Torr.
- 14. the forming method of copper interconnecting line according to claim 11, it is characterised in that the annealing is in hydrogen And carried out in the mixed-gas environment of inert gas, parameter and annealing includes：Annealing temperature is 150 DEG C -300 DEG C, during annealing Between be 5min-30min, pressure 1Torr-10Torr.
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| CN102237295A (en) * | 2010-04-28 | 2011-11-09 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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