CN104102599A - Flash memory device and data transmission method - Google Patents
Flash memory device and data transmission method Download PDFInfo
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- CN104102599A CN104102599A CN201310125024.5A CN201310125024A CN104102599A CN 104102599 A CN104102599 A CN 104102599A CN 201310125024 A CN201310125024 A CN 201310125024A CN 104102599 A CN104102599 A CN 104102599A
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Abstract
The invention provides a flash memory device and a data transmission method. The flash memory device comprises a first memory chip and a second memory chip, wherein the first memory chip comprises a first identification code, and when a first identification part in a first command received by the first memory chip is identical with the first identification code, a first data transmission part in the first command is executed and a first access operation is performed within a first operation period; the second memory chip is provided with a second identification code which is different from the first identification code, the second memory chip receives a second command within the first operation period, and when second identification information in the second command is identical with the second identification code, the second memory chip executes a second data transmission command in the second command to perform a second access operation. Since the plurality of memory chips provided by the invention can respectively perform access operations, the data transmission efficiency of the flash memory device is improved.
Description
Technical field
The invention relates to flash memory, relate to especially a kind of flash memory devices and data transmission method that is applicable to have multiple flash memory chips.
Background technology
Because flash memory can retain the data of having stored in the situation of not power supply, and there is the advantages such as programming time is short, low power consumption, therefore, widely for example, as the medium of the various electronic products such as mobile phone, digital camera, notebook computer: storage card, Portable disk etc.For the storage data volume in response to day by day increasing, and develop the flash memory device of multi-chip (Multi-Die) stacked structure.But, compared to dynamic RAM, flash memory has the longer write time, makes the flash memory device of multi-chip stacking structure need to expend the plenty of time and carries out writing of data, makes the efficiency of flash memory device transmission data lower.
In view of this, need a kind of new scheme, to promote the efficiency of data transmission of flash memory device.
Summary of the invention
The technical matters that the present invention solves is: the invention provides a kind of flash memory device and data transmission method, to solve the low data transmission efficiency causing compared with the long write time because of flash memory.
Technical solution of the present invention is: the invention provides a kind of flash memory device, wherein, flash memory device comprises a first memory chip and a second memory chip, wherein first memory chip comprises one first identification code, one first controller and one first flash memory, when one first Identification Division in one first instruction that the first controller receives is divided while being same as the first identification code, carry out the first data transmission part in the first instruction, in order to the first flash memory is carried out to one first accessing operation within one first operating cycle; Second memory chip has one second identification code that is different from the first identification code, and second memory chip comprises a second controller and one second flash memory, second controller receives one second instruction in the first operating cycle, and in the time that one second identification information in the second instruction is same as the second identification code, second controller is carried out one second data transfer instruction in the second instruction, in order to the second flash memory is carried out to one second accessing operation.
The present invention also provides a kind of data transmission method, be applied to a flash memory device, flash memory device comprises a first memory chip and a second memory chip, wherein first memory chip comprises one first identification code, one first controller and one first flash memory, second memory chip comprises one second identification code, a second controller and one second flash memory, data transmission method comprises: receive one first instruction, wherein the first instruction comprises one first identification part and a first data transmission part; Divide while being same as the first identification code when the first Identification Division that the first controller receives, carry out first data transmission part, in order to the first flash memory is carried out to one first accessing operation within one first operating cycle; And second controller receives one second instruction in the first operating cycle, and in the time that one second identification information in the second instruction is same as the second identification code, second controller is carried out one second data transfer instruction in the second instruction, in order to the second flash memory is carried out to one second accessing operation.
Flash memory device provided by the invention comprises multiple memory chips, and each memory chip can first judge after instruction that whether the identification information of this instruction is identical with the identification code of self receiving.When the identification information of this instruction is identical with the identification code of oneself, just carry out this instruction and carry out corresponding data transmission.Meet the memory chip of identification information of this instruction in the time carrying out write operation, another memory chip can carry out a write operation or read operation.Multiple memory chip provided by the present invention can carry out accessing operation separately, thereby promotes the data transmission efficiency of flash memory device.
Brief description of the drawings
Fig. 1 is the schematic diagram of flash memory device provided by the present invention.
Fig. 2 is the process flow diagram of the data transmission method that is applied to flash memory device provided by the present invention.
[symbol description]
100 ︰ flash memory device C10 ︰ the first instructions
110 ︰ first memory chip C11 ︰ the first identification parts
112 ︰ the first controller C12 ︰ first data transmission parts
114 ︰ first flash memory C20 ︰ the second instructions
120 ︰ second memory chip C21 ︰ the second identification parts
122 ︰ second controller C22 ︰ the second tcp data segments
124 ︰ the second flash memory V
dD︰ power source supply end
130 ︰ input buffers
140 ︰ output buffers
160 ︰ main frames
Embodiment
Device and the using method of various embodiments of the invention will be discussed in detail below.But it should be noted that many feasible inventive concepts provided by the present invention can implement in various particular ranges.These specific embodiments are only for illustrating device provided by the invention and using method, but non-for limiting scope of the present invention.
Fig. 1 is the schematic diagram of flash memory device provided by the present invention.Flash memory device 100 is accepted the instruction from main frame 160, and will write in flash memory device 100 from the data of main frame 160 or other electronic installation (not shown)s according to this instruction, or be sent to main frame 160 or other electronic installations according to this instruction by reading from the data of flash memory device 100.In an embodiment, main frame 160 can be portable apparatus or computer product, and the flash memory devices 100 that is coupled to main frame 160 can be storage card.Flash memory device 100 comprises multiple memory chips, and each memory chip can first judge that after receiving from the instruction of main frame 160 whether the identification information of this instruction is identical with the identification code (identification code) of self.When the identification information of this instruction is identical with the identification code of controlling oneself, just carry out this instruction and carry out corresponding data transmission.Meet the memory chip of identification information of this instruction in the time carrying out write operation, another memory chip can carry out a write operation or read operation.For convenience of description, flash memory device 100 only has two memory chips in the present embodiment.In one embodiment, flash memory device 100 comprises plural memory chip.In another embodiment, flash memory device 100 is a multi-chip stacking structure.
As shown in Figure 1, flash memory device 100 comprises a first memory chip 110, second memory chip 120, input buffer 130 and output buffer 140.As shown in Figure 1, input buffer 130 is coupled to first memory chip 110 and second memory chip 120, in order to the instruction from main frame 160 or data are sent to first memory chip 110 and/or second memory chip 120.Output buffer 140 is coupled to first memory chip 110 and second memory chip 120, in order to the data of first memory chip 110 and/or second memory chip 120 are sent to main frame 160 or other electronic installations.In one embodiment, input buffer 130 can be merged into an inputoutput buffer with the function of output buffer 140.First memory chip 110 has one first identification code (not shown), one first controller 112 and one first flash memory 114, and second memory chip 120 has one second identification code (not shown), a second controller 122 and one second flash memory 124, the hardware control that wherein the first controller 112 and second controller 122 form for logical circuit.In addition, flash memory device 100 can be connected to a power source supply end V
dDand an earth terminal, to obtain the required power supply of data access.
It should be noted that because flash memory device 100 is connected to power source supply end V
dDwith earth terminal, therefore can define the first identification code and the second identification code by different magnitudes of voltage.In one embodiment, power source supply end V
dDthe high voltage providing is denoted as digital signal 1, and the low-voltage that earth terminal provides is denoted as digital signaling zero.In one embodiment, first memory chip 110 is connected to above-mentioned power source supply end V with the pin of second memory chip 120
dDwith earth terminal, make the first identification code and the second identification code be denoted as 1 and 0.In another embodiment, flash memory device 100 has four memory chips, power source supply end V
dDand between earth terminal, can divide into multiple voltage quasi positions, and the pin of four memory chips is connected to respectively multiple voltage quasi positions, makes the first identification code to the four identification codes of its correspondence be denoted as respectively 00,01,10 and 11.In another embodiment, multiple identification codes also can be encoded or be indicated by the software program of flash memory device 100 inside.For example, the software program input signal specific of flash memory device 100 inside is to multiple memory chips storage, as the identification code of described multiple memory chips.
First, flash memory device 100 is unlocked after (power-up), can reset the first identification code of first memory chip 110 and the second identification code of second memory chip 120, and wherein the first identification code is different from the second identification code.Particularly, in order effectively to distinguish each identification code, the identification code of the multiple memory chips in flash memory device 100 is all different each other.Then, flash memory device 100 can receive the one first instruction C10 from a main frame 160, and the first instruction C10 comprises one first identification part C11 and a first data transmission part (also can be described as the first master instruction part) C12.The first instruction C10 is sent to first memory chip 110 and second memory chip 120 by input buffer 130.It should be noted that, now first memory chip 110 is received the first instruction C10 with second memory chip 120 all simultaneously, and the first controller 112 can be compared the first identification code and the first identification part C11, second controller 122 can comparison the second identification code and the first identification part C11.Due to different each other between each identification code, therefore only have an identification code can be same as this first identification part C11.
In one embodiment, in the time that the first identification part C11 is same as the first identification code, that is first identification part C11 be different from the second identification code, the first flash memory 114 can be carried out the first data transmission part C12 of this first instruction C10, in order to the first flash memory 114 is carried out to the first accessing operation within the first operating cycle.For example, the first accessing operation can be the operation that data read or write.When the first accessing operation, to be that data are write fashionable, and data can write among the first flash memory 114 by input buffer 130.Due to flash memory need to be longer the data write time, therefore data, by after input buffer 130, can temporarily be stored in a working storage (not shown) of flash memory device 100 inside.Particularly, this working storage can be arranged among the controller of memory chip, or is arranged among input buffer 130.Within the first operating cycle, the data that are written into the first flash memory 114 have been stored in working storage, and now input buffer 130 can be in order to transmit one second instruction C20 to first memory chip 110 and second memory chip 120.When the first accessing operation is data while reading, the data that read from the first flash memory 114 can export main frame 160 to by output buffer 140.In another embodiment, in the time that the first identification part C11 is different from the first identification code, the first controller 112 is ignored this first instruction C10, the first flash memory 114 is not carried out to any accessing operation.
It should be noted that, in the first flash memory 114 is carried out the first operating cycle of the first accessing operation, flash memory device 100 can receive the one second instruction C20 from a main frame or computer apparatus, and the second instruction C20 comprises one second identification part C21 and one second tcp data segment (also can be described as the second master instruction part) C22.In one embodiment, the first controller 112 in flash memory device 100 all can receive this second instruction C20 with second controller 122.In the time that the second identification part C21 is same as the second identification code, the second flash memory 124 can be carried out the second tcp data segment C22 of the second instruction C20, within the second operating cycle, the second flash memory 124 is carried out to the second accessing operation.The operation that the data that can be the second accessing operation read or write, the detailed class of operation of its data transmission is similar to the first accessing operation, so locate to repeat no more.
Particularly, in one embodiment, when the first accessing operation be data write operation time, write the first operating cycle of the first flash memory 114 in data, the second flash memory 120 can receive the second instruction C20.Now, if the second identification code is same as the second identification part C21, the second accessing operation that the second flash memory 124 can executing data reads or writes.The data that write due to the first flash memory 114 can be stored in working storage, therefore when the first flash memory 114 carries out data when writing, the second flash memory 124 can write another data by input buffer 130, or exports by output buffer 140 data that are read.Therefore,, in the time of first flash memory 114 foundation the first instruction C10 data writing, the second flash memory 124 can be carried out reading or writing of another data according to the second instruction C20.
Be noted that because output buffer 140 once can only pass through data, and the time of reading of flash memory be shorter than the write time, therefore the reading out data of flash memory does not need temporarily to deposit in a working storage.Therefore, the data that read when the first flash memory 114 are during by output buffer 140, and the data that the second flash memory 124 reads just cannot be passed through output buffer 140.In addition, in another embodiment, when the second identification part C21 is different from the second identification code, second controller 122 is ignored this second instruction C20, the second flash memory 124 is not carried out to any accessing operation.
Fig. 2 is the process flow diagram of the data transmission method that is applied to flash memory device provided by the present invention.First, in step S202, open the power supply of flash memory device 100, in step S204, reset the identification code of each memory chip.In step S206, each memory chip receives the first instruction C10, and wherein the first instruction C10 comprises the first identification part C11 and first data transmission part C12.In step S208, judge whether that the identification code of a memory chip is same as the first received identification part C11.If so, enter step S210; If not, get back to step S206.In step S210, the memory chip (supposing it is first memory chip 110) that identification code is identical with the first identification part C11 is carried out first data transmission part C12, in order to carry out the first accessing operation in the first operating cycle, and each memory chip receives the second instruction C20 in the first operating cycle, wherein the second instruction C20 comprises the second identification part C21 and the second tcp data segment C22.Then, enter step S212, judge whether that the identification code of a memory chip is same as the second received identification part C21.If so, enter step S214; If not, get back to step S210.In step S214, the memory chip (supposing second memory chip 120) that identification code is identical with the second identification part C21 is carried out the second tcp data segment C22 to carry out one second accessing operation.Then, enter step S216, end flash memory device 100 transmits the flow process of data.
The foregoing is only preferred embodiment provided by the invention, when not limiting scope of the invention process with this, generally change and modify according to the simple equivalence described in claim provided by the invention and description, all still belonging to patent covering scope provided by the invention.In addition, arbitrary embodiment provided by the invention or claim must not reached whole object provided by the present invention, advantage or feature.In addition, summary part and title are only for the use of auxiliary patent document search, are not used for limiting interest field provided by the invention.
Claims (10)
1. a flash memory device, is characterized in that, described flash memory device comprises:
One first memory chip, there is one first identification code, this first memory chip comprises one first controller and one first flash memory, when one first Identification Division in one first instruction that this first controller receives is divided while being same as this first identification code, carry out the first data transmission part in this first instruction, in order to this first flash memory is carried out to one first accessing operation within one first operating cycle; And
One second memory chip, there is one second identification code that is different from this first identification code, and this second memory chip comprises a second controller and one second flash memory, this second controller receives one second instruction in this first operating cycle, and when one second Identification Division in this second instruction is divided while being same as this second identification code, this second controller is carried out one second tcp data segment in this second instruction, in order to this second flash memory is carried out to one second accessing operation.
2. flash memory device according to claim 1, is characterized in that, described the first controller and described second controller all can receive described the first instruction.
3. flash memory device according to claim 1, it is characterized in that, in the time that the second identification part in described the second instruction is different from the second identification code, this second controller is ignored this second instruction, this second flash memory is not carried out to any accessing operation.
4. flash memory device according to claim 1, is characterized in that, described the first accessing operation is write operation, and the second accessing operation is read operation or write operation.
5. flash memory device according to claim 1, it is characterized in that, described flash memory device comprises a power source supply end and an earth terminal is connected to this flash memory device, make this first memory chip and the pin of this second memory chip be connected to the magnitude of voltage of different levels, to set the identification code of this first memory chip and this second memory chip.
6. a data transmission method, it is characterized in that, described data transmission method is applied to a flash memory device, this flash memory device comprises a first memory chip and a second memory chip, wherein this first memory chip comprises one first identification code, one first controller and one first flash memory, this second memory chip comprises one second identification code, a second controller and one second flash memory, and this data transmission method comprises:
The first controller receives one first instruction, and wherein this first instruction comprises one first identification part and a first data transmission part;
Divide while being same as this first identification code when the first Identification Division that this first controller receives, the first flash memory is carried out this first data transmission part, in order to this first flash memory is carried out to one first accessing operation within one first operating cycle; And
This second controller receives one second instruction in this first operating cycle, and when one second Identification Division in this second instruction is divided while being same as this second identification code, this second controller is carried out one second tcp data segment in this second instruction, in order to this second flash memory is carried out to one second accessing operation.
7. data transmission method according to claim 6, is characterized in that, described the first controller and described second controller all can receive described the first instruction.
8. data transmission method according to claim 6, it is characterized in that, in the time that the second identification part in described the second instruction is different from this second identification code, this second controller is ignored this second instruction, this second flash memory is not carried out to any accessing operation.
9. data transmission method according to claim 6, is characterized in that, described the first accessing operation is write operation, and the second accessing operation is read operation or write operation.
10. data transmission method according to claim 6, it is characterized in that, described data transmission method comprises a power source supply end and an earth terminal is connected to this flash memory device, make this first memory chip and the pin of this second memory chip be connected to the magnitude of voltage of different levels, to set the identification code of this first memory chip and this second memory chip.
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| CN201310125024.5A CN104102599A (en) | 2013-04-11 | 2013-04-11 | Flash memory device and data transmission method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1516115A (en) * | 1997-05-16 | 2004-07-28 | 冲电气工业株式会社 | Non-volatile semiconductor magnetic disk device |
| CN101004953A (en) * | 2006-01-18 | 2007-07-25 | 苹果电脑有限公司 | Disabling faulty flash memory dies |
| CN101482749A (en) * | 2008-01-11 | 2009-07-15 | 鸿富锦精密工业（深圳）有限公司 | Automatic addressing system of master device to slave device |
| CN102428455A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Data striping in a flash memory data storage device |
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2013
- 2013-04-11 CN CN201310125024.5A patent/CN104102599A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1516115A (en) * | 1997-05-16 | 2004-07-28 | 冲电气工业株式会社 | Non-volatile semiconductor magnetic disk device |
| CN101004953A (en) * | 2006-01-18 | 2007-07-25 | 苹果电脑有限公司 | Disabling faulty flash memory dies |
| CN101482749A (en) * | 2008-01-11 | 2009-07-15 | 鸿富锦精密工业（深圳）有限公司 | Automatic addressing system of master device to slave device |
| CN102428455A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Data striping in a flash memory data storage device |
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