CN104092631B - Network-termination device and its control method - Google Patents
Network-termination device and its control method Download PDFInfo
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- CN104092631B CN104092631B CN201410373180.8A CN201410373180A CN104092631B CN 104092631 B CN104092631 B CN 104092631B CN 201410373180 A CN201410373180 A CN 201410373180A CN 104092631 B CN104092631 B CN 104092631B
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Abstract
A kind of network-termination device and its control method.Network-termination device includes at least two grid line connecting holes, a switched circuit, a watchdog circuit, a logic circuit and a process circuit.When the dimorphism wherein of the grid line connecting hole is into loop, switched circuit controls the first signal to form one first square wave state.If the first signal is the first square wave state, watchdog circuit controls a secondary signal to be located at the wavy state of a first level.If secondary signal is located at the wavy state of first level, logic circuit controls one the 3rd signal to be located at a predetermined level section.If the level of the 3rd signal is located at predetermined level section, switched circuit automatically cuts off the communication of switched circuit and process circuit.
Description
Technical field
The present invention relates to a kind of network-termination device and its control method, more particularly to one kind possesses several grid line connections
The network-termination device and its control method in hole.
Background technology
With the development of the network technology, network has been popularized in family, school, company's numbering and mechanism.Setting up network system
During system, various electronic installations can be linked to internet or LAN by network-termination device.
Network-termination device can possess several grid line connecting holes, for being linked to electronic installation after grid line grafting.
When setting up numerous and diverse network system, user may allow the interconnection of two grid line connecting holes accidentally (such as by single network line
Direct interconnection, or by multiple grid lines and at least a mediating device interconnects indirectly), and form loop (loop) (or ring
Return).Once there is loop, the signal exported can not obtain corresponding reply, and produce the loss of a large amount of packages.Such one
Come, it will ample resources is wasted, and other grid line connecting holes can also be affected.
The content of the invention
The invention relates to a kind of network-termination device and its control method, and it utilizes the mode of hardware controls so that
Loop can be detected, and then effectively be excluded.
According to an aspect of the present invention, a kind of network-termination device is proposed.Network-termination device includes at least two networks
Line connecting hole, a switched circuit, a watchdog circuit, a logic circuit and a process circuit.Switched circuit couples those networks
Line connecting hole.Switched circuit exports one first signal.When the dimorphism wherein of those grid line connecting holes is into loop, electricity is exchanged
Road controls the first signal to form one first square wave state.Watchdog circuit couples switched circuit.Watchdog circuit receives first
After signal, shielding is delayed to produce a secondary signal.If the first signal is the first square wave state, watchdog circuit control second
Signal is located at the wavy state of a first level.Logic circuits coupled switched circuit and watchdog circuit.Logic circuit receives the second letter
After number, one the 3rd signal is exported.If secondary signal is located at the wavy state of first level, logic circuit controls the 3rd signal pre- positioned at one
Determine level section.Process circuit couples switched circuit.If the level of the 3rd signal is located at predetermined level section, switched circuit is automatic
Cut off the communication of switched circuit and process circuit.When loop releases, the first signal is fixed level, house dog circuit output second
Signal reseting logic circuit, the state that the level of the 3rd signal is returned to before loop produces, the network equipment recover communication.
A kind of according to another aspect of the invention, it is proposed that control method of network-termination device.Network-termination device includes
At least two grid line connecting holes, a switched circuit, a watchdog circuit, a logic circuit and a process circuit.Switched circuit is defeated
Go out one first signal to watchdog circuit.Watchdog circuit exports a secondary signal to logic circuit.Logic circuit output one the
Three signals are to switched circuit.Control method comprises the following steps.Wherein two when those grid line connecting holes are connected to interconnection
When, switched circuit controls the first signal to form one first square wave state.If the first signal is the first square wave state, house dog
Circuits mask the first signal of delay so that secondary signal is located at the wavy state of a first level.If secondary signal is located at first level
Wavy band, logic circuit control the level of the 3rd signal to be located at a predetermined level section.If the level of the 3rd signal is positioned at predetermined
Level section, switched circuit automatically cut off the communication of switched circuit and process circuit.
Brief description of the drawings
Fig. 1 is the schematic diagram of network-termination device；
Fig. 2 is the thin portion circuit diagram of watchdog circuit and logic circuit；
Fig. 3 is the schematic diagram of the first signal, secondary signal and the 3rd signal；
When Fig. 4 is that loop occurs, the flow chart of the control method of network-termination device；
When Fig. 5 is that loop excludes, the flow chart of the control method of network-termination device.
Wherein reference：
1000：Network-termination device
110：Grid line connecting hole
120：Switched circuit
130：Watchdog circuit
140：Logic circuit
150：Process circuit
800：GMII
900：Grid line
C1：CLK pin
C2：CLRn pins
D1：D pins
L1：LOOPLED pins
P1：P4LinSta pins
Q1：Q pin
R1：RESET pins
R0、R0′：Resistance
S1：First signal
S2：Secondary signal
S3：3rd signal
S401~S404, S501~S504：Process step
T1、T2：Time point
W1：WDI pins
Specific embodiment
More preferably understand to have to foregoing invention and other side, preferred embodiment cited below particularly, and coordinate accompanying drawing, make
Describe in detail as follows：
Fig. 1 is refer to, it is the schematic diagram of Network Termination Type 1 000.Network Termination Type 1 000 is, for example, an ether number
(Ethernet over Coax, EOC) equipment is transmitted according to coaxial cable.Network Termination Type 1 000 connects including at least two grid lines
Connect hole 110, the watchdog circuit (watchdog circuit) 130, one of a switched circuit (switching circuit) 120, one
Logic circuit (logic circuit) 140 and a process circuit (processing circuit) 150.The logic of the present embodiment
Circuit 140 is, for example, to be realized by d type flip flop circuit (D flip flop circuit).
Each grid line connecting hole 110 can couple a grid line.Grid line connecting hole 110 is, for example, Registered Jack
45 (RJ45) connecting holes, RJ11 connectors, optical fiber connector, coaxial cable connector ....Switched circuit 120 couples those networks
Line connecting hole 110, with from outer received signal or to outside transmission signal.Switched circuit 120 be coupled to watchdog circuit 130,
Logic circuit 140 and process circuit 150.Switched circuit 120 exports one first signal S1 to watchdog circuit 130 and logic circuit
140.Logic circuit 140 is coupled to watchdog circuit 130.Watchdog circuit 130 exports a secondary signal S2 to logic circuit
140.Logic circuit 140 exports one the 3rd signal S3 to switched circuit 120.Switched circuit 120 is more controlling switched circuit 120
GMII (Media Independent Interface, MII) 800 between process circuit 150.Switched circuit
120th, watchdog circuit 130, logic circuit 140 and process circuit 150 are for example a chip respectively.
When setting up numerous and diverse network system, user may allow two grid line connecting holes 110 to interconnect accidentally (such as to pass through
The direct interconnection of same grid line 900, or by multiple grid lines and at least a mediating device interconnects indirectly), and form loop
(loop) (or loopback).Once there is loop, the signal exported can not obtain corresponding reply, and produce a large amount of packages
Lose.Thus, it will ample resources is wasted, and other grid line connecting holes 110 and Network Termination Type 1 000 are whole
The running of body can also be affected.
The present embodiment passes through the hardware such as switched circuit 120, watchdog circuit 130, logic circuit 140 and process circuit 150
Running so that Network Termination Type 1 000 is able to detect the generation of loop, to exclude the situation of loop as quickly as possible.
As shown in Fig. 2 it is the thin portion circuit diagram of watchdog circuit 130 and logic circuit 140.One of switched circuit 120
LOOPLED pins L1 is coupled to a resistance R0, and resistance R0 is coupled to one of watchdog circuit 130 WDI pins W1.Switched circuit
120 LOOPLED pins L1 is coupled to the CLK pin C1 of logic circuit 140.One of watchdog circuit 130 RESET pin R1 couplings
It is connected to one of logic circuit 140 CLRn pins C2.One of logic circuit 140 D pins D1 is coupled to a resistance R0 '.Resistance R0 ' couplings
It is connected to the high level of 3.3 volts (V).One of logic circuit 140 Q pin Q1 is coupled to one of switched circuit 120 P4LinSta and drawn
Pin P1.
Alleged first signal S1, secondary signal S2 and the 3rd signal S3 high level or low level refer to the first signal below
S1, the level of secondary signal S2 and the 3rd signal S3 in itself it is relatively high and low.First signal S1, secondary signal S2 and the 3rd letter
Number S3 high level is not necessarily referring to same level section；First signal S1, secondary signal S2 and the 3rd signal S3 low level are simultaneously
It is non-to refer to same level section.Similarly, the first signal S1 and secondary signal S2 square wave state is not necessarily referring to same waveform；
First signal S1 and secondary signal S2 horizontal wavy state is also not necessarily referring to same level section.
It is the first signal S1, secondary signal S2 and the 3rd signal S3 schematic diagram referring to Fig. 2 and Fig. 3, Fig. 3.
Before time point T1, when loop does not occur, LOOPLED pins L1 exports the first signal to WDI pins W1 and CLK pin C1
Horizontal wavy state is presented in S1.RESET pins R1 is exported to CLRn pins C2 secondary signal S2 and is formed square wave state.Namely
Say, secondary signal S2 (timeout) (being, for example, 1.4~2 seconds) during delay is shielded is high level, during reset delay
(being, for example, 200 milliseconds) is low level.Shielding delay can be described as frequency and covers delay, transmission delay or transmission delay again.
It refer to table 1, table 1 illustrates the CLRn pins C2 of logic circuit 140, CLK pin C1, D pin D1 and Q pin Q1
Relation.If the secondary signal S2 that CLRn pins C2 is inputted is located at low level, no matter CLK pin C1 and D pin D1 state,
The 3rd signal S3 that Q pin Q1 is exported will be located at low level.If the secondary signal S2 that CLRn pins C2 is inputted is positioned at high electricity
It is flat, and when the first signal S1 for being inputted of CLK pin C1 are horizontality, no matter D pins D1 state, Q pin Q1 are exported
The 3rd signal S3 will be located at eve state.So because secondary signal S2 is square wave state (i.e. shape at predetermined time intervals
Into low level), the 3rd signal S3 will be located at low level.Then, even if secondary signal S2 rises back high level, due to the first signal
S1 is still horizontality, and the 3rd signal S3 will be maintained at eve state, and be located at low level.
Table 1
When the 3rd signal S3 that P4LinSta pins P1 is inputted is located at low level, switched circuit 120 maintains switched circuit
120 with the communication of the GMII 800 of process circuit 150.
To sum up, when before time point T1, when loop does not occur, the first signal S1 is located at horizontality, will make the second letter
Number S2 is located at square wave state (forming low level at predetermined time intervals), and the 3rd signal S3 will be located at low level.Exchange electricity
State of the road 120 according to the 3rd signal S3, maintenance switched circuit 120 are logical with the GMII 800 of process circuit 150
Letter.
After time point T1, when loop occurs, LOOPLED pins L1 is exported to the of WDI pins W1 and CLK pin C1
Square wave state is presented in one signal S1, and the e.g. half period is the square wave of 400 milliseconds (or 800 milliseconds).Because rectangle is wavy
First signal S1 of state half period (being, for example, 400 or 800 milliseconds) is less than the shielding delay length (example of watchdog circuit 130
1.4~2 seconds in this way) so that RESET pins R1 is exported to CLRn pins C2 secondary signal S1 and is formed horizontal wavy state, and is held
It is continuous to be located at high level.
According to table 1, if the secondary signal S2 that CLRn pins C2 is inputted is continued in high level, and CLK pin C1
The the first signal S1 inputted has propradation (i.e. in square wave state by low level to high level), then according to D pins
D1 state (the present embodiment is 3.3 volts of high level), the 3rd signal S3 that Q pin Q1 is exported will be located at high level.
When the 3rd signal S3 that P4LinSta pins P1 is inputted is located at high level, switched circuit 120 automatically cuts off exchange
The communication of circuit 120 and the GMII 800 of process circuit 150.
To sum up, after time point T1, when loop occurs, the first signal S1 is located at square wave state (having propradation),
Secondary signal S2 is set to be continued in high level positioned at horizontal wavy state, and the 3rd signal S3 is located at high level.Switched circuit 120
The communication of switched circuit 120 and the GMII 800 of process circuit 150 can be automatically cut off.
When user has found that the communication of GMII 800 is cut off, you can exclude the situation of loop immediately.In the time
After point T2, when loop has excluded, the first signal S1 is located at horizontality, and secondary signal S2 will be made to be located at square wave state, and
3rd signal S3 will be located at low level.State of the switched circuit 120 according to the 3rd signal S3, maintain switched circuit 120 and processing
The communication of the GMII 800 of circuit 150.
In order to which how clear explanation the present embodiment realizes that loop is detected by way of hardware controls, below more with flow chart
Describe the control method of network-termination device in detail.Fig. 4 is refer to, when it is that loop occurs, the control of Network Termination Type 1 000
The flow chart of method processed.
First, in step S401, when wherein the two of those grid line connecting holes 110 are connected to interconnection, electricity is exchanged
Road 120 controls the first signal S1 to form one first square wave state.
Then, in step S402, first signal S1 of the shielding delay of watchdog circuit 130 so that secondary signal S2 is located at
The wavy state of one first level.
Then, in step S403, as described in Table 1, logic circuit 140 controls the 3rd signal S3 level predetermined positioned at one
Level section (e.g. higher than a predetermined value).
Then, in step s 404, switched circuit 120 automatically cut off switched circuit 120 and process circuit 150 media it is only
The communication of vertical interface 800.
Referring again to Fig. 5, when it is that loop excludes, the flow chart of the control method of Network Termination Type 1 000.Exist first
In step S501, as described in Table 1, after the grid line connecting hole 110 of two interconnection no longer interconnects, the control of switched circuit 120 first
Signal S1 forms one second horizontal wavy state.
Then, in step S502, watchdog circuit 130 controls secondary signal S2 to be located at one second square wave state.
Then, in step S503, as described in Table 1, logic circuit 140 controls the 3rd signal S3 not to be located at predetermined level area
Between (e.g. not higher than predetermined value).
Then, in step S504, switched circuit 120 maintains (such as automatically replying) switched circuit 120 and process circuit
The communication of 150 GMII 800.
In summary, the Network Termination Type 1 000 of the present embodiment can realize detecing for loop by way of hardware design
Survey, and when loop is detected, automatically cut off the communication of switched circuit 120 and process circuit 150, enable the user to discover
Carry out the exclusion of loop immediately afterwards.When loop excludes, Network Termination Type 1 000 is also able to maintain that switched circuit 120 and processing
The communication of circuit 150, for user's normal use.
Although the present invention is disclosed as above with preferred embodiment, it is not limited to the present invention.Skill belonging to the present invention
The technical staff in art field, without departing from the spirit and scope of the present invention, when various change and modification can be made.Therefore, originally
The protection domain of invention is worked as to be defined depending on appended claims protection domain institute defender.
Claims (10)
1. a kind of network-termination device, it is characterised in that the network-termination device includes：At least two grid line connecting holes；
One switched circuit, those grid line connecting holes are coupled, the switched circuit exports one first signal, when those grid lines connect
During wherein two interconnection in hole, the switched circuit controls first signal to form one first square wave state；
One watchdog circuit, the switched circuit is coupled, after the watchdog circuit receives first signal, shielding is delayed to produce one
Secondary signal, if first signal is the first square wave state, the watchdog circuit controls the secondary signal to be located at one first
Horizontal wavy state；
One logic circuit, the switched circuit and the watchdog circuit are coupled, after the logic circuit receives the secondary signal, output one
3rd signal, if the secondary signal is located at the wavy state of the first level, the logic circuit controls the 3rd signal predetermined positioned at one
Level section；And
One process circuit, the switched circuit is coupled, if the level of the 3rd signal is located at the predetermined level section, the switched circuit
Automatically cut off the communication of the switched circuit and the process circuit；
Wherein first signal is by the switched circuit simultaneous transmission to the watchdog circuit and the logic circuit, wherein logic electricity
Road is coupled between one of watchdog circuit RESET pins and the switched circuit.
2. network-termination device as claimed in claim 1, it is characterised in that positioned at first signal of the first square wave state
Half period be less than the watchdog circuit shielding delay length.
3. network-termination device as claimed in claim 1, it is characterised in that the logic circuit is a d type flip flop circuit, and this first
Signal be by one of switched circuit LOOPLED pins transmit to one of watchdog circuit WDI pins and the logic circuit it
One CLK pin, the secondary signal are to be transmitted to one of logic circuit CLRn to draw by one of watchdog circuit RESET pins
Pin, the 3rd signal are to be transmitted by one of logic circuit Q pin to one of switched circuit P4LinkSta pins.
4. network-termination device as claimed in claim 1, it is characterised in that the logic circuit is a d type flip flop circuit, the logic
One of circuit D pins are coupled to one 3.3 volts of level, and the shielding delay length of the watchdog circuit is 1.4~2 seconds.
5. network-termination device as claimed in claim 1, it is characterised in that when this two interconnection grid line connecting hole no longer
After interconnection, first signal is one second horizontal wavy state by the first square wave State Transferring；If first signal by this
One square wave State Transferring is the second horizontal wavy state, and the watchdog circuit controls the secondary signal to be located at one second square wave
State；If the secondary signal is located at the second square wave state, the logic circuit controls the level of the 3rd signal not to be located at should
Predetermined level section；If the level of the 3rd signal is not located at the predetermined level section, the switched circuit maintains the switched circuit
With the communication of the process circuit.
6. a kind of control method of network-termination device, it is characterised in that the network-termination device includes at least two grid lines
Connecting hole, a switched circuit, a watchdog circuit, a logic circuit and a process circuit, the letter of switched circuit output one first
Number to the watchdog circuit and the logic circuit, the watchdog circuit exports a secondary signal to the logic circuit, logic electricity
Road output one the 3rd signal to the switched circuit, control method includes：
When wherein two interconnection of those grid line connecting holes, the switched circuit controls first signal to form one first rectangle
Wavy state；
If first signal is the first square wave state, watchdog circuit shielding delay first signal so that this second
Signal is located at the wavy state of a first level；
If the secondary signal is located at the wavy state of the first level, the logic circuit controls the level of the 3rd signal predetermined positioned at one
Level section；And
If the level of the 3rd signal is located at the predetermined level section, the switched circuit automatically cuts off the switched circuit and the processing
The communication of circuit, wherein the logic circuits coupled is between one of watchdog circuit RESET pins and the switched circuit.
7. the control method of network-termination device as claimed in claim 6, it is characterised in that the first square wave state this
The half period of one signal is less than the shielding delay length of the watchdog circuit.
8. the control method of network-termination device as claimed in claim 6, it is characterised in that the logic circuit is a d type flip flop
Circuit, first signal are transmitted to one of watchdog circuit WDI pins and are somebody's turn to do by one of switched circuit LOOPLED pins
One of logic circuit CLK pin, the secondary signal be by one of watchdog circuit RESET pins transmit to the logic circuit it
One CLRn pins, the 3rd signal are to be transmitted to one of switched circuit P4LinkSta to draw by one of logic circuit Q pin
Pin.
9. the control method of network-termination device as claimed in claim 6, it is characterised in that the logic circuit is a d type flip flop
One of circuit, logic circuit D pins are coupled to one 3.3 volts of level, the shielding delay length of the watchdog circuit for 1.4~
2 seconds.
10. the control method of network-termination device as claimed in claim 6, it is characterised in that also include：
After the grid line connecting hole of this two interconnection no longer interconnects, the switched circuit controls first signal to form one second
Horizontal wavy state；
If first signal is the second horizontal wavy state by the first square wave State Transferring, the watchdog circuit control this
Binary signal is located at one second square wave state；
If the secondary signal is located at the second square wave state, the logic circuit controls the level of the 3rd signal not pre- positioned at this
Determine level section；And
If the level of the 3rd signal system is not located at the predetermined level section, the switched circuit maintains the switched circuit and the processing
The communication of circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410373180.8A CN104092631B (en) | 2014-07-31 | 2014-07-31 | Network-termination device and its control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410373180.8A CN104092631B (en) | 2014-07-31 | 2014-07-31 | Network-termination device and its control method |
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| Publication Number | Publication Date |
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| CN104092631A CN104092631A (en) | 2014-10-08 |
| CN104092631B true CN104092631B (en) | 2017-11-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201479095U (en) * | 2009-06-19 | 2010-05-19 | 厦门敏讯信息技术股份有限公司 | Startup and shutdown circuit |
| CN203645682U (en) * | 2013-12-04 | 2014-06-11 | 广东东研网络科技股份有限公司 | Active EOC terminal comprising exchange chip port loop monitoring circuit |
| CN203722657U (en) * | 2013-12-23 | 2014-07-16 | 武汉烽火网络有限责任公司 | Loop inspection circuit applicable to EOC system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6996732B2 (en) * | 2002-09-07 | 2006-02-07 | Micrologic, Inc. | Method of and apparatus for achieving “watch dog” functions in microcontrollers and microcomputers and the like, required to shut down for extended periods of time for energy-conservation purposes |
-
2014
- 2014-07-31 CN CN201410373180.8A patent/CN104092631B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201479095U (en) * | 2009-06-19 | 2010-05-19 | 厦门敏讯信息技术股份有限公司 | Startup and shutdown circuit |
| CN203645682U (en) * | 2013-12-04 | 2014-06-11 | 广东东研网络科技股份有限公司 | Active EOC terminal comprising exchange chip port loop monitoring circuit |
| CN203722657U (en) * | 2013-12-23 | 2014-07-16 | 武汉烽火网络有限责任公司 | Loop inspection circuit applicable to EOC system |
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|---|---|
| CN104092631A (en) | 2014-10-08 |
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