CN104064618A - CdTe cell with p-i-n structure and preparation method thereof - Google Patents
CdTe cell with p-i-n structure and preparation method thereof Download PDFInfo
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- 229910004613 CdTe Inorganic materials 0.000 title claims abstract 34
- 238000002360 preparation method Methods 0.000 title claims description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 355
- 239000000758 substrate Substances 0.000 claims abstract description 228
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 230000031700 light absorption Effects 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 123
- 239000007789 gas Substances 0.000 claims description 70
- 238000004544 sputter deposition Methods 0.000 claims description 59
- 229910052786 argon Inorganic materials 0.000 claims description 43
- 229910052738 indium Inorganic materials 0.000 claims description 43
- 229910052782 aluminium Inorganic materials 0.000 claims description 39
- 230000008569 process Effects 0.000 claims description 31
- 238000010438 heat treatment Methods 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims description 16
- 238000002207 thermal evaporation Methods 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 14
- 230000000694 effects Effects 0.000 claims description 14
- 238000005566 electron beam evaporation Methods 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910021389 graphene Inorganic materials 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 229910052797 bismuth Inorganic materials 0.000 claims description 6
- 239000005357 flat glass Substances 0.000 claims description 6
- 229910004609 CdSn Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium atom Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 claims description 3
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical class OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 2
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 238000010894 electron beam technology Methods 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 abstract 1
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 265
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 78
- 239000010408 film Substances 0.000 description 64
- 238000004062 sedimentation Methods 0.000 description 44
- 239000011521 glass Substances 0.000 description 43
- 230000001105 regulatory effect Effects 0.000 description 36
- 238000012545 processing Methods 0.000 description 27
- 230000015572 biosynthetic process Effects 0.000 description 20
- 239000010445 mica Substances 0.000 description 14
- 229910052618 mica group Inorganic materials 0.000 description 14
- 230000009466 transformation Effects 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229910007709 ZnTe Inorganic materials 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 238000013082 photovoltaic technology Methods 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000313 electron-beam-induced deposition Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 3
- 239000004926 polymethyl methacrylate Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000004821 distillation Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 230000011712 cell development Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000003245 coal Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- HVMJUDPAXRRVQO-UHFFFAOYSA-N copper indium Chemical compound [Cu].[In] HVMJUDPAXRRVQO-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000004870 electrical engineering Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000013112 stability test Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000003764 ultrasonic spray pyrolysis Methods 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03925—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including AIIBVI compound materials, e.g. CdTe, CdS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/543—Solar cells from Group II-VI materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a CdTe solar cell with a p-i-n structure. The CdTe solar cell comprises a substrate, a transparent conductive electrode layer, a CdS n-type semiconductor layer, a CdTe intrinsic light absorption layer, a broad-band gap ternary II-VI group semiconductor p<+> layer, a ZnO:Al or In2O3:Sn n<+> layer and a metal electrode layer sequentially from the bottom up. The CdTe solar cell with the p-i-n structure is prepared by low-temperature magnetron sputtering.
Description
Technical field
The present invention relates to a kind of CdTe solar cell and preparation method thereof.
Background technology
As a kind of clean energy resource, that solar energy has is rich, the easily property obtained, recyclability and nonstaining property, effective utilization of solar energy is effective utilization of photovoltaic solar cell especially, is expected to solve the problems such as global energy shortage, environmental pollution, climate warming.Solar cell is if substitute traditional energy and must reduce costs.Thin-film solar cells has the advantage that material usage is few, low-cost, be easy to large area production, the battery that has become the research and development of photovoltaic industrial emphases and produced.In thin-film solar cells, what reached industrial large-scale production is mainly that amorphous silicon (a-Si), copper indium are sowed selenium (CIGS) and cadmium telluride (CdTe) solar cell.CdTe solar cell is one of best, efficient, low-cost photovoltaic technology of current thin film solar cell development prospect.CdTe assembly production cost is 0.55 dollar/watt, is that in current known large-scale application photovoltaic technology, production cost is minimum.The CdTe commercial modules peak efficiency of the U.S.'s the first solar energy (First Solar) is 17.0%, and the highest energy conversion efficiency of laboratory small size CdTe battery is 20.4%, also has a certain distance with unijunction CdTe theoretical efficiency (28-29%).Visible, CdTe cell conversion efficiency still has certain room for promotion, and technical development potentiality are still very large.CdTe is II
b-VI
afamily's binary compound, is a kind of direct gap semiconductor material, has room temperature direct band gap width Eg=1.5eV, high optical absorption coefficient (visible-range >5 * 10 of mating very much with solar spectral
5cm
-1, the thick CdTe film of 2 μ m just can absorb the incident light of the 600nm that is greater than 99%), high stability, low-power temperature coefficient (～-0.21%/℃), good low light level characteristic, without excellent properties such as intrinsic photo attenuation effect, environment friendly.In whole life cycle, comprise that raw material extraction, purification, assembly preparation, assembly are used, assembly is processed and assembly reclaims life cycle management, the cadmium discharge capacity of CdTe solar cell is only 0.3646g/GWh, far below the 4.900g/GWh of coal electricity.
Average level according to current large area assembly conversion efficiency, the conversion efficiency of every raising 1%, just be equivalent to reduce by 10% production cost on existing basis, be expected to make CdTe battery general first become can with the photovoltaic technology of conventional electric power Cost Competition, promote the large-scale application of photovoltaic clean energy resource.Therefore, the conversion efficiency that improves CdTe photovoltaic device not only has important scientific meaning, has too direct economic benefit, and Jiang Wei China wins leadership at compound semiconductor film photovoltaic sciemtifec and technical sphere.At present, Deng Duosuo R&D institution of China CAS Electrical Engineering Research Institute has all opened up the research of CdTe thin-film solar cells.The electrician of Chinese Academy of Sciences institute, since within 2010, carrying out magnetron sputtering method and preparing CdTe hull cell, has obtained 14.26% transformation efficiency so far on the thick CdTe polycrystal film of 2 μ m battery.
At present, the main research purpose of CdTe battery device is to improve its transformation efficiency, improve the open circuit voltage (Voc) that its transformation efficiency must improve CdTe battery, because open circuit voltage is the key factor that determines transformation efficiency.The band gap of CdTe is 1.50eV, and the band gap of GaAs is 1.47eV, and both are more or less the same, and still, the open circuit voltage of CdTe polycrystal film battery is but than the low 230mV nearly of the open circuit voltage of GaAs polycrystal film battery.Low open circuit voltage has reduced the transformation efficiency of CdTe polycrystal film solar cell.Low open circuit voltage is mainly (to approach 10 because of the low carrier lifetime (approaching 1ns) of CdTe, low hole concentration
14cm
-3) and back of the body contact berrier.
Because CdTe exists self compensation effect, obtain highly doped p-type CdTe (the CdTe hull cell hole concentration of conventionally mixing copper also only has～10
14-10
15cm
-3, approach eigenstate) be difficult to.The p-type doping of CdTe is often by realizing to impurity such as CdTe diffusion inside Cu, Sb from back contact, and that use is metal Cu conventionally, but metal Cu tends to cause stability test problem.CdTe surface deposition metal is as current collector, because CdTe work function is up to 4.86eV, considerably less with the metal that its formation good ohmic contacts.Therefore, normally used back contact tends to form ties contrary Schottky barrier with CdS/CdTe, reduces the open circuit voltage of battery.The theoretical open circuit voltage of CdTe solar cell can reach 1.2V, and its high open circuit voltage only surpasses 900mV at present, also has a certain distance with theoretical open circuit voltage.Therefore, need to improve the open circuit voltage of CdTe polycrystal film battery.
James Sites in 2006, Jun Pan[Strategies to increase CdTe solar-cell voltage, Thin Solid Films2007,515,6099-6102] propose to improve by two kinds of methods the open circuit voltage of CdTe: a kind of is carrier concentration and the life-span that increases CdTe, and another kind of method is to increase one deck electron reflection layer in back of the body contact.The carrier concentration and the life-span that increase CdTe need to start with from material, therefore improve the technology path of the Voc of CdTe battery and often absorbed layer material are furtherd investigate, to obtain the p-type CdTe of high-dopant concentration.Can, by CdTe polycrystalline material is started with, by increasing CdTe carrier concentration and life-span, increase the open circuit voltage of battery device.Increase carrier lifetime and can increase open circuit voltage and fill factor, curve factor, approaching of the fill factor, curve factor of the CdTe battery device of large carrier lifetime and GaAs battery, the diode quality factor is suitable, but open circuit voltage is but limited by the separation of quasi-Fermi level, increases carrier concentration raising open circuit voltage and there is limitation.Therefore, only rely on the raising of carrier lifetime open circuit voltage can not be risen to very high value.On the other hand, can improve open circuit voltage by increasing carrier density, but increase carrier concentration can reduce the width of space charge region, the diffusion length that the space charge region width requirement of reduction is large and high carrier lifetime, to can reasonably collect photo-generated carrier.Increase carrier density and carrier lifetime simultaneously, need to reduce complex centre.But in CdTe battery device, because CdS and CdTe interface exist defect, interface is compound is unescapable.Visible, the open circuit voltage that list improves CdTe battery from material angle has certain difficulty, and is not easy to realize.
At present, traditional CdTe solar battery structure is p-n junction structure, and as shown in Figure 1, traditional CdTe solar cell has substrate, transparency conductive electrode layer, CdS N-shaped semiconductor layer, and CdTe light absorbing zone is also p layer simultaneously, metal electrode layer.During tradition p-n junction structure C dTe solar cell working, light enters CdTe light absorbing zone from CdS semiconductor layer one side.CdS is N-shaped semiconductor, and CdTe is p-type semiconductor.Minority carrier life time short (τ <10ns) in polycrystalline CdTe film, make the thickness of CdTe semiconductor layer of the CdTe polycrystal film battery of traditional p-n junction structure be generally 2-10 μ m, tens times of N-shaped CdS semiconductor layer thickness, and because the p-type of CdTe semiconductor layer in battery is very weak, conventionally space charge region can extend to 3-4 μ m, makes in the Dou depletion region, region of photo-generated carrier generation.That is to say that in CdTe, the collection of photo-generated carrier is to rely on electrical drift rather than diffusion to realize.
On the other hand, tellurium Te is one of minimum element of content in the earth's crust, and this is another bottleneck of restriction CdTe solar cell fast development.The supply of tellurium at present is almost completely refined and is obtained from the byproduct of copper mine and the generation of lead ore refining process, the Te total output in the whole world in 2008 only has 480 tons, even if adopt the higher technology of extraction efficiency, this output be it is generally acknowledged also can only reach 1500 tons/year of left and right.The conclusion that various analyses draw for the production scale LIMIT ESTIMATION of CdTe photovoltaic technology disagrees, the most conservative estimation of Martin Green is about about 10GWp/, and more optimistic estimation is at 20-100GWp/, and will after the year two thousand twenty, start reached zero growth by current growth rate.
Can, by reducing the thickness of CdTe, reduce the use of CdTe.CdTe is a kind of desirable light absorption semiconductor, and visible-light absorptivity reaches 10
4– 10
5cm
-1, only need 0.1 μ m just can absorb at least 63% visible ray (wavelength <826nm).U.S. Univ.of Toledo adopts the method for magnetron sputtering to prepare the CdTe battery that thickness is only 0.5 μ m and 0.75 μ m, and conversion efficiency has reached respectively 11% and 12.5%.
Yet there is a basic physical problem in ultra-thin CdTe solar cell, the weak diode effect both having caused due to the spatial heterogeneity of CdTe semiconductor layer thickness or composition.This is to be all polycrystal film owing to forming p-type CdTe semiconductor layer and the N-shaped CdS semiconductor layer of junction field in battery, and whole device is equivalent to and is numerously arranged side by side, the micro photoelectric diode of link in parallel.There is certain microcosmic heterogeneity in polycrystal film thickness, what meeting was random causes front and back electrode layer nearer than other place with the distance of junction interface in battery somewhere, at regional area, form miniature weak diode.Due to miniature weak diode to open the normal diode of pressure ratio little, the voltage of the normal light electric diode in parallel with it existing when periphery is during in maximum power point, the weak diode of same voltage status is just in time in forward conduction state computation surface, and weak diode can be engulfed the photogenerated current in 1mm to 1m scope around in the thick CdTe battery of traditional 2 – 10 μ m.Coverage surpasses 10 of self size
3-10
6doubly.Also be to cause CdTe solar cell to open an important microcosmic mechanism of drops.
Visible, if reduce merely the thickness of CdTe semiconductor layer, although can reduce the semi-conductive use of CdTe, tend to reduce the open circuit voltage of CdTe solar cell.James Sites professor [the Kuo-Jui Hsiao of U.S. Colorado State Univ., James R.Sites, " ELECTRON REFLECTOR STRATEGY FOR CdTe SOLAR CELLS ", Proceedings of34th IEEE Photovoltaic Specialist Conference, 001846-001850,2009; K.-J.Hsiao, J.R.Sites, " Electron reflector to enhance photovoltaic efficiency:application to thin-film CdTe solar cells ", Prog.Photovolt:Res.Appl., 20,486 – 489,2012.] propose recently between CdTe light absorbing zone and metal electrode layer, to use the structure that can form electronics back reflection potential barrier, the structure that simultaneously reduces the thickness of CdTe semiconductor layer improves battery efficiency.They find by a large amount of device simulation research, if the electronics back reflection potential barrier that is 0.2eV at CdTe solar cell CdTe semiconductor layer and metal electrode layer contact interface height of formation can be that the open circuit voltage of the CdTe solar cell of 10 μ m is brought up to 900mV from current～860mV by thickness; Further reduce thickness to the 2 μ m of CdTe light absorption semiconductor layer, more than open circuit voltage can being brought up to 940mV.If further reduce thickness to the 1 μ m left and right of CdTe light absorption semiconductor layer, and use the optical back antistructure of reflectivity 100%, even if the hole concentration of CdTe light absorption semiconductor layer is less than 10
14cm
-3, open circuit voltage also may be brought up to 1V, and transformation efficiency reaches 20%.
Although James Site has proposed use Cd
1-xzn
xte, Cd
1-xmg
xthe technology path that Te broad-band gap ternary II-VI family semiconductor obtains suitable electronics back reflection potential barrier and reduces CdTe light absorbing zone thickness obtains higher open circuit voltage, but at actual process technology path with will not propose substantial suggestion on the physical problem facing.
Along with the reduction of CdTe light absorbing zone thickness, the probability that forms pin hole in CdTe light absorbing zone becomes large; And the weak diode effect that the heterogeneity of CdTe light absorbing zone thickness causes can become more outstanding.Therefore prepare thickness lower than the CdTe light absorbing zone of 1.0 μ m, need to obtain size much smaller than the polycrystalline particle of average thickness.What in the production at present of tradition p-n junction CdS/CdTe solar cell and scientific research, the most often adopt is physical vapour deposition (PVD) and near space sublimating technologe; these two kinds of deposition technique substrate temperatures reach 600 ℃ of left and right; be high temperature deposition technology, the CdTe light absorbing zone film crystal grain conventionally obtaining is all between 5-10 μ m.And the another kind of normal method adopting is magnetron sputtering technique, underlayer temperature is lower than 600 ℃, but can acquisition and physical vapour deposition (PVD) and approaching transformation efficiency and the open circuit voltage of near space sublimating technologe.In low temperature magnetic sputtering deposition technique process, there is the bombardment of plasma to semiconductor layer surface, can make low temperature atom obtain enough kinetic energy and move to energy position.The semiconductor layer polycrystal film crystallite dimension of magnetron sputtering only has 0.5 μ m, crystal grain prepared by Magnetron Sputtering Thin Film can be realized the microcosmic evenness that thickness is less than 1 μ mCdTe light absorbing zone polycrystal film surface, thereby greatly reducing the probability that weak diode effect occurs, physical vapour deposition (PVD) and near space distillation deposition process have obvious advantage relatively.
Patent CN102891204A proposes a kind of CdTe thin-film solar cells of n-i-p structure, but it is lower substrat structure, and intrinsic light absorbing zone and p-type semiconductor layer be all CdTe, and the thickness of CdTe is thicker.
Summary of the invention
The object of the invention is in order to overcome solar cell open circuit voltage and the transformation efficiency of existing p-n junction CdTe structure lowly, and the thick shortcoming of CdTe semiconductor layer thickness of using, proposes CdTe solar cell of a kind of p-i-n structure and preparation method thereof.
The CdTe solar cell of p-i-n structure of the present invention can make the thickness reduction of CdTe intrinsic light absorbing zone below 1 μ m, but still can reach open circuit voltage and 20% above transformation efficiency more than 1V.The present invention is by magnetron sputtering preparation method, realize the preparation of N-shaped semiconductor layer in p-i-n battery structure, intrinsic semiconductor layer and p-type semiconductor layer, can, in CdTe intrinsic light absorbing zone thickness reduction, improve open circuit voltage and the transformation efficiency of CdTe solar cell.And magnetron sputtering preparation method of the present invention can also further reduce the cost of CdTe solar cell.
The CdTe solar battery structure of p-i-n structure of the present invention is as follows:
Described CdTe battery comprises transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, the broad-band gap ternary II-VI semiconductor p of family
+layer, ZnO:Al or In
2o
3: Sn n
+increase anti-tunnel layer, and metal electrode layer.On described substrate, be on transparency conductive electrode layer, transparency conductive electrode layer for CdS N-shaped semiconductor layer, on CdS N-shaped semiconductor layer, be CdTe intrinsic light absorbing zone, on CdTe intrinsic light absorbing zone, be the broad-band gap ternary II-VI semiconductor p of family
+layer, the broad-band gap ternary II-VI semiconductor p of family
+on layer, be ZnO:Al or In
2o
3: Sn n+ increase anti-tunnelling layer by layer, ZnO:Al or In
2o
3: it is metal electrode layer that Sn n+ increases on anti-tunnel layer.
Described broad-band gap ternary II-VI family semiconductor is such as Cd
1-xzn
xte or Cd
1-xmg
xte.
The thickness of the CdTe intrinsic light absorbing zone of described CdTe battery is 0.1-1.0 μ m, and under illumination, portion produces photo-generated carrier within it.
CdS in described CdTe battery is N-shaped semiconductor layer, and broad-band gap ternary II-VI family semiconductor is p-type semiconductor layer, such as: Cd
1-xzn
xte, Cd
1-xmg
xte.CdS N-shaped semiconductor layer and broad-band gap II-VI semiconductor p-type layer provide p-n junction, and the effect such as separation, transmission of the photo-generated carrier producing in CdTe intrinsic light absorbing zone is provided.
P-i-n structure C dTe solar cell of the present invention can obtain good light trapping structure from two aspects.CdTe intrinsic light absorbing zone thickness is less than traditional p-n junction structure CdTe device of 1.0 μ m, and its loss in efficiency is mainly derived near the compound and incomplete absorption near infrared band back of the body metal electrode layer.In p-i-n solar cell device, except selecting suitable electronics (few son) back reflection field structure, reduce to carry on the back the compound of metal electrode place, also need to adopt suitable light trapping structure to reduce deep layer absorption loss water.This is the key that improves ultra-thin CdTe battery open circuit voltage and reduce the loss of slimline battery short circuit current as far as possible.First, p-i-n structure C dTe solar cell of the present invention adopts the method for magnetron sputtering to prepare CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, the broad-band gap ternary II-VI semiconductor p of family
+layer, ZnO:Al or In
2o
3: Sn n
+increase and instead then wear layer.By magnetron sputtering, can obtain the CdS/CdTe interface of porous. before entering CdTe intrinsic light absorbing zone, be scattered, be increased in the light path in absorbed layer.Secondly, p-i-n structure C dTe solar cell of the present invention is at the broad-band gap ternary II-VI semiconductor p of family
+layer and simultaneously for inserting ZnO:Al or the In of N-shaped between electrode layer and the metal electrode layer in reflector
2o
3: Sn n
+increase and instead then wear layer, further realized good light trapping effect.
The CdTe solar cell of p-i-n structure of the present invention is used broad-band gap ternary II-VI family semiconductor to coordinate ZnO:Al or In in the middle of the metal electrode layer of CdTe intrinsic light absorbing zone
2o
3: Sn n
+increase the composite construction of instead then wearing layer, such as: Cd
1-xzn
xte or Cd
1-xmg
xte/ZnO:Al or In
2o
3: Sn, the simultaneously function of electron gain back reflection field and back reflection light trapping structure.Broad-band gap II-VI family semiconductor, such as: ZnTe is broad-band gap II-VI family semiconductor, and band gap width is 2.26eV, for visible ray, is transparent, forms broad-band gap II-VI family semiconductor with CdTe, such as: Cd
1-xzn
xte semiconductor, can obtain the semiconductor of band gap between 1.5-2.26eV.This ternary semiconductor layer, as the back of the body contact transition zone of CdTe intrinsic light absorbing zone, can play and increase the effect of instead then wearing layer.The more important thing is, the work function of ZnTe and CdTe are very approaching, are respectively 5.79eV and 5.72eV, almost consistent.Therefore, to broad-band gap II-VI family semiconductor, such as: the p-type doping of ZnTe layer can directly cause the rising of the relative CdTe of its top of valence band, and at conduction band, forms the back reflection potential barrier of relative CdTe, for reflecting light induced electron.Near the charge carrier of metal electrode be can effectively avoid like this carrying on the back compound, open circuit voltage and fill factor, curve factor improved.ZnTe is the II-VI semiconductor that easily carries out p-type doping, adds Zn can improve the semi-conductive doping ability of CdTe in CdTe semiconductor, more easily obtains p-type semiconductor.Alternative p-type doped chemical comprises the shallow energy level acceptor impurity in these CdTe of N, P and ZnTe, and the conventional p-type impurity of CdTe battery such as Cu, Sb, Bi, P.Nitrogen N and phosphorus P doping can be by sneaking into the nitrogen N of proper proportion in rf magnetron sputtering working gas Ar
2or phosphine PH
3realize, the target that other elements can contain these impurity by sputter obtains corresponding doping, such as mixing the elements such as Cu, P, Sb, Bi.CdTe and broad-band gap ternary II-VI family semiconductor, such as: Cd
1-xzn
xte, Cd
1-xmg
xte contact can effectively reduce the lattice mismatch of interface, reduces near the recombination center concentration of back electrode.
In the CdTe solar cell of p-i-n structure of the present invention, at the broad-band gap ternary II-VI semiconductor layer of p-type be to insert ZnO:Al or the In of N-shaped between the metallic reflector of electrode simultaneously
2o
3: layer is instead worn in Sn increasing then.Aspect optical property, can be by regulating ZnO:Al or In
2o
3: Sn increases the anti-thickness of then wearing layer and obtains the highest near infrared light reflectivity at back of the body metal electrode interface.N-shaped ZnO:Al or In
2o
3: Sn increasing is instead then worn between layer and p-type broad-band gap ternary II-VI family material layer and is formed p
+/ n
+the double layer tunneling structure of type, helps hole transmission to metal electrode layer through back electrode interface from CdTe.
Although the thickness of battery CdTe of the present invention is only 0.1-1.0 μ m, more than open circuit voltage still can reach 1V, transformation efficiency can reach more than 20%.Can greatly reduce the cost of CdTe battery, the transformation efficiency of raising CdTe polycrystal film battery.
In magnetron sputtering process of the present invention, in the Ar gas passing into, sneak into the gas containing N and P, preparation CdTe battery.Magnetically controlled sputter method can be realized low-temperature epitaxy, can well control the speed of growth, effectively controls the size of polycrystal film crystal grain, and the surface roughness of controlling polycrystal film.The crystal grain of magnetron sputtering polycrystal film can guarantee the microcosmic evenness of the ultra-thin CdTe intrinsic light-absorption layer film surface of thickness≤1 μ m, thereby greatly reducing the probability that weak diode effect occurs, gas-phase transport and deposition and near space distillation deposition process have obvious advantage relatively.
Preparation method of solar battery of the present invention specifically describes as follows:
1, clean substrate;
2, at Grown transparency conductive electrode layer;
3, on the transparency conductive electrode layer on substrate, grow successively CdS N-shaped semiconductor layer and CdTe intrinsic light absorption semiconductor layer;
4, there iing CdCl
2in the atmosphere of steam, CdS N-shaped semiconductor layer and the CdTe intrinsic light absorption semiconductor layer of preparation are carried out to annealing in process;
5, through CdCl
2on CdTe intrinsic light absorption semiconductor layer after annealing in process, by magnetically controlled sputter method, deposit successively broad-band gap II-VI semiconductor p
+layer and ZnO:Al or In
2o
3: Sn n
+increase and instead then wear layer.In magnetron sputtering process, in the Ar passing into, sneak into the gas containing N and P, at the semiconductor p of broad-band gap II-VI family
+in wide bandgap layer, mix nitrogen (N) or phosphorus (P), or the mode of diffusion after adopting is mixed the p-type impurity such as copper (Cu) or phosphorus (P) or dysprosium (Sb) or bismuth (Bi) in broad-band gap II-VI family semiconductor wide bandgap layer.
6, at ZnO:Al or In
2o
3: Sn n
+increase and instead then wear a layer surface deposition metallic conduction electrode layer.
So far make the CdTe solar cell of described p-i-n structure.
In described step 1, described substrate can be rigid substrate, or flexible substrate.
Described step 2 is growth transparency conductive electrode layers, and it act as derivation electronics.Transparent conductive film can be In
2o
3: Sn or ZnO:Al or ZnO:B or In
2o
3: Mo or In:ZnO or Graphene or SnO
2: F or Cd
2snO
4deng.The technique of growth transparent conductive film can adopt magnetron sputtering method, pulsed laser deposition technique, ultrasonic spray pyrolysis, molecular beam epitaxy, glue method gel method, chemical vapour deposition technique.The thickness of conductive electrode layer is 0.3-1500nm.
The method of operation of described step 3 is: on the position of magnetron sputtering stove placement substrate, put the substrate of having prepared transparency conductive electrode layer, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and intensification makes underlayer temperature remain on 25-600 ℃.When back end vacuum arrives 10
-3below Pa, start sputter CdS semiconductor layer.The sputtering condition of CdS semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber.When the thickness of the CdS semiconductor layer of institute's sputter is 10-100nm on substrate, stop the preparation of CdS semiconductor layer.Substrate is turned to over against the position of CdTe target, start sputter CdTe semiconductor layer.The sputtering condition of CdTe semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber.When the CdTe semiconductor layer thickness of institute's sputter on substrate reaches the thickness 0.1-1 μ m of setting, the thickness of CdTe layer is surveyed by online film thickness measuring equipment.Stop the preparation of CdTe semiconductor layer, stop, to substrate heating, when underlayer temperature is reduced to room temperature, taking out the substrate that has deposited CdS and CdTe semiconductor layer simultaneously.
In described step 4, at CdCl
2in atmosphere to preparation CdS and CdTe semiconductor layer carry out annealing in process, at 300-500 ℃ to CdS N-shaped semiconductor layer and CdTe intrinsic light absorption semiconductor layer annealing in process 5-120min.Annealing can adopt wet method or dry method.The technical process of wet method annealing is as follows: CdCl
2saturated methanol solution evenly drop on CdTe intrinsic light absorption semiconductor layer, CdTe intrinsic light absorption semiconductor layer is carried out to annealing in process.The technical process of dry method annealing is as follows: CdCl
2evenly be placed on sheet glass, then apart from this sheet glass 1-5mm place, placing the substrate with CdTe intrinsic light absorption semiconductor layer, CdSn type semiconductor layer and transparency conductive electrode layer, CdTe half intrinsic light absorption conductor layer is over against there being CdCl
2sheet glass, then CdSn type semiconductor layer and CdTe intrinsic light absorption semiconductor layer are carried out to annealing in process.
The method of operation of described step 5 is: on the position of magnetron sputtering stove placement substrate, put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the underlayer temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on the scope of 25-600 ℃.When back end vacuum arrives 10
-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family
+layer.The broad-band gap ternary II-VI semiconductor p of family
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar or Ar and N in magnetron sputtering chamber
2, or Ar and PH
3, gas flow rate 10-100sccm, chamber pressure 0.1-10Pa.As the broad-band gap ternary II-VI semiconductor p of family
+when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family
+the preparation of layer.Or the complete broad-band gap ternary of the sputter II-VI semiconductor p of family
+after layer, being coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, the broad-band gap ternary II-VI semiconductor p of family
+the substrate of layer takes out, and then passes through electron beam or thermal evaporation at the broad-band gap ternary II-VI semiconductor p of family
+cu or P or the Sb of growth 1-20nm on layer
2te
3or Bi
2te
3, then in quick anneal oven, 50-600 ℃ of temperature range, to spread, the time of diffusion is 0.1-120min.Substrate is turned to over against ZnO:Al or In
2o
3: the position of Sn target, starts sputter ZnO:Al or In
2o
3: Snn
+layer.ZnO:Al or In
2o
3: Sn n
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber.ZnO:Al or the In of institute's sputter on substrate
2o
3: Sn n
+when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In
2o
3: Sn n
+the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.
Or put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone on the position of magnetron sputtering stove placement substrate, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the substrate temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on 25-600 ℃.When back end vacuum arrives 10
-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family
+layer.The broad-band gap ternary II-VI semiconductor p of family
+the sputtering condition of layer is: target is the broad-band gap ternary II-VI family semiconductor layer that mixes the materials such as Cu or P or Sb or Bi, such as: Cd
1-xzn
xte or Cd
1-xmg
xte, underlayer temperature 25-600 ℃ passes into high-purity Ar gas flow rate 10-100sccm in magnetron sputtering chamber, chamber pressure 0.1-10Pa.As the broad-band gap ternary II-VI semiconductor p of family
+when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family
+the preparation of layer.Substrate is turned to over against ZnO:Al or In
2o
3: the position of Sn target, starts sputter ZnO:Al or In
2o
3: Sn n
+layer.ZnO:Al or In
2o
3: Sn n
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber.ZnO:Al or the In of institute's sputter on substrate
2o
3: Sn n
+when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In
2o
3: Sn n
+the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.
The method of operation of described step 6 is: by thermal evaporation or electron beam at ZnO:Al or In
2o
3: Sn n
+layer increases instead wears the metal electrode layer that layer upper evaporation thickness is greater than 5nm then, and the thickness of metal electrode layer records by quartz crystal.
So far, obtain the CdTe solar cell of p-i-n structure of the present invention.
The CdTe solar cell of p-i-n structure of the present invention is compared tool with traditional p-n junction structure CdTe polycrystal film solar cell and is had the following advantages:
The intrinsic layer of battery structure of the present invention is CdTe, and CdTe light absorption intrinsic thickness is only 0.1-1.0 μ m, and thickness obtains by online film thickness measuring equipment, has greatly reduced the use of CdTe material.
Battery structure of the present invention is p-i-n structure, preparation method is magnetically controlled sputter method, can obtain enough little semiconductor layer film crystal grain, can characterize by SEM the structure of semiconductor layer film crystal grain, guarantee the quality of intrinsic i layer film, can guarantee the microcosmic evenness on ultra-thin CdTe (≤1 μ m) light absorbing zone surface, thereby greatly reduce the probability that weak diode effect occurs, physical vapour deposition (PVD) and near space sublimating technologe have obvious advantage relatively.
Low temperature magnetic sputtering that the present invention adopts is prepared p-i-n structure, can obtain good light trapping structure.Adopt the method for magnetron sputtering to prepare each layer of semiconductor layer of p-i-n, can obtain the CdS/CdTe interface of porous, by FIB, process section, by SEM, observe, before light enters CdTe light absorption intrinsic layer, be scattered, be increased in the light path in absorbed layer.Secondly, at the broad-band gap ternary II-VI semiconductor p of family
+layer and simultaneously insert ZnO:Al or In between electrode and the metal level in reflector
2o
3: Snn+ type increases instead wears layer then, increases the anti-layer of then wearing and can play good light trapping effect, further reaches effective light trapping effect.
The CdTe solar cell of p-i-n structure of the present invention adopts the mode of reactive sputtering at the broad-band gap ternary II-VI semiconductor p of family
+in layer, mix nitrogen (N) or phosphorus (P), or the mode of diffusion after adopting is mixed the p-type impurity such as copper (Cu) or phosphorus (P) or dysprosium (Sb) or bismuth (Bi).
The present invention adopts the CdTe solar cell of p-i-n structure, and more than its open circuit voltage is expected to reach 1V, transformation efficiency is expected to reach more than 20%.
Accompanying drawing explanation
Fig. 1 is the structural representation of the CdTe thin-film solar cells of traditional p-n junction structure, in figure: 1-1 substrate, 1-2 transparency conductive electrode layer, 1-3CdS N-shaped semiconductor layer, 1-4CdTe intrinsic light absorbing zone, 1-5 metal electrode layer.
Fig. 2 is the structural representation of the CdTe solar cell of p-i-n structure of the present invention, in figure: 2-1 substrate, 2-2 transparency conductive electrode layer, 2-3CdS N-shaped semiconductor layer, 2-4CdTe intrinsic light absorbing zone, the 2-5 broad-band gap ternary II-VI semiconductor p of family
+layer, 2-6ZnO:Al or In
2o
3: Sn n
+layer, 2-7 metal electrode layer.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.
Described CdTe battery comprises transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe intrinsic light absorbing zone 2-4, the broad-band gap ternary II-VI semiconductor p of family
+layer 2-5, ZnO:Al or In
2o
3: Sn n
+increase anti-tunnel layer 2-6, and metal electrode layer 2-7.On described substrate 2-1, be the upper CdS N-shaped semiconductor layer 2-3 of being of transparency conductive electrode layer 2-2, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3 is upper is CdTe intrinsic light absorbing zone 2-4, and CdTe intrinsic light absorbing zone 2-4 is upper is the broad-band gap ternary II-VI semiconductor p of family
+layer 2-5, the broad-band gap ternary II-VI semiconductor p of family
+layer 2-5 is upper is ZnO:Al or In
2o
3: Sn n+ increases anti-tunnelling 2-6, ZnO:Al or In layer by layer
2o
3: it is metal electrode layer 2-7 that Sn n+ increases anti-tunnel layer 2-6 upper.
Embodiment 1
First high-purity ZnO:Al target of 99.999% is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and be heated to 200 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, opens radio-frequency power supply, and regulating this output power of power supply is 180W, and the distance between target and glass substrate is 11cm, ZnO:Al transparency conductive electrode layer (TCO) 2-2 that sputtering sedimentation 1.0 μ m are thick under this technique.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and glass substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 10nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and glass substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 100nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 300 ℃, and the processing time is 5min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 1nm under this technique
1-xzn
xte semiconductor layer 2-5, then turns to ZnO:Al the position of substrate, and pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate is 11cm, the ZnO:Al n that sputtering sedimentation 1nm is thick under this technique
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, ZnO:Al n
+layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, ZnO:Aln
+layer takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at ZnO:Al n
+the Mg metal electrode layer 2-7 that layer 2-6 surface deposition thickness is 200nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Embodiment 2
First high-purity ZnO:B target of 99.999% is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 is sent into the vacuum chamber of magnetron sputtering apparatus, and remain on 25 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and Ar flow velocity is 10sccm,, open radio-frequency power supply, regulating this output power of power supply is 140W, distance between target and glass substrate 2-1 is 11cm, ZnO:B transparency conductive electrode layer (TCO) 2-2 that sputtering sedimentation 1.0 μ m are thick under this technique.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and remain on 25 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, and Ar flow velocity is 10sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 10nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, Ar flow velocity is 10sccm, open radio-frequency power supply, regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 500nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 500 ℃, and the processing time is 5min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, underlayer temperature remains on 25 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and Ar gas flow rate 10sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 1nm under this technique
1-xzn
xte semiconductor layer 2-5, then turns to In the position of substrate 2-1
2o
3: Sn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick In of sputtering sedimentation 1nm under this technique
2o
3: Snn
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn n
+layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn n
+layer 2-6 takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at In
2o
3: Sn n
+the Ni metallic conduction electrode layer 2-7 that layer 2-6 surface deposition thickness is 200nm.So far complete the preparation of described p-i-n structure C dTe polycrystal film battery.
Embodiment 3
Graphene transparency conductive electrode layer 2-2 prepared by chemical vapour deposition technique method in the mica substrate 2-1 surface cleaning up with micro-90.Graphene growing method is as follows: by chemical vapour deposition technique, in tube furnace, prepare Graphene, the Cu paper tinsel that 0.5mm is thick is put into tube furnace, then diamond heating to 1000 ℃, pass into methane and hydrogen, at 1000 ℃, keep 15min, obtain needed Graphene.Then by the solution of ferric trichloride and hydrochloric acid, Graphene is transferred on polymethyl methacrylate (PMMA), Graphene is being put on mica substrate 2-1, by acetone, polymethyl methacrylate is dissolved, obtain obtaining the transparency conductive electrode layer 2-2 that 0.3nm is thick on mica substrate 2-1.Then the mica substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 600 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 10Pa, and Ar flow velocity is 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 100W, and the distance between target and mica substrate 2-1 is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 100nm is thick under this technique.Then substrate 2-1 is being turned to over against the position of CdTe target, start sputter CdTe intrinsic light absorption semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, Ar flow velocity is 100sccm, open radio-frequency power supply, regulating this output power of power supply is 120W, and the distance between target and substrate 2-1 is 11cm, the CdTe intrinsic light absorption semiconductor layer 2-4 that sputtering sedimentation 1000nm is thick under this technique.Make by the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 400 ℃, and the processing time is 30min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 600 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas and N
2to 10Pa, gas flow rate is 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 160W, and the distance between target and glass 2-1 substrate is 11cm, the thick Cd of sputtering sedimentation 100nm under this technique
1-xmg
xte semiconductor p
+layer 2-5, then turns to In the position of substrate 2-1
2o
3: Sn target, pressure in vacuum tank keeps 10Pa, and the power output of radio-frequency power supply is 160W, and the distance between target and mica substrate 2-1 is 11cm, the thick In of sputtering sedimentation 100nm under this technique
2o
3: Sn n
+increase and instead then wear a layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xte semiconductor p
+layer 2-5, In
2o
3: Sn n
+increase and instead then wear a layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xte semiconductor p
+layer 2-5, In
2o
3: Sn n
+increase and instead then wear a layer 2-6 taking-up chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at In
2o
3: Sn n
+increase and instead then wear the Al metallic conduction electrode layer 2-7 that layer 2-6 surface deposition thickness is 500nm.So far complete the preparation of described p-i-n structure C dTe polycrystal film battery.
Embodiment 4
First by high-purity In of 99.999%
2o
3: Mo target is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 is sent into the vacuum chamber of magnetron sputtering apparatus, and remains on 270 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and Ar flow velocity is 40sccm, opens radio-frequency power supply, and regulating this output power of power supply is 80W, and the distance between target and glass substrate 2-1 is 11cm, the thick In of sputtering sedimentation 1.5 μ m under this technique
2o
3: Mo transparency conductive electrode layer (TCO) 2-2.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and remain on 270 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 0.1Pa, and Ar flow velocity is 10sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 40nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 0.1Pa, Ar flow velocity is 10sccm, open radio-frequency power supply, regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 900nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 390 ℃, and the processing time is 10min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, underlayer temperature is heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas and PH
3to 2Pa to 2Pa, gas flow rate 40sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 10nm under this technique
1-xzn
xte semiconductor layer 2-5, then turns to Al the position of substrate 2-1
2o
3: Zn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Al of sputtering sedimentation 100nm under this technique
2o
3: Znn
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Znn
+layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Znn
+layer 2-6 takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at Al
2o
3: Zn n
+the Au metallic conduction electrode layer 2-7 that layer 2-6 surface deposition thickness is 100nm.So far complete the preparation of described p-i-n structure C dTe polycrystal film battery.
Embodiment 5
First by high-purity In of 99.999%
2o
3: Sn target is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and is heated to 300 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, opens radio-frequency power supply, and regulating this output power of power supply is 120W, and the distance between target and glass substrate is 11cm, the thick In of sputtering sedimentation 1.0 μ m under this technique
2o
3: Sn transparency conductive electrode layer (TCO) 2-2.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and glass substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 50nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and glass substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 600nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 380 ℃, and the processing time is 30min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and other flow 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 50nm under this technique
1-xzn
xte semiconductor layer 2-5.Stop heating, then wait and be coated with transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xthe substrate cool to room temperature of Te semiconductor layer 2-5 takes out from chamber, puts into the vacuum chamber the inside of electron beam and thermal evaporation, treats that chamber vacuum is evacuated to 10
-4below Pa, start the thick Cu with electron beam deposition 20nm, then in quick anneal oven, at 600 ℃, spread 0.1min.
Then thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Cd
1-xzn
xthe substrate on Te semiconductor layer 2-5 with Cu is put into the vacuum chamber of sputter, and is heated to 320 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and the position of substrate is turned to Al
2o
3: Zn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate is 11cm, the thick Al of sputtering sedimentation 50nm under this technique
2o
3: Zn n
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Zn n
+the structure of layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS n type semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Zn n
+layer takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at Al
2o
3: Zn n
+the Au metal electrode layer 2-7 that layer 2-6 surface deposition thickness is 50nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Embodiment 6
First high-purity ZnO:Al target of 99.999% is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and be heated to 200 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, opens radio-frequency power supply, and regulating this output power of power supply is 150W, and the distance between target and glass substrate is 11cm, ZnO:Al transparency conductive electrode layer (TCO) 2-2 that sputtering sedimentation 1.0 μ m are thick under this technique.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and glass substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 50nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and glass substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 600nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 380 ℃, and the processing time is 30min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and other flow 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, the Cd of doping Sb element
1-xmg
xdistance between Te target and glass substrate 2-1 is 11cm, the Sb doping Cd that sputtering sedimentation 20nm is thick under this technique
1-xmg
xte semiconductor layer 2-5.Stop heating, then wait and be coated with transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xthe substrate cool to room temperature of Te semiconductor layer 2-5 takes out from chamber.Then thering is transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xthe substrate 2-1 of Te semiconductor layer 2-5 puts into sputtering chamber, and is heated to 200 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and the position of substrate is turned to Al
2o
3: Zn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate is 11cm, the thick Al of sputtering sedimentation 50nm under this technique
2o
3: Zn n
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xte semiconductor layer 2-5, Al
2o
3: Zn n
+the structure of layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xmg
xte semiconductor layer 2-5, Al
2o
3: Zn n
+layer takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at Al
2o
3: Zn n
+the Au metal electrode layer 2-7 that layer 2-6 surface deposition thickness is 150nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Embodiment 7
First by high-purity SnO of 99.999%
2: F target is installed on the target position of magnetron sputtering apparatus, then the glass substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and is heated to 300 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, opens radio-frequency power supply, and regulating this output power of power supply is 120W, and the distance between target and glass substrate is 11cm, the thick SnO of sputtering sedimentation 1.0 μ m under this technique
2: F transparency conductive electrode layer (TCO) 2-2.Then the glass substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and glass substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 50nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and glass substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 600nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 380 ℃, and the processing time is 30min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and other flow 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and glass substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 50nm under this technique
1-xzn
xte semiconductor layer 2-5.Stop heating, then wait and be coated with transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xthe substrate cool to room temperature of Te semiconductor layer 2-5 takes out from chamber, puts into the vacuum chamber the inside of electron beam and thermal evaporation, treats that chamber vacuum is evacuated to 10
-4below Pa, start the thick Cu with electron beam deposition 20nm, then in quick anneal oven, at 450 ℃, spread 1min.
Then thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Cd
1-xzn
xthe substrate on Te semiconductor layer 2-5 with Cu is put into the vacuum chamber of sputter, and is heated to 320 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and the position of substrate is turned to Al
2o
3: Zn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and glass substrate is 11cm, the thick Al of sputtering sedimentation 50nm under this technique
2o
3: Zn n
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Zn n
+the structure of layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, Al
2o
3: Zn n
+layer takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at Al
2o
3: Zn n
+the Au metal electrode layer 2-7 that layer 2-6 surface deposition thickness is 200nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Embodiment 8
First by high-purity Zn of 99.999%
2snO
4target is installed on the target position of magnetron sputtering apparatus, then the polyimide substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and is heated to 200 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 5Pa, opens radio-frequency power supply, and regulating this output power of power supply is 80W, and the distance between target and polyimide substrate is 11cm, the thick Zn of sputtering sedimentation 1.0 μ m under this technique
2snO
4transparency conductive electrode layer (TCO) 2-2.Then the mica substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and polyimide substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 70nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and polyimide substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 800nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 300 ℃, and the processing time is 120min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.
Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas and NH
3to 2Pa, gas flow 60sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and polyimide substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 20nm under this technique
1-xzn
xte semiconductor layer 2-5.Then the position of substrate 2-1 is turned to In
2o
3: Sn target, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and polyimides 2-1 substrate is 11cm, the thick In of sputtering sedimentation 50nm under this technique
2o
3: Snn
+increase anti-layer 2-6.So far obtain substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn increases the structure of instead then wearing layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn increases the polycrystal film taking-up chamber of instead then wearing layer 2-6.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at In
2o
3: Snn
+increase the Au metal electrode layer 2-7 that anti-layer 2-6 surface deposition thickness is 50nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Embodiment 9
First by high-purity Cd of 99.999%
2snO
4target is installed on the target position of magnetron sputtering apparatus, then the mica substrate 2-1 cleaning up with micro-90 by step 1 is sent into the vacuum chamber of magnetron sputtering apparatus, and is heated to 200 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 5Pa, opens radio-frequency power supply, and regulating this output power of power supply is 180W, and the distance between target and mica substrate is 11cm, the thick Cd of sputtering sedimentation 500nm under this technique
2snO
4transparency conductive electrode layer (TCO) 2-2.Then the mica substrate 2-1 that deposits transparency conductive electrode layer 2-2 is put in the vacuum chamber of magnetron sputtering apparatus, and be heated to 250 ℃.Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 3Pa, opens radio-frequency power supply, and regulating this output power of power supply is 40W, and the distance between target and mica substrate is 11cm, the CdS N-shaped semiconductor layer 2-3 that sputtering sedimentation 20nm is thick under this technique.Then substrate is being turned to over against the position of CdTe target, start sputter CdTe semiconductor layer 2-4, vacuum chamber is filled with argon gas to 2Pa, open radio-frequency power supply, regulating this output power of power supply is 60W, distance between target and mica substrate is 11cm, the CdTe semiconductor layer 2-4 that sputtering sedimentation 100nm is thick under this technique.Make the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.
Stop the heating to substrate 2-1, when substrate 2-1 temperature is reduced to room temperature, take out the solar cell multi-layer film structure being formed by substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4.By step 4 pair battery multi-layer film structure, carry out Cl processing, Cl treatment temperature is 500 ℃, and the processing time is 5min.Complete Cl processing procedure, the solar cell plural layers cool to room temperature with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation.Then the solar cell plural layers with substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4 formation after Cl processes are put into the vacuum chamber of magnetron sputtering, and be heated to 250 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and other flow 100sccm, opens radio-frequency power supply, and regulating this output power of power supply is 60W, and the distance between target and mica substrate 2-1 is 11cm, the thick Cd of sputtering sedimentation 20nm under this technique
1-xzn
xte semiconductor layer 2-5.Stop heating, then wait and be coated with transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xthe substrate cool to room temperature of Te semiconductor layer 2-5, takes out from chamber, puts into the vacuum chamber the inside of electron beam and thermal evaporation, treats that chamber vacuum is evacuated to 10
-4below Pa, start the thick Bi with electron beam deposition 1nm
2se
3.
Then in quick anneal oven, at 50 ℃, spread 120min.Then thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xthe substrate of Te semiconductor layer 2-5 is put into the vacuum chamber of sputter, and is heated to 100 ℃; Vacuum chamber is evacuated to lower than 10
-4pa, vacuum chamber is filled with argon gas to 2Pa, and the position of substrate is turned to In
2o
3: Sn, pressure in vacuum tank keeps 2Pa, and the power output of radio-frequency power supply is 60W, and the distance between target and mica substrate is 11cm, the thick In of sputtering sedimentation 50nm under this technique
2o
3: Sn n
+layer 2-6.So far obtain thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn n
+the structure of layer 2-6.Treat that it is cooled to room temperature, thering is substrate 2-1, transparency conductive electrode layer 2-2, CdS N-shaped semiconductor layer 2-3, CdTe semiconductor layer 2-4, Cd
1-xzn
xte semiconductor layer 2-5, In
2o
3: Sn n
+layer takes out chamber.Put into the vacuum chamber the inside of electron beam and thermal evaporation, treat that chamber vacuum is evacuated to 10
-4below Pa, start at In
2o
3: Sn n
+the Au metal electrode layer 2-7 that layer 2-6 surface deposition thickness is 5nm.So far complete the preparation of the CdTe solar cell polycrystal film battery of described p-i-n structure.
Claims (10)
1. a p-i-n structure C dTe solar cell, it is characterized in that, described p-i-n structure C dTe battery comprises substrate (2-1), transparency conductive electrode layer (2-2), CdS N-shaped semiconductor layer (2-3), CdTe intrinsic light absorbing zone (2-4), the broad-band gap ternary II-VI semiconductor p of family
+layer (2-5), ZnO:Al or In
2o
3: Sn n
+layer (2-6), metal electrode layer (2-7); On described substrate (2-1), be that transparency conductive electrode layer (2-2), transparency conductive electrode layer (2-2) are above CdS N-shaped semiconductor layer (2-3), CdS N-shaped semiconductor layer (2-3) is upper is CdTe intrinsic light absorbing zone (2-4), and CdTe intrinsic light absorbing zone (2-4) is upper is the broad-band gap ternary II-VI semiconductor p of family
+layer (2-5), the broad-band gap ternary II-VI semiconductor p of family
+layer (2-5) is upper is ZnO:Al or In
2o
3: Sn n+ increases anti-tunnelling (2-6), ZnO:Al or In layer by layer
2o
3: it is metal electrode layer (2-7) that Sn n+ increases anti-tunnel layer (2-6) upper; The described broad-band gap ternary II-VI semiconductor p of family
+layer (2-5) is Cd
1-xzn
xte or Cd
1-xmg
xte.
2. the preparation method of p-i-n structure C dTe battery claimed in claim 1, is characterized in that, described preparation method is magnetron sputtering method, and concrete steps are:
(1) clean substrate (2-1);
(2) at the upper growth of substrate (2-1) transparency conductive electrode layer (2-2);
(3) on transparency conductive electrode layer (2-2), grow successively CdS N-shaped semiconductor layer (2-3) and CdTe intrinsic light absorption semiconductor layer (2-4);
(4) described having CdCl
2in the atmosphere of steam, CdS N-shaped semiconductor layer (2-3) and the CdTe intrinsic light absorption semiconductor layer (2-4) of step 3 preparation are carried out to annealing in process; Through CdCl
2on CdTe intrinsic light absorption semiconductor layer (2-4) after annealing in process, deposit successively broad-band gap II-VI semiconductor p
+layer (2-5) and ZnO:Al or In
2o
3: Sn n
+increase and instead then wear layer (2-6);
(5) in magnetron sputtering process, pass into Ar gas, in Ar gas, sneak into the gas containing N and P; At the semiconductor p of broad-band gap II-VI family
+layer (2-5) mixes nitrogen or phosphorus, or the mode of diffusion after adopting is at the semiconductor p of broad-band gap II-VI family
+in layer, mix copper or phosphorus or dysprosium or bismuth;
(6) at ZnO:Al or In
2o
3: Sn n
+increase and instead then wear layer (2-6) surface deposition metallic conduction electrode layer (2-7);
So far make the CdTe solar cell of described p-i-n structure.
3. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, in described step (2), transparency conducting layer is In
2o
3: Sn or ZnO:Al or ZnO:B or In
2o
3: Mo or In:ZnO or Graphene or SnO
2: F or Cd
2snO
4, the thickness of described transparency conductive electrode layer is 0.3-1500nm.
4. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method of operation of described step 3 is: the substrate of having prepared transparency conductive electrode layer is put in the position of placing substrate at magnetron sputtering stove, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and intensification makes underlayer temperature remain on 25-600 ℃; When back end vacuum arrives 10
-3below Pa, start sputter CdS semiconductor layer; The sputtering condition of CdS semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber; When the thickness of the CdS semiconductor layer of institute's sputter is 10-100nm on substrate, stop the preparation of CdS semiconductor layer, substrate is turned to over against the position of CdTe target, start sputter CdTe semiconductor layer; The sputtering condition of CdTe semiconductor layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering furnace chamber pressure 0.1-10Pa in magnetron sputtering furnace chamber; When the CdTe semiconductor layer thickness of institute's sputter on substrate reaches the thickness 0.1-1 μ m of setting, stop the preparation of CdTe semiconductor layer, stop, to substrate heating, when underlayer temperature is reduced to room temperature, taking out the substrate that has deposited CdS and CdTe semiconductor layer simultaneously.
5. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, described step 4 is at CdCl
2in atmosphere, the CdS of preparation and CdTe semiconductor layer are carried out annealing method and are, at 300-500 ℃ to CdSn type semiconductor layer and CdTe intrinsic light absorption semiconductor layer annealing in process 5-120min; Annealing adopts wet method or dry method; The technical process of wet method annealing is as follows: CdCl
2saturated methanol solution evenly drop on CdTe intrinsic light absorption semiconductor layer, CdTe intrinsic light absorption semiconductor layer is carried out to annealing in process.The technical process of dry method annealing is as follows: CdCl
2evenly be placed on sheet glass, then apart from this sheet glass 1-5mm place, placing the substrate with CdTe intrinsic light absorption semiconductor layer, CdSn type semiconductor layer and transparency conductive electrode layer, CdTe half intrinsic light absorption conductor layer is over against there being CdCl
2sheet glass, then CdSn type semiconductor layer and CdTe intrinsic light absorption semiconductor layer are carried out to annealing in process.
6. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method of operation of described step 5 is: on the position of magnetron sputtering stove placement substrate, put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the underlayer temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on the scope of 25-600 ℃; When back end vacuum arrives 10
-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family
+layer; The broad-band gap ternary II-VI semiconductor p of family
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar or Ar and N in magnetron sputtering chamber
2, or Ar and PH
3, gas flow rate 10-100sccm, chamber pressure 0.1-10Pa; As the broad-band gap ternary II-VI semiconductor p of family
+when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family
+the preparation of layer; Or the complete broad-band gap ternary of the sputter II-VI semiconductor p of family
+after layer, being coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, the broad-band gap ternary II-VI semiconductor p of family
+the substrate of layer takes out, and then passes through electron beam or thermal evaporation at the broad-band gap ternary II-VI semiconductor p of family
+cu or P or the Sb of growth 1-20nm on layer
2te
3or Bi
2te
3, then in quick anneal oven, 50-600 ℃ of temperature range, to spread, the time of diffusion is 0.1-120min; Substrate is turned to over against ZnO:Al or In
2o
3: the position of Sn target, starts sputter ZnO:Al or In
2o
3: Snn
+layer; ZnO:Al or In
2o
3: Sn n
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber; ZnO:Al or the In of institute's sputter on substrate
2o
3: Sn n
+when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In
2o
3: Sn n
+the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.
7. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, in described step 5, on the position of magnetron sputtering stove placement substrate, put the substrate that is coated with transparency conductive electrode layer, CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone, cover the bell of magnetron sputtering stove, magnetron sputtering furnace chamber is vacuumized, and heat up make to there is transparency conductive electrode layer, the substrate temperature of CdS N-shaped semiconductor layer, CdTe intrinsic light absorbing zone remains on 25-600 ℃; When back end vacuum arrives 10
-3below Pa, start the sputter broad-band gap ternary II-VI semiconductor p of family
+layer; The broad-band gap ternary II-VI semiconductor p of family
+the sputtering condition of layer is: target is the broad-band gap ternary II-VI family semiconductor layer that mixes the materials such as Cu or P or Sb or Bi, such as: Cd
1-xzn
xte or Cd
1-xmg
xte, underlayer temperature 25-600 ℃ passes into high-purity Ar gas flow rate 10-100sccm, chamber pressure 0.1-10Pa in magnetron sputtering chamber; As the broad-band gap ternary II-VI semiconductor p of family
+when the thickness of layer is 1-100nm, stop the broad-band gap ternary II-VI semiconductor p of family
+the preparation of layer; Substrate is turned to over against ZnO:Al or In
2o
3: the position of Sn target, starts sputter ZnO:Al or In
2o
3: Sn n
+layer; ZnO:Al or In
2o
3: Sn n
+the sputtering condition of layer is: underlayer temperature 25-600 ℃ passes into high-purity Ar gas, gas flow rate 10-100sccm, magnetron sputtering chamber pressure 0.1-10Pa in magnetron sputtering chamber; ZnO:Al or the In of institute's sputter on substrate
2o
3: Sn n
+when the thickness of layer reaches the thickness 1-100nm of setting, stop ZnO:Al or In
2o
3: Sn n
+the preparation of layer stops, to substrate heating, when underlayer temperature is reduced to room temperature, taking out substrate simultaneously.
8. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, the method for operation of described step 6 is: by thermal evaporation or electron beam at ZnO:Al or In
2o
3: Sn n
+layer increases instead wears the metal electrode layer that layer upper evaporation thickness is greater than 5nm then, and the thickness of metal electrode layer records by quartz crystal.
9. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, adopt the method for magnetron sputtering to prepare N-shaped CdS semiconductor layer, intrinsic CdTe light absorbing zone, broad-band gap ternary II-VI semiconductor p
+layer; Magnetically controlled sputter method can obtain the CdS/CdTe interface of porous, before light enters CdTe absorbed layer, is scattered, and increases the light path of light in CdTe absorbed layer, reaches the effect that falls into light; At the broad-band gap ternary II-VI semiconductor p of family
+the n inserting between layer and metal electrode layer
+type ZnO:Al or In
2o
3: layer is instead worn in Sn increasing then can play light trapping effect.
10. according to the preparation method of p-i-n structure C dTe battery claimed in claim 2, it is characterized in that, described substrate is rigid substrate, or flexible substrate.
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