CN104064520B - Polysilicon resistance integrated manufacturing method in germanium silicium HBT technique - Google Patents
Polysilicon resistance integrated manufacturing method in germanium silicium HBT technique Download PDFInfo
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- CN104064520B CN104064520B CN201310095359.7A CN201310095359A CN104064520B CN 104064520 B CN104064520 B CN 104064520B CN 201310095359 A CN201310095359 A CN 201310095359A CN 104064520 B CN104064520 B CN 104064520B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 139
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 131
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 60
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 43
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 69
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000001259 photo etching Methods 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 18
- 238000005516 engineering process Methods 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000012530 fluid Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses polysilicon resistance integrated manufacturing method in a kind of germanium silicium HBT technique, including step: deposit ground floor polysilicon is also doped；Ground floor polysilicon is carried out chemical wet etching and forms polysilicon resistance；Deposit second layer silicon oxide also carries out back carving the side wall forming polysilicon resistance；Thermal oxidation technology is used to form the 3rd silicon oxide layer；Deposit the 4th silicon oxide layer and the 5th polysilicon son's crystal layer successively；Photoetching and etching technics is used to open germanium silicon epitaxial layer window；Deposit germanium silicon epitaxial layer and the 6th silicon oxide layer；Photoetching process is used to define the formation region, base of germanium silicium HBT；Wet-etching technology is used to be removed by the 6th silicon oxide layer outside base；Dry etch process is used the germanium silicon epitaxial layer outside base and the 5th polysilicon son's crystal layer to be removed and form base.The present invention can eliminate the residual polycrystalline silicon around polysilicon resistance, improves the inner evenness of polysilicon resistance.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of germanium silicon (SiGe) different
In matter knot bipolar transistor (Heterojunction bipolar transistor, HBT) technique, polysilicon resistance is integrated
Manufacture method.
Background technology
Radio frequency leading portion chip circuit for the communications field is typically made up of four parts: power amplifier, low noise are put
Big device, on-off circuit and simple logic control circuit.Power germanium silicium HBT technique, be integrated with SiGe NPN, PNP,
After resistance, electric capacity (including variable capacitance), inductance and switching device, mate in may conform to circuit carries out sheet, patrol
Collect and control and receive and dispatch the requirements such as conversion.
In germanium silicium HBT Process ba-sis flow process, various devices integrate and obtain preferable uniformity and bigger
Process window be considerable.Electric capacity and inductance are single devices, as long as adding corresponding in last part technology
Processing step is the formation of；But high-precision polysilicon resistance is i.e. forming germanium silicon before then needing to be integrated in germanium silicon technology
Before epitaxial layer technique, need individually to deposit, adulterate and etch, the most again through the related process of germanium silicium HBT.
As shown in Figure 1A to Fig. 1 C, it it is the device architecture schematic diagram in each step of existing method；Existing germanium silicium HBT work
In skill, polysilicon resistance integrated manufacturing method includes step:
Step (1), as shown in Figure 1A, it is provided that one has the silicon substrate of an oxygen 101 isolation structure, carries out polysilicon shallow lake
Amass, adulterate and etch, the polysilicon after etching form polysilicon resistance 102.Polysilicon resistance 102 is formed at field
On oxygen 101.
Step (2), as shown in Figure 1A, carries out silicon oxide deposition and carries out go back to being engraved in the formation side, side of polysilicon resistance
Wall 103.Using wet processing to go silicon to remain again, higher wet oxidation silicon removal can make side wall steep.
Step (3), as shown in Figure 1A, then silicon oxide deposition 104 and polysilicon son's crystalline substance 105.
Step (4), as shown in Figure 1A, uses photoetching and etching technics to open germanium silicon epitaxial layer window.Germanium and silicon epitaxial
Layer window is positioned at the formation region of SiGe HBT, does not shows in figure ia.Figure 1A illustrate only polysilicon resistance 102
Formation region.
Step (5), as shown in Figure 1A, deposits germanium silicon epitaxial layer 106；Deposit one layer of silicon oxide 107 again for protecting
Germanium silicon face.Wherein germanium silicon epitaxial layer 106 is positioned at the surfaces of active regions part isolated by field oxygen is monocrystal silicon, is positioned at
Brilliant 105 surface portion of polysilicon son are polysilicon.
The silicon oxide layer 107 formed in step (6), as illustrated in figures ib and 1 c, photoetching and dry etching step (5)
With the base that germanium silicon epitaxial layer 106 forms HBT.In this step, owing to using dry etch process to carry out etching oxidation silicon
Layer 107, owing to the side wall 103 of polysilicon resistance 102 is relatively steep, refer to district as shown in the dotted line frame 108 in Figure 1A
Territory, each layer of deposit longitudinal thickness of each layer thicker i.e. dotted line frame 108 in terms of vertical direction is the thickest；Such as Figure 1B
Shown in, etching deficiency can be caused during the silicon oxide layer 107 of dry etching base to cause silicon oxide to remain 107a.Such as Fig. 1 C institute
Showing, silicon oxide residual 107a is when brilliant 105 etching of ensuing polysilicon i.e. germanium silicon epitaxial layer 106 and polysilicon son
Become barrier layer, cause and remain 105a along the base polysilicon around polysilicon resistance, in follow-up band ultrasonic waves for cleaning
Shi Ze becomes defect, affects the uniformity of polysilicon resistance.
Summary of the invention
The technical problem to be solved is to provide the integrated making side of polysilicon resistance in a kind of germanium silicium HBT technique
Method, it is possible to eliminate the residual polycrystalline silicon around polysilicon resistance, improves the inner evenness of polysilicon resistance.
For solving above-mentioned technical problem, polysilicon resistance integrated manufacturing method in the germanium silicium HBT technique that the present invention provides,
For realization, polysilicon resistance and germanium silicium HBT are integrated making, comprise the steps:
Step one, offer one have a silicon substrate for oxygen isolation structure, and the active area of described silicon substrate is entered by described field oxygen
Row isolation；On described silicon substrate, deposit forms ground floor polysilicon；Described ground floor polysilicon is doped, makes
Square resistance after described ground floor polysilicon doping is the square resistance of described polysilicon resistance to be formed.
Described ground floor polysilicon is performed etching by step 2, employing lithographic etch process, and this etching technics is by described many
The described ground floor polysilicon formed outside region of crystal silicon resistance is removed, being formed described polysilicon resistance in region
Described ground floor polysilicon retains, the described ground floor polysilicon retained after etching form described polysilicon resistance.
Step 3, be formed described polysilicon resistance described surface of silicon deposit second layer silicon oxide, to described
Second layer silicon oxide carries out back carving, and second layer silicon oxide described in Hui Kehou only remaines in the side of described polysilicon resistance also
Form the side wall of described polysilicon resistance.
Step 4, employing thermal oxidation technology are formed in the described surface of silicon of the side wall being formed with described polysilicon resistance
3rd silicon oxide layer, electric to described polysilicon resistance surface and described polysilicon for time carving technology of removal step three
The damage of the described surface of silicon outside resistance.
Step 5, deposit the 4th silicon oxide layer and the 5th polysilicon son's crystal layer successively on described 3rd silicon oxide layer surface.
Step 6, employing photoetching and etching technics open germanium silicon epitaxial layer window, the institute in described germanium silicon epitaxial layer window
State the 3rd silicon oxide layer, described 4th silicon oxide layer and described 5th polysilicon son's crystal layer be all removed and will be used for being formed
The described surfaces of active regions of described germanium silicium HBT is exposed.
Step 7, be formed described germanium silicon epitaxial layer window described silicon substrate front deposit germanium silicon epitaxial layer；Institute
State germanium silicon epitaxial layer surface deposition the 6th silicon oxide layer.
Step 8, employing photoetching process form photoetching offset plate figure and are defined described germanium silicium HBT by this photoetching offset plate figure
Formation region, base, uses wet-etching technology by outside formation region, described base with described photoetching offset plate figure for mask
Described 6th silicon oxide layer is removed；Dry etch process is used to be formed described base with described photoetching offset plate figure for mask
Described germanium silicon epitaxial layer and described 5th polysilicon son's crystal layer outside region are removed, and described dry etch process is the most also wrapped
Including an isotropic over etching technique, this over etching technique is by described 4th silicon oxide outside formation region, described base
Described germanium silicon epitaxial layer and described 5th polysilicon son's crystal layer of the layer surface place of being uneven residual are removed completely；Described dry
Defined the described germanium silicon epitaxial layer in region by described photoetching offset plate figure after method etching technics and form the base of described germanium silicium HBT
District.
Further improving is that the thickness of ground floor polysilicon described in step one is 1500 angstroms～3000 angstroms, uses
Described ground floor polysilicon is doped by ion implantation technology.
Further improving is that the thickness of second layer silicon oxide described in step 3 is more than 2000 angstroms, to described the
Two layers of silicon oxide use after returning quarter described second layer silicon oxide without the cleanout fluid of corrasion described surface of silicon
It is carried out.
Further improving is that the thickness of the 3rd silicon oxide layer described in step 4 is 30 angstroms～80 angstroms；In step 5
The thickness of described 4th silicon oxide layer is 200 angstroms～500 angstroms, the thickness of described 5th polysilicon son's crystal layer be 300 angstroms～
500 angstroms.
Further improving is that the thickness of the 6th silicon oxide layer described in step 7 is 150 angstroms～300 angstroms.
Further improving is that field oxygen described in step one is local field oxygen or shallow groove field oxygen, described polysilicon resistance position
Above the oxygen of described field.
Further improving is to be additionally included in described germanium silicium HBT before step one deposits described ground floor polysilicon
Form the step forming collecting zone in the described active area in region, described collecting zone and the described base being subsequently formed to connect
Touch；After step 8 forms described base, be additionally included in above described base formed described germanium silicium HBT by polycrystalline
The step of silicon launch site.
There is advantages that
1, the present invention is to use wet-etching technology by outside the germanium silicon outside base when the base carrying out germanium silicium HBT etches
Silicon oxide that is the 6th silicon oxide layer prolonging layer surface is removed, and wet etching, for etch in the same direction, relative in prior art is
The dry etching of anisotropic etching, the wet etching of the inventive method can be by the 6th around polysilicon resistance side wall
Silicon oxide is removed completely, eliminates silicon oxide residual, thus to follow-up polysilicon when also eliminating silicon oxide residual
Stop can be produced and form the problem of residual polycrystalline silicon when germanium silicon epitaxial layer and the 5th polysilicon son's crystal layer etching, so this
Invention can eliminate residual polycrystalline silicon, and then can improve the inner evenness of polysilicon resistance.
2, to polysilicon i.e. germanium silicon epitaxial layer and the 5th polysilicon son's crystal layer when the present invention forms the base of germanium silicium HBT
Finally also including an isotropic over etching technique in dry etch process, this over etching technique can aoxidize the 4th
The silicon surface place of being uneven remaining polycrystalline silicon completes to remove, and can improve the inner evenness of polysilicon resistance further.
3, the thickness being used for being formed the second layer silicon oxide of side wall is set to more than 2000 angstroms by the inventive method, it is possible to
Increase the gradient of side wall, reduce the probability being subsequently formed residual polycrystalline silicon, the face of polysilicon resistance can be improved further
Interior uniformity.
4, the inventive method is after side wall is formed, and uses silicon oxide without the cleanout fluid of corrasion surface of silicon
It is carried out, and without using ultrasound wave, it is possible to prevent the detraction of side wall or come off, it is possible to preventing the gradient of side wall from becoming
Suddenly, further reduce the probability being subsequently formed residual polycrystalline silicon, equal in the face of polysilicon resistance can be improved further
Even property.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Figure 1A-Fig. 1 C is the device architecture schematic diagram in each step of existing method；
Fig. 2 is the flow chart of embodiment of the present invention method；
Fig. 3 A-Fig. 3 E is the device architecture schematic diagram in each step of embodiment of the present invention method.
Detailed description of the invention
As in figure 2 it is shown, be the flow chart of embodiment of the present invention method；As shown in Fig. 3 A to Fig. 3 E, it is that the present invention is real
Execute the device architecture schematic diagram in each step of example method.In embodiment of the present invention germanium silicium HBT technique, polysilicon resistance is integrated
Polysilicon resistance 2 and germanium silicium HBT are integrated making for realization by manufacture method, comprise the steps:
Step one, as shown in Figure 3A, it is provided that one has the silicon substrate of an oxygen 1 isolation structure, having of described silicon substrate
Source region is isolated by described field oxygen 1.Described field oxygen 1 is local field oxygen (LOCOS) or shallow groove field oxygen (STI).
Only illustrating the structure chart forming region of polysilicon resistance 2 in Fig. 3 A, germanium silicium HBT forms the structure chart in region
Not shown.Firstly the need of the collection forming described germanium silicium HBT in the described active area forming region of described germanium silicium HBT
Electricity district.
On described silicon substrate, deposit forms the ground floor polysilicon that thickness is 1500 angstroms～3000 angstroms, described ground floor
The preferred thickness of polysilicon is 2500 angstroms；Use ion implantation technology that described ground floor polysilicon is doped, make
Square resistance after described ground floor polysilicon doping is the square resistance of described polysilicon resistance 2 to be formed.
Step 2, as shown in Figure 3A, uses lithographic etch process to perform etching described ground floor polysilicon, this quarter
The described ground floor polysilicon formed outside region of described polysilicon resistance 2 is removed, by described polysilicon electricity by etching technique
The described ground floor polysilicon formed in region of resistance 2 retains, by the described ground floor polysilicon group retained after etching
Become described polysilicon resistance 2.Described polysilicon resistance 2 is positioned at above described field oxygen 1.
Step 3, as shown in Figure 3A, deposits second in the described surface of silicon being formed with described polysilicon resistance 2
Layer silicon oxide, carries out back described second layer silicon oxide carving, and second layer silicon oxide described in Hui Kehou only remaines in described many
The side of crystal silicon resistance 2 also forms the side wall 3 of described polysilicon resistance 2.
The thickness of described second layer silicon oxide is more than 2000 angstroms, and thicker described second layer silicon oxide can make formation
Described side wall 3 has the less gradient, it is possible to prevent the follow-up base etching that described side wall 3 gradient is caused when crossing steep
Time the problem of residual polycrystalline silicon.
Use after described second layer silicon oxide is returned quarter described second layer silicon oxide without the cleanout fluid of corrasion institute
State surface of silicon to be carried out, this cleaning be not required to use ultrasound wave, it is possible to prevent described side wall 3 detraction or
Come off.
Step 4, as shown in Figure 3 B, uses thermal oxidation technology being formed with the side wall 3 of described polysilicon resistance 2
Described surface of silicon forms the 3rd silicon oxide layer that thickness is 30 angstroms～80 angstroms, for the Hui Kegong of removal step three
The skill damage to the described surface of silicon outside described polysilicon resistance 2 surface and described polysilicon resistance 2.
Step 5, as shown in Figure 3 B, deposits the 4th silicon oxide layer 4 and successively on described 3rd silicon oxide layer surface
Five polysilicon son's crystal layers 5.The thickness of described 4th silicon oxide layer 4 is 200 angstroms～500 angstroms, described 5th polysilicon
The thickness of young crystal layer 5 is 300 angstroms～500 angstroms.
Step 6, as shown in Figure 3 C, uses photoetching and etching technics to open germanium silicon epitaxial layer window, outside described germanium silicon
Prolong described 3rd silicon oxide layer in layer window, described 4th silicon oxide layer 4 and described 5th polysilicon son's crystal layer 5 all
It is removed and the described surfaces of active regions being used for being formed described germanium silicium HBT is exposed.Described germanium silicon epitaxial layer window is positioned at
In the formation region of described germanium silicium HBT, the most do not show.
Step 7, as shown in Figure 3 C, deposits germanium in the described silicon substrate front being formed with described germanium silicon epitaxial layer window
Silicon epitaxy layer 6；At the 6th silicon oxide layer 7 that described germanium silicon epitaxial layer 6 surface deposition thickness is 150 angstroms～300 angstroms.
In described germanium silicon epitaxial layer window and to be positioned at the described germanium silicon epitaxial layer 6 of the described surfaces of active regions exposed be monocrystalline
Silicon, the described germanium silicon epitaxial layer 6 on the surface being positioned at described 5th polysilicon son's crystal layer 5 is polysilicon.
Step 8, as shown in Figure 3 D, uses photoetching process to form photoetching offset plate figure and is also defined by this photoetching offset plate figure
The formation region, base of described germanium silicium HBT, uses wet-etching technology by described base with described photoetching offset plate figure for mask
Described 6th silicon oxide layer 7 outside formation region, district is removed.
As shown in FIGURE 3 E, use dry etch process by formation region, described base with described photoetching offset plate figure for mask
Outer described germanium silicon epitaxial layer 6 and described 5th polysilicon son's crystal layer 5 are removed, and described dry etch process is the most also wrapped
Including an isotropic over etching technique, this over etching technique is by described 4th silicon oxide outside formation region, described base
Described germanium silicon epitaxial layer 6 and described 5th polysilicon son's crystal layer 5 of the layer 4 surface place of being uneven residual are removed completely；
Defined the described germanium silicon epitaxial layer 6 in region by described photoetching offset plate figure after described dry etch process and form described germanium silicon
The base of HBT.
Being formed after described base, be additionally included in above described base formed described germanium silicium HBT by polysilicon emitter
The step in district.Formed afterwards and carry out contacting by collecting zone, base and the launch site of described germanium silicium HBT and described polycrystalline
The electrode of silicon resistor 2 is drawn, and forms metal interconnection pattern afterwards.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (7)
1. a polysilicon resistance integrated manufacturing method in germanium silicium HBT technique, for realizing polysilicon resistance and germanium
Silicium HBT integrates making, it is characterised in that comprise the steps:
Step one, offer one have a silicon substrate for oxygen isolation structure, and the active area of described silicon substrate is entered by described field oxygen
Row isolation；On described silicon substrate, deposit forms ground floor polysilicon；Described ground floor polysilicon is doped, makes
Square resistance after described ground floor polysilicon doping is the square resistance of described polysilicon resistance to be formed；
Described ground floor polysilicon is performed etching by step 2, employing lithographic etch process, and this etching technics is by described many
The described ground floor polysilicon formed outside region of crystal silicon resistance is removed, being formed described polysilicon resistance in region
Described ground floor polysilicon retains, the described ground floor polysilicon retained after etching form described polysilicon resistance；
Step 3, be formed described polysilicon resistance described surface of silicon deposit second layer silicon oxide, to described
Second layer silicon oxide carries out back carving, and second layer silicon oxide described in Hui Kehou only remaines in the side of described polysilicon resistance also
Form the side wall of described polysilicon resistance；
Step 4, employing thermal oxidation technology are formed in the described surface of silicon of the side wall being formed with described polysilicon resistance
3rd silicon oxide layer, electric to described polysilicon resistance surface and described polysilicon for time carving technology of removal step three
The damage of the described surface of silicon outside resistance；
Step 5, deposit the 4th silicon oxide layer and the 5th polysilicon son's crystal layer successively on described 3rd silicon oxide layer surface；
Step 6, employing photoetching and etching technics open germanium silicon epitaxial layer window, the institute in described germanium silicon epitaxial layer window
State the 3rd silicon oxide layer, described 4th silicon oxide layer and described 5th polysilicon son's crystal layer be all removed and will be used for being formed
The surfaces of active regions of described germanium silicium HBT is exposed；
Step 7, be formed described germanium silicon epitaxial layer window described silicon substrate front deposit germanium silicon epitaxial layer；Institute
State germanium silicon epitaxial layer surface deposition the 6th silicon oxide layer；
Step 8, employing photoetching process form photoetching offset plate figure and are defined described germanium silicium HBT by this photoetching offset plate figure
Formation region, base, uses wet-etching technology by outside formation region, described base with described photoetching offset plate figure for mask
Described 6th silicon oxide layer is removed；Dry etch process is used to be formed described base with described photoetching offset plate figure for mask
Described germanium silicon epitaxial layer and described 5th polysilicon son's crystal layer outside region are removed, and described dry etch process is the most also wrapped
Including an isotropic over etching technique, this over etching technique is by described 4th silicon oxide outside formation region, described base
Described germanium silicon epitaxial layer and described 5th polysilicon son's crystal layer of the layer surface place of being uneven residual are removed completely；Described dry
Defined the described germanium silicon epitaxial layer in region by described photoetching offset plate figure after method etching technics and form the base of described germanium silicium HBT
District.
2. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
The thickness of ground floor polysilicon described in step one is 1500 angstroms～3000 angstroms, uses ion implantation technology to described the
One layer of polysilicon is doped.
3. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
The thickness of second layer silicon oxide described in step 3 is more than 2000 angstroms, uses after described second layer silicon oxide returns quarter
Described surface of silicon is carried out by described second layer silicon oxide without the cleanout fluid of corrasion.
4. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
The thickness of the 3rd silicon oxide layer described in step 4 is 30 angstroms～80 angstroms；The thickness of the 4th silicon oxide layer described in step 5
Degree is 200 angstroms～500 angstroms, and the thickness of described 5th polysilicon son's crystal layer is 300 angstroms～500 angstroms.
5. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
The thickness of the 6th silicon oxide layer described in step 7 is 150 angstroms～300 angstroms.
6. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
Field oxygen described in step one is local field oxygen or shallow groove field oxygen, and described polysilicon resistance is positioned at above the oxygen of described field.
7. polysilicon resistance integrated manufacturing method in germanium silicium HBT technique as claimed in claim 1, it is characterised in that:
The described active area forming region of described germanium silicium HBT it was additionally included in before step one deposits described ground floor polysilicon
The step of middle formation collecting zone, described collecting zone and the described base being subsequently formed contact；Formed described in step 8
After base, be additionally included in above described base formed described germanium silicium HBT by the step of polysilicon emissioning area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310095359.7A CN104064520B (en) | 2013-03-22 | 2013-03-22 | Polysilicon resistance integrated manufacturing method in germanium silicium HBT technique |
Applications Claiming Priority (1)
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