US20190273132A1 - Structures with an airgap and methods of forming such structures - Google Patents
Structures with an airgap and methods of forming such structures Download PDFInfo
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- US20190273132A1 US20190273132A1 US15/911,831 US201815911831A US2019273132A1 US 20190273132 A1 US20190273132 A1 US 20190273132A1 US 201815911831 A US201815911831 A US 201815911831A US 2019273132 A1 US2019273132 A1 US 2019273132A1
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Images
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
- The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures that include an airgap and methods for forming a structure that includes an airgap.
- Complementary metal-oxide semiconductor (CMOS) circuitry is utilized in mobile communication devices (e.g., laptops, cellular phones, tablets, etc.) to handle wireless high frequency signals transmitted to and/or received by the mobile communication devices. The circuitry may include a low noise amplifier and a high frequency switch that allows for high frequency signals received by an antenna to be routed from the low noise amplifier to other chip circuitry and for high frequency signals to be routed from a power amplifier to the antenna. The high frequency switch may include a stack or bank of field-effect transistors formed by CMOS processes. Field-effect transistors fabricated on a bulk substrate may exhibit poor linearity due to, for example, non-linear electric fields on the substrate and poor intermodulation properties. Semiconductor-on-insulator (SOI) substrates may mitigate these issues, but are costly in comparison with bulk substrates.
- Improved structures that include an airgap and methods for forming such structures are needed.
- In an embodiment of the invention, a structure includes a substrate and a first semiconductor layer on the substrate. The first semiconductor layer includes a device region, and a device structure is located in the device region. An airgap is arranged in a vertical direction between the substrate and the device region. The semiconductor layer includes a plurality of openings that extend through the device region to the airgap.
- In an embodiment of the invention, a method includes epitaxially growing a layer stack including a first semiconductor layer and a second semiconductor layer on a substrate. The method further includes forming a plurality of openings extending through a device region of the first semiconductor layer to the second semiconductor layer, and etching the second semiconductor layer through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIG. 1 is a top view of a structure at an initial fabrication stage of a processing method in accordance with an embodiment of the invention. -
FIG. 2 is a cross-sectional view taken generally along line 2-2 inFIG. 1 . -
FIGS. 3-5 are cross-sectional views of the structure at successive fabrication stages subsequent toFIG. 2 . -
FIG. 6 is a cross-sectional view of a chip that includes the structure ofFIG. 5 . - With reference to
FIGS. 1, 2 and in accordance with embodiments of the invention, asemiconductor layer 10 usable to form the devices of an integrated circuit with front-end-of-line (FEOL) processing and asemiconductor layer 12 are formed on asubstrate 14. Thesemiconductor layer 10 may be composed of single-crystal silicon. Thesubstrate 14 may be a bulk wafer comprised of single-crystal silicon. In an embodiment, thesubstrate 14 may be a high-resistivity bulk silicon wafer having a resistivity greater than or equal to 1 kOhm-cm. Thesemiconductor layer 12 is epitaxially grown over thesubstrate 14 using thesubstrate 14 as a growth seed, and thesemiconductor layer 10 is epitaxially grown over thesemiconductor layer 12 using thesemiconductor layer 12 as a growth seed. - The
semiconductor layer 12 may be composed of a material, such as silicon-germanium (SiGe), that can be etched selective to the semiconductor material (e.g., silicon) of thesemiconductor layer 10 and to the semiconductor material of the substrate 14 (e.g., silicon). As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. In an embodiment, thesemiconductor layer 12 may be composed of silicon-germanium with a germanium content ranging from twenty percent (20%) to thirty-five percent (35%), which etches at a higher rate than silicon. In an embodiment, thesemiconductor layer 12 may have a thickness, t1, that is less than or equal to 50 nanometers. In an embodiment, thesemiconductor layer 10 may have a thickness that is less than or equal to 500 nanometers such that a top surface of thesemiconductor layer 12 is spaced from thetop surface 11 of thesemiconductor layer 10 by a distance that is less than or equal to 500 nanometers. - Deep
trench isolation regions 16 are formed that extend from thetop surface 11 of thesemiconductor layer 10 through thesemiconductor layer 10 and thesemiconductor layer 12 and penetrate to a shallow depth into thesubstrate 14. The deeptrench isolation regions 16 surround a section of thesemiconductor layer 10 to define adevice region 18 that may be used in front-end-of-line (FEOL) device fabrication. The top surface of thedevice region 18 coincides with thetop surface 11 of thesemiconductor layer 10. The deeptrench isolation regions 16 may be formed by etching trenches and then filling the etched trenches with a dielectric material, such as silicon dioxide (SiO2), that is deposited (e.g., by chemical vapor deposition (CVD)) and planarized with, for example, chemical mechanical polishing (CMP). - An
etch mask 20, shown in dashed lines, is formed over thetop surface 11 of thesemiconductor layer 10 and deeptrench isolation regions 16, and is arranged to cover thedevice region 18. Theetch mask 20 may include a photoresist that is applied as a coating by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to form openings. A directional etching process, such as reactive ion etching (ME), is used to formopenings 22 at the locations of the openings in theetch mask 20. Theopenings 22 penetrate completely through thesemiconductor layer 10 to thesemiconductor layer 12. The etching process may remove the material of thesemiconductor layer 10 selective to the material of thesemiconductor layer 12 such that thesemiconductor layer 12 functions as an etch stop. - The
openings 22 may be arranged in an array or another pattern across thetop surface 11 of thedevice region 18, or the arrangement of theopenings 22 may be placed in random positions. The number and size of theopenings 22 may also vary depending on design parameters. In the representative embodiment, theopenings 22 terminate at the top surface of thesemiconductor layer 12. In alternative embodiments, theopenings 22 may penetrate partially through thesemiconductor layer 12. In alternative embodiments, theopenings 22 may penetrate completely through thesemiconductor layer 12. In alternative embodiments, theopenings 22 may penetrate completely through thesemiconductor layer 12 and into theunderlying substrate 14. - With reference to
FIG. 3 in which like reference numerals refer to like features inFIGS. 1, 2 and at a subsequent fabrication stage, anairgap 26 is formed that extends beneath thedevice region 18 and that is arranged vertically between thedevice region 18 of thesemiconductor layer 10 and thesubstrate 14. To that end, thesemiconductor layer 12 may be completely removed from beneath thedevice region 18 with an isotropic etching process that etches the material constituting thesemiconductor layer 12 selective to the materials constituting thesemiconductor layer 10,substrate 14, and the deeptrench isolation regions 16. Theairgap 26 may have a height equal to the thickness of thesemiconductor layer 12. Theopenings 22 in thesemiconductor layer 10 provide ingress and egress pathways for the etchant removing thesemiconductor layer 12. The anisotropic etching process includes a lateral etching component that etches the sacrificial layer starting at the locus of each opening 22 and expanding outwardly until the individual etched volumes merge together to form theairgap 26. Until merger occurs, the individual unetched volumes of the solid material of thesemiconductor layer 12 between the individual etched volumes provide support for thedevice region 18. Thesemiconductor layer 12 may be etched and removed using, for example, hot ammonia (NH3) and/or hydrochloric acid (HCl) vapor. - The
airgap 26 may be characterized by a permittivity or dielectric constant of near unity (i.e., vacuum permittivity). Theairgap 26 may be filled by atmospheric air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain atmospheric air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum). The reduced dielectric constant of theairgap 26 reduces the capacitive coupling between device structures formed in thedevice region 18 and thesubstrate 14. - The deep
trench isolation regions 16 define a boundary over which thesemiconductor layer 12 is removed and surround theairgap 26 on all sides. Thedevice region 18 is attached to the deeptrench isolation regions 16 about its entire perimeter. The deeptrench isolation regions 16 surrounding thedevice region 18 apply an inward compressive stress on thedevice region 18 at the sidewall of thedevice region 18. The inward compressive stress, which may cause thedevice region 18 to bow upward, physically and structurally supports thedevice region 18 and prevents its collapse after theairgap 26 is formed. Thesemiconductor layer 12 outside of the deeptrench isolation regions 16 is not removed and also surrounds theairgap 26 on all sides. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIG. 3 and at a subsequent fabrication stage,pillars 30 of a dielectric material may be formed inside theairgap 26 below each of theopenings 22. The dielectric material may be composed of, for example, aluminum oxide (Al2O3) or silicon dioxide (SiO2) deposited by atomic layer deposition (ALD) or a rapid thermal oxide (RTO). The deposited dielectric material increases in height as the deposition progresses. Thedielectric material pillars 30 are arranged in theairgap 26 with the same arrangement as theopenings 22 in thedevice region 18. The height of thedielectric material pillars 30 may be greater than or equal to the height of theairgap 26 so that thedielectric material pillars 30 assist with physically and structurally supporting thedevice region 18 above theairgap 26. Thedielectric material pillars 30 are optional features and, in an alternative embodiment, thedielectric material pillars 30 may be omitted from the structure. - The
openings 22 may be at least partially filled withplugs 34 composed of a semiconductor material such that thedevice region 18 is unbroken. In an embodiment, the semiconductor material plugs 34 may be composed of an epitaxially-grown semiconductor material, such as silicon, that pinches off to seal and occlude theopenings 22. The semiconductor material constituting theplugs 34 may be the same as the semiconductor material constituting thesemiconductor layer 10. - With reference to
FIG. 5 in which like reference numerals refer to like features inFIG. 4 and at a subsequent fabrication stage, a well 38 is formed in the upper section of thedevice region 18 above theairgap 26 by, for example, ion implantation. Shallowtrench isolation regions 40 are formed that penetrate to a shallow depth into thedevice region 18. The shallowtrench isolation regions 40 may be composed of a dielectric material, such as an oxide of silicon (e.g., silicon dioxide (SiO2)), deposited by chemical vapor deposition (CVD) into trenches etched by a masked etching process in thedevice region 18. - A device structure, generally indicated by
reference numeral 42, may be formed by front-end-of-line (FEOL) processing using thedevice region 18. For example, thedevice structure 42 may be a switch field-effect transistor that includesmultiple gate fingers 44 having a parallel arrangement in rows and connected together at one end. Eachgate finger 44 may include a gate electrode and a gate dielectric formed by depositing a layer stack and patterning the layer stack with photolithography and etching. The gate electrode may be composed of a conductor, such as doped polycrystalline silicon (i.e., polysilicon), and the gate dielectric may be composed of an electrical insulator, such as silicon dioxide (SiO2). Thedevice structure 42 may include other elements such as source/drain regions 46, halo regions, and lightly doped drain (LDD) extensions, as well as non-conductive spacers (not shown) formed on the vertical sidewalls of thegate fingers 44 and abody contact 48 coupled with the well 38. The source/drain regions 46 may be doped with an n-type dopant (e.g., arsenic (As) or phosphorus (P)) selected from Group V of the Periodic Table to produce n-type conductivity, and the well 38 andbody contact 48 may be implanted with ions of a p-type dopant (e.g., boron B)) selected from Group III of the Periodic Table to produce p-type conductivity. - Other types of active device structures may be formed in the device region, such as laterally-diffused metal-oxide-semiconductor (LDMOS) devices, bipolar junction transistors or heterojunction bipolar transistors, etc. In addition, passive device structures may be formed in the
device region 18 in addition to the active device structures or instead of the active device structures. - Middle-of-line (MOL) and back-end-of-line (BEOL) processing follow, which includes formation of
contacts 50 in an interlayer dielectric layer that extend to the source/drain regions 46. The filling of the openings 22 (FIG. 3 ) with the plugs 34 (FIG. 4 ) provides source/drain regions 46 that are solid and unbroken such that thecontacts 50 can land on the source/drain regions 46 at the former locations of theopenings 22. - With reference to
FIG. 6 in which like reference numerals refer to like features inFIG. 5 and in embodiments of the invention, theairgap 26 may be used in conjunction with asubstrate 14 that has a thickness, t2, less than or equal to 100 microns and that includes through-silicon vias 54 extending through the semiconductor layers 10, 12 andsubstrate 14 to ametal layer 52. The through-silicon vias 54 provide vertical electrical connections that pass through the semiconductor layers 10, 12 andsubstrate 14 to establish electrical connections from one side (i.e., a front side) to an opposite side (i.e., a back side). The through-silicon vias 54 may be fabricated by etching via openings that penetrate through the semiconductor layers 10, 12 andsubstrate 14, filling the resulting via openings with a conductor, and performing a back side reveal process. Themetal layer 52 may be deposited on the back side of thesubstrate 14 after the through-silicon vias 54 are fabricated. During the operation of thedevice structure 42, theairgap 26 prevents thesubstrate 14 from being fully depleted across its entire thickness and thereby reduces leakage current. Theairgap 26 may reduce the limitations on the resistivity of thesubstrate 14 such that higher substrate resistivities are achievable without affecting device operation. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. For example, the field-effect transistor and/or handle wafer contact in the embodiments described herein may be used in a switch, a low noise amplifier, or a logic circuit.
- References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
- A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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US11515158B2 (en) | 2020-03-11 | 2022-11-29 | Globalfoundries U.S. Inc. | Semiconductor structure with semiconductor-on-insulator region and method |
US20220406833A1 (en) * | 2020-04-07 | 2022-12-22 | Globalfoundries U.S. Inc. | Photodetector with buried airgap reflectors |
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US11177345B1 (en) | 2020-06-05 | 2021-11-16 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistor |
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