CN104064223A - Flash memory verification apparatus - Google Patents
Flash memory verification apparatus Download PDFInfo
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- CN104064223A CN104064223A CN201310091311.9A CN201310091311A CN104064223A CN 104064223 A CN104064223 A CN 104064223A CN 201310091311 A CN201310091311 A CN 201310091311A CN 104064223 A CN104064223 A CN 104064223A
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Abstract
The invention discloses a flash memory verification apparatus, which comprises a test controller and a characteristic adjusting circuit. The test controller provides supply voltage, and is used for verifying read-write operation of the flash memory. The characteristic adjusting circuit is coupled between the test controller and the flash memory, is controlled by the test controller for determining actuation, and provides supply voltage to the flash memory while actuating. The test controller can actuates the characteristic adjusting circuit during a power supply preparation period, uses supply voltage for starting the flash memory, and the verification apparatus is used for verifying the flash memory.
Description
Technical field
The invention relates to a kind of demo plant, and relate to especially a kind of demo plant of flash memories.
Background technology
Flash memories (Flash Memory) element can repeatedly carry out the actions such as depositing in, read, wipe of data owing to having, and the advantage that the data that deposit in also can not disappear after power-off, so become a kind of non-volatile memory device that PC and electronic equipment extensively adopt.
Generally speaking, manufacturer all can carry out test and the checking of flash memories before shipment, uses filtering defective products, the quality of the flash memories of output to guarantee.In actual application, because flash memories can be widely applicable for the function of different electronic installations with executing data access, wherein the operations specifications of each electronic installation and circuit configurations are each variant, and described operations specifications all may affect reading, write or erase operation of corresponding flash memories with the difference of circuit configurations.In other words, flash memories is in the time being disposed in different electronic installations, and the situation that all may have characteristic deviation occurs, and described characteristic deviation may cause the operation failure of flash memories.
But in the test and validation mechanism of existing flash memories, whether demo plant only can be verified with regard to the default specification of flash memories, and cannot the operation of verification flash memory memory bit under different qualities pass through.Moreover because kind and the specification of electronic installation are various, the state that manufacturer is also difficult to be disposed in each electronic installation for flash memories is verified and tests.
Summary of the invention
The invention provides a kind of demo plant of flash memories, power initiation replacement (power on reset) characteristic of its capable of regulating flash memories, and according to this flash memories is verified.
The present invention proposes a kind of demo plant of flash memories, comprises test controller and performance regulator circuit.Test controller provides supply voltage, and in order to the read-write operation of verification flash memory storer.Performance regulator circuit is coupled between test controller and flash memories, is controlled by test controller and determines whether activation, and in the time of activation, supply voltage being provided to flash memories.Wherein, test controller is rear activation performance regulator circuit between the power supply preparatory stage, in order to using power supply voltage start flash memories, and according to this flash memories is verified.
In an embodiment of the present invention, the operating voltage of flash memories is promoted to gradually operation level from low level within the starting period, the multiple time points of test controller within the starting period sequentially send reading command, with verification flash memory storer within the starting period, read for the first time the time point passing through.
In an embodiment of the present invention, the operating voltage of flash memories is promoted to gradually operation level from low level within the starting period, the multiple time points of test controller within the starting period sequentially send and write instruction, with verification flash memory storer within the starting period, write for the first time the time point passing through.
In an embodiment of the present invention, flash memories has power end, and performance regulator circuit comprises power switch and the first resistance.The first end of power switch couples test controller to receive supply voltage, the second end of power switch couples power end, and the control end of power switch receives the first control signal of test controller, wherein power switch conducting or cut-off according to the first control signal.One end of the first resistance couples the second end and the power end of power switch, and the other end of the first resistance couples ground voltage.
In an embodiment of the present invention, test controller ends power switch after the operating voltage of flash memories is promoted to operation level, operating voltage is reduced gradually, and in the time that operating voltage is down to the first level, test controller again conducting power switch starts flash memories, and sends reading command or write instruction the read-write operation while startup from the first different level with verification flash memory storer.
In an embodiment of the present invention, performance regulator circuit also comprises capacitor cell.Capacitor cell couples the second end and the power end of power switch, wherein capacitor cell is adjusted the equivalent capacity of power end through control, use and control the charge rate of flash memories, test controller send reading command or write instruction with verification flash memory storer the read-write operation under different charge rates.
In an embodiment of the present invention, capacitor cell comprises multiple electric capacity and multiple switch.Described multiple electric capacity has respectively different capacitances.One end of described multiple switches couples respectively described multiple electric capacity, and the other end of described multiple switches couples flash memories, wherein this capacitor cell through control and described in conducting multiple switches one of them, with by the flash memories that is capacitively coupled to of correspondence.
In an embodiment of the present invention, capacitor cell comprises variable capacitance, and wherein capacitor cell is adjusted the capacitance of variable capacitance through control.
In an embodiment of the present invention, test controller is more in order to the erase operation of verification flash memory storer, and demo plant also comprises discharge circuit.Discharge circuit couples performance regulator circuit and flash memories.Discharge circuit is controlled by test controller and determines whether activation, and discharge path is provided in the time of activation.Test controller sends erasing instruction so that flash memories carries out erase operation, and carry out the interior disable feature Circuit tuning of erasing period and the activation discharge circuit of erase operation at flash memories, flash memories is discharged via discharge path, use and check whether flash memories over-erasure (over-erase) occurs.
In an embodiment of the present invention, flash memories has power end, and discharge circuit comprises discharge switch and the second resistance.The first end of discharge switch couples power end, and the control end of discharge switch receives the second control signal of test controller, wherein discharge switch conducting or cut-off according to the second control signal.One end of the second resistance couples the second end of discharge switch, and the other end of the second electricity group couples ground voltage.
In an embodiment of the present invention, test controller is multiple time point disable feature Circuit tunings and the conducting discharge switch in the erase period in order, to check respectively under described multiple time points whether over-erasure occurs.
Based on above-mentioned, the embodiment of the present invention proposes a kind of demo plant of flash memories, it can utilize performance regulator circuit to adjust accordingly the power initiation replacement characteristic of flash memories, make test controller under different power initiation replacement characteristics, to carry out the checking of read-write operation for flash memories, and then promoted the accuracy of checking.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of demo plant of flash memories.
Fig. 2 is the schematic diagram of the power initiation replacement characteristic of flash memories.
Fig. 3 is the schematic diagram of the demo plant of the flash memories of one embodiment of the invention.
Fig. 4 is the circuit diagram according to the demo plant of the flash memories of Fig. 3 embodiment.
The schematic diagram of power initiation replacement characteristic when Fig. 5 is starting from different voltage levels of one embodiment of the invention.
Fig. 6 is the schematic diagram of the power initiation replacement characteristic under the different charge rates of one embodiment of the invention.
Fig. 7 is the schematic diagram of the demo plant of the flash memories of another embodiment of the present invention.
Fig. 8 is the signal schematic representation that the flash memories of one embodiment of the invention carries out erase operation.Fig. 9 is the circuit diagram according to the demo plant of the flash memories of Fig. 7 embodiment.Wherein, description of reference numerals is as follows:
10: flash memories
12: start reset circuit
14: memory circuitry
100,300,400,700,900: demo plant
310,710: test controller
312,712: power supply unit
320,420,720: performance regulator circuit
422: power switch
424,934: resistance
426: capacitor cell
730,930: discharge circuit
932: discharge switch
C1～Cn: electric capacity
CS1: the first control signal
CS2: the second control signal
CUV1, CUV2: family curve
ES1～ES4: stage
DBUS: data bus
SW1～SWn: switch
T0～tn: time point
TD1: the first interdischarge interval
TD2: the second interdischarge interval
TE: between erasing period
TO, TO1, TO2: between the starting period
TP1: first default during
TP2: second default during
TI: during initialization
TS: between the power supply preparatory stage
VCC: operating voltage
VDD: supply voltage
V1, V1 ': level
VL: low level
VI: initialization level
VW: operation level
VWL: minimum operation level
Embodiment
Fig. 1 is a kind of schematic diagram of demo plant of flash memories.The manufacturer of general flash memories all can utilize demo plant 100 as shown in Figure 1 to carry out the read-write operation of verification flash memory storer before shipment.Please refer to Fig. 1, demo plant 100 can provide supply voltage VDD to give flash memories 10, makes the startup reset circuit 12 of flash memories 10 react on received supply voltage VDD and produce operating voltage VCC.Then, the memory circuitry of flash memories 10 14 can carry out initialization and start according to starting the operating voltage VCC that reset circuits 12 produce, to make flash memories 10 can normally carry out read-write operation.
After flash memories 10 starts, demo plant 100 can send reading command or write instruction to flash memories 10 via data bus dbus, makes flash memories 10 carry out the corresponding operation of reading or writing according to the instruction receiving.Then, flash memories 10 can be back to via data bus dbus the result that reads or write in demo plant 100, and the read/write instruction that demo plant 100 can be sent out by comparison and the read/write result receiving are carried out the read-write operation of verification flash memory storer 10 for passing through (pass) or lost efficacy (fail).
In the time that flash memories 10 is disposed at different electronic installations, the power initiation of flash memories 10 is reset (power-on reset) characteristic can be according to the change to some extent with circuit configurations of the operations specifications of corresponding electronic installation.The change of described power initiation replacement characteristic may impact the initialization of memory circuitry 14 or read-write operation, and then makes reading and writing generation extremely of flash memories 10.But the abnormality of this type is difficult to utilize demo plant 100 to detect conventionally.
Below, describe simply with regard to the power initiation replacement characteristic of flash memories 10, wherein the power initiation replacement characteristic of flash memories 10 as shown in Figure 2.Referring to Fig. 1 and Fig. 2, in the time that flash memories 10 receives supply voltage VDD, starting reset circuit 12 can react on supply voltage VDD and produce the such as 0V from low level VL(between the starting period in TO) be promoted to gradually such as 3V of operation level VW() operating voltage VCC, wherein memory circuitry 14 can be during operating voltage VCC be promoted to initialization level VI from low level VL in (TI during being initialization) carry out initialization, and finish initialized action in the time that operating voltage VCC exceedes initialization level VI.Between the starting period, after TO, operating voltage VCC is stably maintained at operation level VW.
Generally speaking, flash memories 10 operating voltage VCC reach minimum operation level VWL and default through one section first during can successfully carry out read operation after for example 10 microseconds of TP1((μ s)), and flash memories 10 reaches initialization level VI(at operating voltage VCC and completes initialization) and default through one section second during TP2(for example 1 millisecond (ms)) after can successfully carry out write operation.Therefore, flash memories 10 can be according to the access requirement of corresponding electronic installation, and reads for the first time or write in the time that its operating voltage VCC not yet arrives operation level VW.But, it should be noted that flash memories 10 reality can successfully carry out the time point of read operation and write operation for the first time for the first time and also can be subject to the impact of the factor such as circuit design or technique and variation to some extent.
In the time of demo plant 100 verification flash memory storer 10, demo plant 100 can utilize TS between one period of power supply preparatory stage to stablize the supply voltage VDD that it provides, and after provided supply voltage VDD is stable, just sends reading command or write instruction and carry out verification flash memory storer 10, use the authentication error of avoiding causing because supply voltage VDD is unstable flash memories 10.Wherein, between the power supply preparatory stage, TS needs the extremely time of hundreds of milliseconds of tens of milliseconds conventionally.In comparison, flash memories 10 is after startup, and between its starting period, TO only needs the extremely time of several milliseconds of several microseconds.Therefore,, after TS between the power supply preparatory stage, operating voltage VCC is stably maintained at operation level VW conventionally.
In other words, demo plant 100 only can be between the power supply preparatory stage after TS, the flash memories 10 operating under stable operating voltage VCC is carried out to the checking of read-write operation, and cannot verify for flash memories 10 read-write operation for the first time in TO between the starting period.Therefore, demo plant 100 also cannot be measured the time point that flash memories 10 successfully reads for the first time in TO/writes for the first time between the starting period.
On the other hand, in the time that flash memories 10 is disposed in the electronic installation of different size or kind, because the equivalent capacity of the power end of flash memories 10 can be subject to the impact of different operations specifications and circuit configurations and change to some extent, thereby the charge rate of flash memories 10 is affected, wherein the charge rate of flash memories 10 refers to that operating voltage VCC is promoted to the required time of operation level VW from low level VL.The difference of charge rate can directly have influence on the length of TI during the initialization of flash memories, and during different initialization, TI may cause the initialization mistake of memory circuitry 14, and then causes the read-write operation of flash memories 10 abnormal.
In addition, in the time that flash memories 10 is closed during normal running, operating voltage VCC can be down to low level VL gradually from operation level VW, so that flash memories 10 while again starting, can carry out initialized action before operating voltage VCC is promoted to initialization level VI.In other words, memory circuitry 14 need start under lower than the state of initialization level VI and just can carry out initialized action at operating voltage VCC.But because initialization level VI may depart from because of the impact of circuit design or technique the design load of expection, the skew of initialization level VI may make the operation of flash memories 10 that unexpected mistake occurs.For example, be not yet down to initialization level VI while starting once again when flash memories 10 at operating voltage VCC, flash memories 10 can cause read-write operation abnormal because of not carrying out initialized action.Therefore actual value, how to verify initialization level VI is also considerable problem.
Hence one can see that, and the parameter that flash memories 10 can successfully carry out the power initiation replacement characteristics such as time, charge rate and the initialization level of read/write for the first time all affects the key factor of flash memories 10 read-write operations.But demo plant 100 only can be verified with regard to the default specification of flash memories 10, and cannot be verified for each above-mentioned parameter.
In order to address the above problem, the present embodiment proposes a kind of framework of demo plant, as shown in Figure 3.Fig. 3 is the schematic diagram of the demo plant of the flash memories of one embodiment of the invention.Please refer to Fig. 3, demo plant 300 comprises test controller 310 and performance regulator circuit 320.Test controller 310 provides supply voltage VDD, and in order to the read-write operation of verification flash memory storer 10.Performance regulator circuit 320 is coupled between test controller 310 and flash memories 10, is controlled by test controller 310 and determines whether activation, and in the time of activation, supply voltage VDD being provided to flash memories 10.
Specifically, connect flash memories to be measured 10 when starting checking machine-processed at demo plant 300, the power supply unit 312 of test controller 310 can output supply voltage VDD, and within one period of power supply preparatory stage, carry out the action of stabilized supply voltage VDD.Wherein, power supply unit 312 is coupled to flash memories 10 so that supply voltage VDD to be provided via performance regulator circuit 320.Because performance regulator circuit 320 has the function of similar switch, therefore in the time that not being enabled, it supply voltage VDD can't be provided to flash memories 10.In other words, flash memories 10 can't be started by supply voltage VDD within the power supply preparatory stage.
After between the power supply preparatory stage, test controller 310 activation performance regulator circuits 320, performance regulator circuit 320 is provided supply voltage VDD to flash memories 10, react on supply voltage VDD and produce operating voltage VCC so that start reset circuit 12, and make according to this memory circuitry 14 carry out initialization and start.In the present embodiment, because power supply unit 312 is adjusted to stable state by supply voltage VDD in the power supply preparatory stage before flash memories 10 starts, therefore test controller 310 can send immediately reading command or write instruction the read-write operation that carrys out verification flash memory storer 10 in the time that flash memories 10 starts.
More particularly, referring to Fig. 2 and Fig. 3, because supply voltage VDD was adjusted to stable before flash memories 10 starts, therefore test controller 310 can send reading command by the multiple time points in TO between the starting period, reads for the first time the time point passing through with verification flash memory storer 10 between the starting period in TO.Similarly, test controller 310 also can be between the starting period the multiple time points in TO send and write instruction, between the starting period, in TO, write for the first time the time point passing through with verification flash memory storer 10.
For instance, in the time that proving installation 300 carries out the read operation checking of flash memories 10, test controller 310 can be after initialization completes, with interval time of fixing (for example 1 μ s) sends reading command, and carry out verification flash memory storer 10 according to the reading result of flash memories 10 read for the first time the time point passing through.Similarly, in the time that demo plant 300 carries out the write operation checking of flash memories 10, test controller 310 can be after initialization completes, write instruction to send the interval time of fixing, and according to flash memories 10 write that result carrys out verification flash memory storer 10 write for the first time the time point passing through.
In order to be illustrated more clearly in the embodiment of the present invention, Fig. 4 is the circuit diagram according to the demo plant of the flash memories of Fig. 3 embodiment.Please refer to Fig. 4, demo plant 400 comprises test controller 310 and performance regulator circuit 420, and wherein performance regulator circuit 420 comprises power switch 422, resistance 424 and capacitor cell 426.
In the present embodiment, the first end of power switch 422 couples the supply voltage VDD that test controller 310 is produced to receive power supply unit 312, the second end of power switch 422 couples the power end PT of flash memories 10, and the control end of power switch 422 couples test controller 310, the first control signal CS1 being provided to receive test controller 310.Wherein, power switch 422 can conducting or cut-off according to the first control signal CS1.One end of resistance 424 couples the second end and the power end PT of power switch 422, and the other end of resistance 424 couples ground voltage GND.426 of capacitor cells couple the second end and the power end PT of power switch 422.
In this, though power switch 422 illustrates taking BJT transistor as example.But in other embodiments, described power switch 422 also can utilize MOS transistor to realize, and the present invention is not as limit.
According to the circuit framework of performance regulator circuit 420, test controller 310 can export the first control signal CS1 to the transistorized base stage of BJT and control the transistorized conducting of BJT or cut-off with the first control signal CS1 that utilizes respectively activation and forbidden energy.Furthermore, test controller 310 can be after power supply unit 312 can provide stable supply voltage VDD, the first control signal CS1 of output enable is with conducting BJT transistor, and according to this supply voltage VDD is provided to flash memories 10, use the checking of the read/write for the first time that realizes the flash memories 10 described in above-described embodiment.
On the other hand, further actual value and the flash memories 10 of the initialization level of verification flash memory storer 10 are positioned at the read-write operation under different charge rates at operating voltage VCC to demo plant 400.First, just utilize the verification operation of the actual value of the initialization level of demo plant 400 verification flash memory storeies 10 to describe.
Referring to Fig. 4 and Fig. 5, wherein, the schematic diagram of power initiation replacement characteristic when what Fig. 5 was one embodiment of the invention starts from different voltage levels.In the time of the initialization level of verification flash memory storer 10, first, test controller 310 can first provide supply voltage VDD according to aforesaid mode, makes the operating voltage VCC of flash memories 10 be promoted to gradually operation level VW.Be promoted to after operation level VW at operating voltage VCC, test controller 310 is exported the first control signal CS1 of forbidden energy with cut-off power switch 422, flash memories 10 is discharged via resistance 424, and make operating voltage VCC reduce gradually.
In the present embodiment, the initial level of operating voltage VCC when user can be adjusted flash memories 10 and started by the length during controlled discharge, so that the read-write operation state that demo plant 400 verification flash memory storeies 10 start under different initial levels.More particularly, in demo plant 400, the path that resistance 424 in performance regulator circuit 420 can provide flash memories 10 to discharge, flash memories 10 can be discharged to internal linear during supply voltage VDD closes, and therefore user can control by the time length of decision forbidden energy the first control signal CS1 the initial level of operating voltage VCC.Whether the read-write operation state that by this, user can start according to flash memories 10 under different initial levels judges the actual value of initialization level VI extremely.
For instance, test controller 310 can be through setting and mono-section of first interdischarge interval TD1 of forbidden energy the first control signal CS1, so that the level of operating voltage VCC is down to gradually the first level V1 from operation level VW in the first interdischarge interval TD1, and after the first interdischarge interval TD1 activation the first control signal CS1 again.After the first interdischarge interval TD1, test controller 310 is understood activation the first control signal CS1 and conducting power switch 422, use and restart flash memories 10, and send reading command or write instruction the read-write operation while startup from level V1 with verification flash memory storer 10.Now, because level V1 is lower than actual initialization level VI, therefore demo plant 400 can judge that flash memories 10 can normally carry out new read-write operation under this test condition.
Similarly, test controller 310 can utilize similar above-mentioned mode to control flash memories 10 and discharge in one section of second interdischarge interval TD2 through setting, so that flash memories 10 restarts under level V1 ', so that test controller 310 can send reading command or write instruction the read-write operation while startup from level V1 ' with verification flash memory storer 10.Now, because level V1 ' is higher than actual initialization level VI, flash memories 10 can't carry out initialized action, and therefore demo plant 400 can judge that flash memories 10 cannot normally carry out new read-write operation under this test condition.
Because the numerical value of level V1 and V1 ' all can be learnt by measurement, therefore user can judge that the actual value of initialization level VI is to be positioned between level V1 and V1 ' according to the result of above-mentioned verification operation.Wherein, though above-described embodiment describe as example to get two different initial level V1 and V1 ', but the present invention is not as limit.In actual application, the sampling number of verification operation and the numerical value of initial level all can be adjusted to some extent according to user's demand.
On the other hand, with regard to utilizing the read-write operation of demo plant 400 verification flash memory storeies 10 under different charge rates, referring to Fig. 4 and Fig. 6, wherein, the schematic diagram of the power initiation replacement characteristic under the different charge rates that Fig. 6 is one embodiment of the invention.In the present embodiment, capacitor cell 426 can be adjusted through control the equivalent capacity of the power end PT of flash memories 10, uses the charge rate of controlling flash memories 10.Specifically, capacitor cell 426 can be through user's manual control, or automatically controlled and adjusted its capacitance by test controller 310.In the time having the capacitor cell 426 of different capacitances and be coupled to the power end PT of flash memories 10, operating voltage VCC can react on the equivalent capacity of power end PT and have different family curve (as CUV1 and CUV2).
For instance, in the time that capacitor cell 426 is adjusted to little capacitance, operating voltage VCC can be corresponding to family curve CUV1.Now, flash memories 10 can have TO1 between higher charge rate and shorter starting period.On the contrary, in the time that capacitor cell 426 is adjusted to large capacitance, operating voltage VCC can be corresponding to family curve CUV2.Now, flash memories 10 can have TO2 between lower charge rate and longer starting period.Therefore, test controller 310 can send reading command or write instruction having the flash memories 10 of family curve CUV1 and CUV2 respectively, uses the read-write operation of verification flash memory storer 10 under different charge rates.
In the present embodiment, described capacitor cell 426 can utilize the circuit framework of switch SW 1～SWn of multiple capacitor C 1～Cn and each capacitor C of multiple correspondence 1～Cn to realize.Wherein, each capacitor C 1～Cn has respectively different capacitances, and one end of switch SW 1～SWn coupling capacitance C1～Cn respectively, and the other end of switch SW 1～SWn couples the power end PT of flash memories 10.Under this circuit framework, user can manually control or utilize test controller 310 automatically to control conducting or the cut-off of each switch SW 1～SWn, make to be coupled to according to demand corresponding to capacitor C 1～Cn of each switch SW 1～SWn the power end PT of flash memories 10, use the equivalent capacity that changes power end PT.
In addition, capacitor cell 426 also can be realized by variable capacitance, and wherein the capacitance of variable capacitance can manually be adjusted by user, or is automatically adjusted by test controller 310, and the present invention is not as limit.
Referring again to Fig. 1, in demo plant 100, except the read-write operation checking to flash memories 10 has as the aforementioned problem.Demo plant 100 also cannot in order to flash memories 10 erase operation in the erase period verify.Specifically, referring to Fig. 1 and Fig. 8, generally speaking, in the time that flash memories 10 carries out erase operation, flash memories can carry out the erasing move of multiple different phases (as ES1～ES4) between an erasing period in TE, to wipe a section (sector) or block (block).Wherein, between a complete erasing period TE conventionally need to about 30ms to 300ms between.If in the erase period in TE, the unexpected power-off of flash memories 10, in memory circuitry 14, the erase operation of the corresponding storage unit being wiped free of may be because discharging too much electronics with positive charge, that is the phenomenon of over-erasure (over-erase) has occurred, and may make flash memories 10 after restarting, the read-write operation of adjoining memory cell be lost efficacy.Wherein, the Probability that all may affect over-erasure phenomenon is considered in design of the technique of flash memories 10, circuit design and erasing instruction etc.
Furthermore, in actual applications, deviser is still difficult to the phenomenon of the no generation over-erasure of discovery meeting in the stage of design and simulation, only utilizes the checking action of rear end that the flash memories of over-erasure can filtering easily occurs.But because demo plant 100 is also verified flash memories 10 in TE in the erase period, therefore the phenomenon of above-mentioned over-erasure also cannot be detected by demo plant 100.
In order to address the above problem, the present embodiment more proposes a kind of framework of demo plant, as shown in Figure 7.Fig. 7 is the schematic diagram of the demo plant of the flash memories of another embodiment of the present invention.Please refer to Fig. 7, demo plant 700 comprises test controller 710, performance regulator circuit 720 and discharge circuit 730.Test controller 710 provides supply voltage VDD, and reading, writing and erase operation in order to verification flash memory storer 10.Performance regulator circuit 720 is coupled between test controller 710 and flash memories 10, is controlled by test controller 710 and determines whether activation, and in the time of activation, supply voltage VDD being provided to flash memories 10.Discharge circuit 730 couples performance regulator circuit 720 and flash memories 10, and wherein discharge circuit 730 is controlled by test controller 710 and determines whether activation, and in the time of activation, provides flash memories 10 1 discharge paths.
In the present embodiment, demo plant 700 is except utilizing the verification mode of above-described embodiment to come the read-write operation of verification flash memory storer 10, and demo plant 700 also can be in order to the erase operation of verification flash memory storer 10.Referring to Fig. 7 and Fig. 8, in the time that demo plant 700 carries out the checking of erase operation to flash memories 10, test controller 710 can send erasing instruction so that flash memories 10 carries out erase operation.Carry out between the erasing period of erase operation in TE at flash memories 10, test controller 710 can be in the lower disable feature Circuit tuning 720 of particular point in time (as t0～tn) and activation discharge circuit 730, the discharge path that flash memories 10 is provided via discharge circuit 730 discharges, under the particular point in time in TE in the erase period, operating voltage VCC is down to low level rapidly and closes flash memories 10.Then, test controller 710 can check whether the signal of each storage unit in memory circuitries 14 meets desired value, uses erase operation under this particular point in time of verifying in TE in the erase period and whether occur the phenomenon of over-erasure.
Fig. 9 is the circuit diagram according to the demo plant of the flash memories of Fig. 7 embodiment.Please refer to Fig. 9, demo plant 900 comprises test controller 710, performance regulator circuit 420 and discharge circuit 930.Wherein, performance regulator circuit 420 comprises power switch 422, resistance 424 and capacitor cell 426.Discharge circuit comprises discharge switch 932 and resistance 934.
In the present embodiment, the first end of power switch 422 couples the supply voltage VDD that test controller 710 is produced to receive power supply unit 712, the second end of power switch 422 couples the power end PT of flash memories 10, and the control end of power switch 422 couples test controller 710, the first control signal CS1 being provided to receive test controller 710.Wherein, power switch 422 can conducting or cut-off according to the first control signal CS1.One end of resistance 424 couples the second end and the power end PT of power switch 422, and the other end of resistance 424 couples ground voltage GND.426 of capacitor cells couple the second end and the power end PT of power switch 422.
The first end of discharge switch 932 couples power end PT, and the control end of discharge switch 932 receives the second control signal CS2 that test controller 710 is exported, wherein discharge switch 932 conducting or cut-off according to the second control signal CS2.One end of resistance 934 couples the second end of discharge switch 932, and the other end of resistance 934 couples ground voltage GND.
In this, though discharge switch 932 illustrates taking BJT transistor as example.But in other embodiments, described discharge switch 932 also can utilize MOS transistor to realize, and the present invention is not as limit.In addition, the circuit operation of the performance regulator circuit 420 of the present embodiment and related description please refer to above-mentioned Fig. 4 embodiment, repeat no more in this.
In the present embodiment, according to the framework of discharge circuit 930, test controller 710 can export the second control signal CS2 to the base stage of discharge switch 932 to utilize respectively the second control signal CS2 of activation and forbidden energy to come conducting or the cut-off of controlled discharge switch 932.Furthermore, test controller 710 can be in order multiple time point t0～tn disable feature Circuit tuning 720 and the conducting discharge switch 932 respectively in TE in the erase period, so that test controller 710 checks respectively the phenomenon whether over-erasure occurs under time point t0～tn, wherein the interval between each time point t0～tn is for example 1ms, this numerical value can be set according to design requirement, and the present invention is not as limit.
In addition, in another embodiment, test controller 710 also can be chosen the several time points in TE between erasing period and disable feature Circuit tuning 720 and conducting discharge switch 932 randomly, so that test controller 710 checks flash memories 10 phenomenon of generation meeting over-erasure whether under the selected time point of getting, use in the situation that significant impact is not verified accuracy, effectively reduce the checking required time of expending of erase operation.
In sum, the embodiment of the present invention proposes a kind of demo plant of flash memories, it can utilize performance regulator circuit to adjust accordingly the power initiation replacement characteristic of flash memories, make test controller under different power initiation replacement characteristics, to carry out the checking of read-write operation for flash memories, and then promoted the accuracy of checking.In addition, whether the demo plant of the embodiment of the present invention more can cause in order to the erase operation of verification flash memory storer under in the erase period interior multiple time points the phenomenon of over-erasure.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; technician in technical field under any; not departing from the spirit and scope of the claims in the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim scope of the applying for a patent person of defining.
Claims (11)
1. a demo plant for flash memories, is characterized in that, comprising:
One test controller, provides a supply voltage, and in order to verify the read-write operation of this flash memories; And
One performance regulator circuit, is coupled between this test controller and this flash memories, and be controlled by this test controller and determine whether activation, and in the time of activation, this supply voltage being provided to this flash memories,
Wherein this test controller rear this performance regulator circuit of activation between a power supply preparatory stage, to utilize this flash memories of this power supply voltage start, and verifies this flash memories according to this.
2. the demo plant of flash memories as claimed in claim 1, it is characterized in that, wherein an operating voltage of this flash memories is promoted to gradually an operation level from a low level within a starting period, the multiple time points of this test controller within this starting period sequentially send a reading command, to verify that this flash memories reads for the first time the time point passing through within this starting period.
3. the demo plant of flash memories as claimed in claim 1, it is characterized in that, wherein an operating voltage of this flash memories is promoted to gradually an operation level from a low level within a starting period, the multiple time points of this test controller within this starting period sequentially send one and write instruction, to verify that this flash memories writes for the first time the time point passing through within this starting period.
4. the demo plant of flash memories as claimed in claim 1, is characterized in that, wherein this flash memories has a power end, and this performance regulator circuit comprises:
One power switch, its first end couples this test controller to receive this supply voltage, its second end couples this power end, and its control end receives one first control signal of this test controller, wherein this power switch conducting or cut-off according to this first control signal; And
One first resistance, its one end couples the second end and this power end of this power switch, and its other end couples a ground voltage.
5. the demo plant of flash memories as claimed in claim 4, it is characterized in that, wherein this test controller ends this power switch after an operating voltage of this flash memories is promoted to an operation level, this operating voltage is reduced gradually, and in the time that this operating voltage is down to first level, this test controller again this power switch of conducting starts this flash memories, and sends a reading command or and write the read-write operation of instruction when verifying that this flash memories starts from different these first level.
6. the demo plant of flash memories as claimed in claim 4, is characterized in that, wherein this performance regulator circuit also comprises:
One capacitor cell, couple the second end and this power end of this power switch, wherein this capacitor cell is adjusted the equivalent capacity of this power end through control, use a charge rate of controlling this flash memories, this test controller sends a reading command or and writes instruction to verify the read-write operation of this flash memories under this different charge rates.
7. the demo plant of flash memories as claimed in claim 6, is characterized in that, wherein this capacitor cell comprises:
Multiple electric capacity, wherein the plurality of electric capacity has respectively different capacitances; And
Multiple switches, its one end couples respectively the plurality of electric capacity, and its other end couples this flash memories, wherein this capacitor cell through control and the plurality of switch of conducting one of them, so that corresponding electric capacity is coupled to this flash memories.
8. the demo plant of flash memories as claimed in claim 6, is characterized in that, wherein this capacitor cell comprises:
One variable capacitance, wherein this capacitor cell is adjusted the capacitance of this variable capacitance through control.
9. the demo plant of flash memories as claimed in claim 1, is characterized in that, wherein this test controller is more in order to verify the erase operation of this flash memories, and this demo plant also comprises:
One discharge circuit, couples this performance regulator circuit and this flash memories, and be controlled by this test controller and determine whether activation, and a discharge path is provided in the time of activation,
Wherein this test controller sends an erasing instruction so that this flash memories carries out erase operation, and carry out interior this performance regulator circuit of forbidden energy of an erasing period and this discharge circuit of activation of erase operation at this flash memories, make this flash memories via this discharge path fast break, use check this flash memories whether there is over-erasure.
10. the demo plant of flash memories as claimed in claim 9, is characterized in that, wherein this flash memories has a power end, and this discharge circuit comprises:
One discharge switch, its first end couples this power end, and its control end receives one second control signal of this test controller, wherein this discharge switch conducting or cut-off according to this second control signal; And
One second resistance, its one end couples the second end of this discharge switch, and its other end couples a ground voltage.
The demo plant of 11. flash memories as claimed in claim 10, it is characterized in that, wherein this test controller multiple these performance regulator circuits of time point forbidden energy and this discharge switch of conducting in this erasing period in order, to check respectively whether over-erasure occurs under the plurality of time point.
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| CN201310091311.9A CN104064223B (en) | 2013-03-20 | 2013-03-20 | Flash memory verification apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106291300A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Chip pressure drop, the method for testing of structure and chip improved method |
| CN113961419A (en) * | 2021-09-24 | 2022-01-21 | 北京百度网讯科技有限公司 | Memory verification method and device, electronic equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030031049A1 (en) * | 1992-12-03 | 2003-02-13 | Fujitsu Limited | Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| CN1435845A (en) * | 2002-02-02 | 2003-08-13 | 三星电子株式会社 | Non-Volatile semiconductor memory with charging read mode |
| CN104064222A (en) * | 2013-03-20 | 2014-09-24 | 华邦电子股份有限公司 | Verification apparatus for flash memory |
-
2013
- 2013-03-20 CN CN201310091311.9A patent/CN104064223B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030031049A1 (en) * | 1992-12-03 | 2003-02-13 | Fujitsu Limited | Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics |
| CN1435845A (en) * | 2002-02-02 | 2003-08-13 | 三星电子株式会社 | Non-Volatile semiconductor memory with charging read mode |
| CN104064222A (en) * | 2013-03-20 | 2014-09-24 | 华邦电子股份有限公司 | Verification apparatus for flash memory |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106291300A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Chip pressure drop, the method for testing of structure and chip improved method |
| CN113961419A (en) * | 2021-09-24 | 2022-01-21 | 北京百度网讯科技有限公司 | Memory verification method and device, electronic equipment and storage medium |
| CN113961419B (en) * | 2021-09-24 | 2022-09-23 | 北京百度网讯科技有限公司 | Memory verification method and device, electronic equipment and storage medium |
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| CN104064223B (en) | 2017-04-26 |
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