CN104064161B - Data transmission system applied to display and operation method - Google Patents
Data transmission system applied to display and operation method Download PDFInfo
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Abstract
The invention discloses a data transmission system applied to a display, which comprises a transmitting end and a receiving end. The transmitting terminal is used for receiving the first clock signal and providing a display data stream according to the first clock signal. The receiving end comprises an error detection module and a clock data recovery circuit. The error detection module is used for judging whether the display data stream received by the receiving end has errors according to the second clock pulse signal and providing an error signal to the transmitting end according to the judgment result so that the transmitting end transmits the clock pulse calibration signal through the display data stream. The clock data recovery circuit is used for updating the second clock signal according to the clock calibration signal.
Description
Technical field
The invention relates to a kind of electronic system.Particularly a kind of data transmission system and method for operating being applied to display.
Background technology
Along with the rapid progress of electronics technology, display has been widely used in the middle of the life of people, such as mobile phone or notebook computer etc.
Generally speaking, display can comprise time schedule controller and source electrode driver.Time schedule controller can provide image data to source electrode driver by data transmission interface, is provided suitable data voltage to the pixel in display to make source electrode driver.Pixel upgrades its display state (such as color and GTG) according to data voltage.By this, display and capable of displaying image.
In traditional method, time schedule controller transmits clock signal and image data to source electrode driver through different transmission channels respectively.But under way like this, clock signal and image data be the misalignment each other because of transmission delay easily, makes source electrode driver correctly cannot receive image data, and causes the instability of display.
Therefore how to solve the important research direction that this problem is this area.
Summary of the invention
An aspect of the present invention is for providing a kind of data transmission system being applied to display.According to one embodiment of the invention, data transmission system comprises transmission end and receiving end.Transmission end in order to produce the first clock signal, and in order to provide display data stream according to the first clock signal.Receiving end is in order to receive display data stream.Receiving end comprises debug module and clock data recovery circuit.Debug module, in order to according to the second clock signal, judges whether the display data stream that receiving end receives has mistake, and in order to provide rub-out signal to transmission end according to judged result, to make transmission end transmission display data stream clock pulse calibrating signal.Clock data recovery circuit is in order to upgrade the second clock signal according to clock pulse calibrating signal.
Another aspect of the present invention is for providing a kind of method of operating being applied to display.According to one embodiment of the invention, display comprises transmission end and receiving end.Method of operating comprises: through transmission end, provides display data stream according to the first clock signal; Through receiving end, receive display data stream, judge whether display data stream has mistake according to the second clock signal, and provide a rub-out signal according to judged result; Through transmission end, according to rub-out signal, transmit a clock pulse calibration data by display data stream; And through receiving end, upgrade the second clock signal according to clock pulse calibration data.
Through the above-mentioned embodiment of application, in display data stream, transmit clock pulse calibrating signal, can avoid clock signal and image data because of transmission delay misalignment each other, to improve the degree of stability of display.In addition, utilize debug module to carry out error detection to display data stream, transmission end can be notified when mistake appears in display data stream, carry out corresponding Wrong control according to this to make transmission end.Thus, the degree of stability of display can further be improved.
Accompanying drawing explanation
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, the description of the drawings is as follows:
The schematic diagram of display of Fig. 1 for illustrating according to one embodiment of the invention;
The schematic diagram of data transmission system of Fig. 2 for illustrating according to one embodiment of the invention;
The schematic diagram of transmission end of Fig. 3 A for illustrating according to one embodiment of the invention;
The schematic diagram of receiving end of Fig. 3 B for illustrating according to one embodiment of the invention;
The schematic diagram of display data stream of Fig. 4 for illustrating according to one embodiment of the invention;
The process flow diagram of method of operating of Fig. 5 for illustrating according to one embodiment of the invention; And
The schematic diagram of display data stream of Fig. 6 for illustrating according to the present invention one operational example.
Wherein, Reference numeral:
10: display
20: time schedule controller
30: source electrode driver
40: gate drivers
100: data transmission system
104: pel array
106: pixel
110: transmission end
111: phase-locked loop
112: scrambler
113: processor
114: converter
115: forwarder
120: receiving end
121: receiver
122: clock data recovery circuit
123: converter
124: debug module
125: demoder
126: control module
G (1)-G (N): sweep signal
D (1)-D (M): data-signal
DS-S: display data stream
DS-P: display data stream
LK: rub-out signal
CLK1: the first clock signal
CLK2: the second clock signal
CONF: setting data
DT: image data
DT-E: the image data after coding
FM: frame data
L (1)-L (N): data frame
CN: data frame
VB: data frame
H-BK: horizontal blanking code
V-BK: vertical blanking code
BAC: bit synchronization code
CTRL: control code
EOL: end code
TAJ: clock pulse calibrating signal
S1-S13: step
T0-t11: time point
Embodiment
Below by with accompanying drawing and describe the spirit clearly demonstrating content of the present invention in detail, any person of ordinary skill in the field is after the preferred embodiment understanding content of the present invention, when can by the technology of content institute of the present invention teaching, be changed and revise, it does not depart from spirit and the scope of content of the present invention.
About " first " used herein, " second " etc., the not special meaning of censuring order or cis-position, is also not used to limit the present invention, and it is only in order to distinguish the element or operation that describe with constructed term.
About " electric connection " used herein, can refer to two or multiple element mutually directly make entity or in electrical contact, or mutually indirectly put into effect body or in electrical contact, and " electric connection " also can refer to two or multiple element mutual operation or action.
About " comprising " used herein, " comprising ", " having ", " containing " etc., be open term, namely mean including but not limited to.
About used herein " and/or ", comprise the arbitrary of described things or all combine.
About term used herein " roughly ", " about " etc., in order to modify any can the quantity of slight variations or error, but this slight variations or error can't change its essence.Generally speaking, the scope of the slight variations that this type of term is modified or error is 20%, is 10% in part preferred embodiment, is 5% in the better embodiment of part.
About word used herein (terms), outside indicating especially, usually have each word use in this area, in content disclosed herein with the usual meaning in special content.Some is in order to describe word of the present invention by lower or discuss in the other places of this instructions, to provide those skilled in the art guiding extra in description for the present invention.
An aspect of the present invention is for providing a kind of data transmission system.In the examples below, the display panel internal transmission interface (intra-panelinterface) for a display is described, but the present invention is not as limit.
The schematic diagram of display 10 of Fig. 1 for illustrating according to the embodiment of the present invention.Display 10 can comprise time schedule controller 20, source electrode driver 30, gate drivers 40 and pel array 104.Time schedule controller 20 is electrically connected source electrode driver 30 and gate drivers 40 respectively.Source electrode driver 30 and gate drivers 40 are electrically connected pel array.Pel array 104 can comprise multiple with the pixel 106 of matrix arrangement.Time schedule controller 20 can provide and control signal to gate drivers 40, with make gate drivers 40 sequentially provide multiple sweep signal G (1) ..., G (N) is to the pixel 106 in pel array 104, with by column/on-pixel 106 line by line, wherein N is natural number.In addition, time schedule controller 20 can provide display data to source electrode driver 30, with make source electrode driver 30 provide according to this data-signal D (1) ..., D (M) give open pixel 106, to make the pixel 106 of opening upgrade its display state (such as color and GTG), wherein M is natural number.Thus, image can show on display 10.
In some ways, time schedule controller 20 provides clock signal and image data to source electrode driver 30 respectively.But under way like this, clock signal and image data be the misalignment each other because of transmission delay easily, makes source electrode driver 30 correctly cannot receive image data, and causes the instability of display 10.Therefore in one embodiment of this invention, can pass through and provide a kind of new data transmission system 100 between time schedule controller 20 and source electrode driver 30, to improve the stability of display 10.
The schematic diagram of data transmission system 100 of Fig. 2 for illustrating according to the embodiment of the present invention.In the present embodiment, data transmission system 100 comprises transmission end 110 and multiple receiving end 120, and wherein transmission end 110 is arranged in time schedule controller 20, and receiving end 120 lays respectively in different source electrode drivers 30, and is electrically connected transmission end 110 respectively.In certain embodiments, this little source electrode driver 30 respectively in order to outputting data signals to the pixel 106 of different lines.In addition, when noticing, in the present embodiment, though be described for 6 source electrode drivers 30 and receiving end 120, however in fact the quantity of source electrode driver 30 and receiving end 120 not as limit.In different embodiments, the quantity of source electrode driver 30 and receiving end 120 can change according to actual demand.
In the present embodiment, time schedule controller 20 is through data transmission system 100 and links up each other with source electrode driver 30.Such as, time schedule controller 20 can pass through data transmission system 100 and transmits display data stream DS-S to source electrode driver 30.On the other hand, when source electrode driver 30 finds mistake (being such as find the mistake of himself or the mistake of display data stream DS-S), the data transmission system 100 that can pass through source electrode driver 30 transmits rub-out signal LK to time schedule controller 20, to represent that source electrode driver 30 self is in error condition, with the relevant control making time schedule controller 20 be carried out debug.
In the present embodiment, the transmission channel of single line is can be in order to the transmission channel of error of transmission signal LK.That is each source electrode driver 30 all provides rub-out signal LK to time schedule controller 20 through identical transmission channel.When any one in source electrode driver 30 is in error condition, namely this one source pole driver 30 provides rub-out signal LK (being such as the signal of a low voltage level) so far transmission channel, with the relevant control making time schedule controller 20 carry out debug.Through way so, the area shared by transmission channel can be reduced.
It should be noted that, in different embodiments, source electrode driver 30 also can utilize many transmission channel error of transmission signal LK, and the present invention is not limited with above-described embodiment.
The schematic diagram of transmission end 110 of Fig. 3 A for illustrating according to one embodiment of the invention.In the present embodiment, transmission end 110 comprises phase-locked loop 111, scrambler 112, processor 113, converter 114 and forwarder 115.Phase-locked loop 111 is electrically connected scrambler 112, processor 113 and converter 114.Scrambler 112 is electrically connected process device 113.Processor 113 is electrically connected converter 114.Converter 114 is electrically connected forwarder 115.In the present embodiment, phase-locked loop 111, scrambler 112, processor 113, converter 114 and forwarder 115 all can with concrete circuit realiration.
Those skilled in the art work as can be clear, the implementation of above-mentioned phase-locked loop 111, scrambler 112, processor 113, converter 114 and forwarder 115 is not with being limited disclosed in above-described embodiment, and annexation is not also limited with above-described embodiment, all be enough to make transmission end 110 to realize following technology contents connected mode and implementation all can apply to the present invention.
In the present embodiment, phase-locked loop 111, in order to receive and to produce the first clock signal CLK1 to scrambler 112, processor 113 and converter 114, carries out respective operation to make scrambler 112, processor 113 and converter 114 based on the first clock signal CLK1.
In the present embodiment, scrambler 112, in order to receive image data DT, is encoded to image data DT, and provides the image data DT-E after coding to processor 113.In one embodiment, scrambler 112 can be 8 bit to 9 bit scramblers (8b/9bencoder), in order to the image data DT of 8 bits is encoded to the image data DT-E after the coding of 9 bits.But in fact, the pattern of scrambler 112 can change according to actual demand.In different embodiments, scrambler 112 also can be 4 bit to 5 bit scramblers or 12 bit to 14 bit scramblers etc., and the present invention is not limited with above-described embodiment.
In the present embodiment, processor 113 is in order to image data DT-E, the setting data CONF after received code and the rub-out signal LK from receiving end 120.Processor 113 in order to according to the image data DT-E after data transmission system 100 predefined data formatting coding and setting data CONF, with output display data stream DS-P to converter 114.The particular content of display data stream DS-P can refer to Fig. 4, and related content describes in detail in paragraph then.
In addition, under the situation that processor 113 receives from the rub-out signal LK of receiving end 120, processor 113 can transmit clock pulse calibrating signal TAJ to each receiving end 120, upgrades its clock signal according to this to make each receiving end 120.Detail about clock pulse calibrating signal TAJ describes in detail in paragraph then.
In the present embodiment, converter 114 is in order to receive display data stream DS-P, and according to the predefined transformat of data transmission system 100, parallel display data stream DS-P is converted to the display data stream DS-S of tandem form, and provide the display data stream DS-S of tandem form to forwarder 115, carry out transfer operation according to this to make forwarder 115.In addition, in the present embodiment, converter 114 is the display data stream DS-S producing tandem form according to the first clock signal CLK1.That is in the cycle of each the first clock signal CLK1, converter 114 produces the display data stream DS-S of a tandem form.By way like this, the first clock signal CLK1 can be embedded in display data stream DS-S, to transmit.
In the present embodiment, forwarder 115 in order to receive the display data stream DS-S of tandem form, and transmits the display data stream DS-S of this tandem form to receiving end 120 through transmission channel.In one embodiment, forwarder 115 be the display data stream DS-S of the tandem form of transmission 2 bit to receiving end 120, and the frequency range of transmission channel is also 2 bits.
The setting of above, transmission end 110 can provide display data stream DS-P to receiving end 120 according to the first clock signal CLK1.
The schematic diagram of receiving end 120 of Fig. 3 B for illustrating according to one embodiment of the invention.Receiving end 120 comprises receiver 121, clock data recovery circuit 122, converter 123, debug module 124, demoder 125 and control module 126.In the present embodiment, receiver 121 is electrically connected clock data recovery circuit 122, converter 123 and control module 126.Clock data recovery circuit 122 is electrically connected converter 123, debug module 124 and demoder 125.Converter 123 is electrically connected debug module 124 and control module 126.Debug module 124 is electrically connected demoder 125.Demoder 125 is electrically connected control module 126.In the present embodiment, receiver 121, clock data recovery circuit 122, converter 123, debug module 124, demoder 125 and control module 126 all available circuit realizations.
Those skilled in the art work as can be clear, the implementation of above-mentioned receiver 121, clock data recovery circuit 122, converter 123, debug module 124, demoder 125 and control module 126 is not with being limited disclosed in above-described embodiment, and annexation is not also limited with above-described embodiment, all be enough to make receiving end 120 to realize following technology contents connected mode and implementation all can apply to the present invention.
In the present embodiment, receiver 121 in order to receive the display data stream DS-S from the tandem form of transmission end 110, and provides the display data stream DS-S of this tandem form to clock data recovery circuit 122, converter 123 and control module 126.In the present embodiment, receiver 121 can realize with comparer.The form of receiver 121 and the form of forwarder 115 correspond to each other.
In the present embodiment, clock data recovery circuit 122 is in order to receive the display data stream DS-S of tandem form, the second clock signal CLK2 is produced according to the display data stream DS-S of tandem form, and provide the second clock signal CLK2 to converter 123, debug module 124 and demoder 125, carry out respective operation to make converter 123, debug module 124 and demoder 125 based on the second clock signal CLK2.In one embodiment, the second clock signal CLK2 is roughly the same with the frequency of the first clock signal CLK1.
In a still further embodiment, clock data recovery circuit 122 receives the clock pulse calibrating signal TAJ in the display data stream DS-S of tandem form, and produce according to this or upgrade the second clock signal CLK2.Relevant operation is described in detail in paragraph then.
In addition, in one embodiment, clock data recovery circuit 122 can realize with phase-locked loop (phaselockloop, PLL) or delay-locked loop (delaylockloop, DLL).
In the present embodiment, the display data stream DS-S of tandem form, in order to receive the display data stream DS-S of the second clock signal CLK2 and tandem form, and according to the second clock signal CLK2, is converted to parallel display data stream DS-P by converter 123.In the present embodiment, the form of converter 123 and the form of converter 114 correspond to each other.
In the present embodiment, debug module 124 is in order to receive the second clock signal CLK2 and the display data stream DS-P from converter 123, and according to the content of the second clock signal CLK2 and display data stream DS-P, judge whether display data stream DS-P has mistake.Then, debug module 124, in order to provide rub-out signal LK to transmission end 110 according to judged result, transmits clock pulse calibrating signal TAJ to make the processor 113 transmission display data stream DS-P/DS-S of transmission end 110.
For example, when debug module 124 judges that display data stream DS-P has mistake, debug module 124 provides rub-out signal LK (being such as the signal of low voltage level) to transmission end 110.Now, the processor 113 of transmission end 110 transmits clock pulse calibrating signal TAJ to the clock data recovery circuit 122 in each source electrode driver 30 according to rub-out signal LK in display data stream DS-P/DS-S.This little clock data recovery circuit 122 according to clock pulse calibrating signal TAJ to upgrade the second clock signal CLK2, (it should be noted that to make the frequency of the second clock signal CLK2 and the phase place first clock signal CLK1 that again aligns, due to signal propagation delay, the phase place of the second clock signal CLK2 falls behind the first clock signal CLK1 in fact slightly).Then, transmission end 110 can retransfer same data (as same data traffic frame) or directly transmit a time data (as follows the data frame of a data frame or a secondary frame) again.
Through above-mentioned mechanism, when the second clock signal CLK2 misalignment and/or display data stream DS-S/DS-P make a mistake in transmitting, debug module 124 can notify because detecting mistake that clock pulse calibrating signal TAJ is transmitted in transmission end 110, is again alignd with phase place to make the frequency of first and second clock signal CLK1, CLK2.Then, transmission end 110 continues to transmit data.By this, display 10 can be made more stable.
In addition, in the present embodiment, demoder 125 is in order to receive the display data stream DS-P from debug module 124, and the image data DT-E after the coding in display data stream DS-P of decoding, to produce decoded image data DT.Then, demoder 125 can provide decoded image data DT to the related elements of source electrode driver 30 rear end, with make this little related elements according to image data DT produce data-signal D (1) ..., D (M).
Moreover, demoder 125 also can provide setting data CONF in display data stream DS-P to control module 126, controls accordingly (such as controlling the color depth bit (colordepthbit) of source electrode driver 30) according to setting data CONF to make control module 126.
The schematic diagram of display data stream DS-P of Fig. 4 for illustrating according to one embodiment of the invention.Display data stream DS-P comprises many frame data FM.Display 10 shows the image of each frame according to each frame data FM.
In the present embodiment, each frame data FM sequentially comprise this frame many data frame L (1), L (2) ..., L (N), CN, VB.Wherein data frame L (the 1)-L (N) of a frame data FM comprises the scan-line data (scanlinedata) of the 1-N row of this frame respectively.In each frame, display 10 is that the number of scanning lines arranged according to the 1-N of this frame makes each row pixel 106 show the image of this frame according to this respectively.
In addition, data frame CN comprises setting data CONF.Time schedule controller 20 is through data frame CN to control source electrode driver 30 (such as controlling the color depth bit of source electrode driver 30).
Moreover data frame VB comprises vertical blanking code V-BK.Data frame VB is the finishing touch data frame of a frame data FM.
In the present embodiment, data frame L (1), L (2) ... L (N), CN, VB all comprise horizontal blanking code H-BK and service data OPD.Data frame L (1), L (2) ... the service data OPD of L (N) sequentially comprises the image data DT-E after bit synchronization code (bitalignmentcode) BAC, control code CTRL, coding and end code EOL.The service data OPD of data frame CN sequentially comprises bit synchronization code BAC, control code CTRL, setting data CONF and end code EOL.The service data OPD of data frame VB sequentially comprises bit synchronization code BAC, control code CTRL and vertical blanking code V-BK.
In the present embodiment, bit synchronization code (bitalignmentcode) BAC in each data frame is the first cis-position data in service data OPD, the reference position of respective operations data OPD.Control code CTRL in each data frame is the second cis-position data adjacent to bit synchronization code BAC in service data OPD, can in order to represent the type (being such as data frame L (1)-L (N) or data frame CN) of data frame.Each end code EOL be data frame L (1), L (2) ... last cis-position data in the service data OPD of L (N), CN, corresponding data frame L (1), L (2) ... the end position of the service data OPD of L (N), CN.Image data DT-E after each coding is 1-N scan-line data in these frame data FM respectively.
In addition, during transmission end 110 is the horizontal blanking of corresponding display 10, during (horizontalblankingperiod) or vertical blanking, (verticalblankingperiod) transmits horizontal blanking code H-BK and vertical blanking code V-BK respectively to receiving end 120.
For making the technology contents of the embodiment of the present invention be easier to understand, below will arrange in pairs or groups Fig. 5-6, with an example operation, detail of the present invention is described.
It is the process flow diagram of the method for operating according to the display 10 in one embodiment of the invention with reference to Fig. 5,6, Fig. 5 simultaneously.The schematic diagram of display data stream DS-P/DS-S of Fig. 6 for illustrating according to the present invention one operational example.Method of operating comprises the following steps.
In step sl, after display 10 starts, clock pulse calibrating signal TAJ is transmitted to receiving end 120 (with reference to time point t0-t1 in Fig. 6) by display data stream DS-S/DS-P in transmission end 110.
In step s 2, when receiving end 120 receives clock pulse calibrating signal TAJ, receiving end 120 through clock data recovery circuit 122 to produce the second clock signal CLK2 according to clock pulse calibrating signal TAJ.Then, upper once upgrade the second clock signal CLK2 before, the converter 123 of receiving end 120, debug module 124 and demoder 125 all operate according to this one second clock signal CLK2.
In step s3, horizontal blanking code H-BK is transmitted to receiving end 120 (with reference to time point t1-t2 in Fig. 6) by display data stream DS-S/DS-P in transmission end 110.
In step s 4 which, when receiving end 120 receives horizontal blanking code H-BK, through debug module 124, receiving end 120 judges whether this little horizontal blanking code H-BK has mistake.More particularly, debug module 124 is that this little horizontal blanking code H-BK of comparison hides from view a yard coded format with default, whether meet with at least one judging in this little horizontal blanking code H-BK and default hide from view a yard coded format, and determine whether provide rub-out signal LK to transmission end 110 according to this.So-called " hiding from view a yard coded format " means the predefined coded format of deviser herein.Default a yard coded format is hidden from view because each horizontal blanking code H-BK under normal circumstances all should meet, therefore whether the horizontal blanking code H-BK received according to receiving end 120 meets and hide from view a yard coded format, can learn whether display data stream DS-S/DS-P and/or the second clock signal CLK2 makes a mistake.
One in this little horizontal blanking code H-BK or continuous many persons do not meet default when hiding from view yard coded format, and receiving end 120 judges to make a mistake through debug module 124, and carries out step S14.Otherwise then carry out step S5.
In step S14, receiving end 120 transmits rub-out signal LK to transmission end 110 through debug module 124, and flow process gets back to step S1.
It should be noted that, the condition (as horizontal blanking code H-BK recurs the number of times of mistake) that debug module 124 transmits rub-out signal LK can change according to actual demand, and the present invention is not limited with above-described embodiment.
In step s 5, transmission end 110 by display data stream DS-S/DS-P sequentially traffic bit synchronous code BAC and control code CTRL to receiving end 120 (with reference to time point t2-t4 in Fig. 6).
In step s 6, when receiving end 120 reception puts control code CTRL in place, through debug module 124, receiving end 120 judges whether control code CTRL is correctly received.Specifically, debug module 124 is after receiving bit synchronization code BAC (i.e. the first operation cis-position data (with reference to Fig. 4) of service data OPD), judge whether meet at least one default control code coded format adjacent to the second cis-position data of bit synchronization code BAC in service data OPD, to determine whether receiving end 120 correctly receives control code CTRL.So-called " control code coded format " pre-defines for deviser herein, can in order to represent the coded format of the type of data frame.Because control code CTRL should meet control code coded format under normal circumstances, therefore whether meet control code coded format according to the control code CTRL that receiving end 120 receives, can learn whether display data stream DS-S/DS-P and/or the second clock signal CLK2 makes a mistake.
More particularly, in this operational example, receiving end 120 is in fact judge whether meet default image frame coded format adjacent to the second cis-position data of bit synchronization code BAC, default arrange frame coded format or default hide from view a yard frame coded format in service data OPD.
When not meeting arbitrary default control code coded format adjacent to the second cis-position data of bit synchronization code BAC in service data OPD, receiving end 120 judges to make a mistake through debug module 124, and carries out step S14.Otherwise, if when control code CTRL meets default image frame coded format, then carry out step S7, if when control code CTRL meet default frame coded format is set, then carry out step S10, if again when control code CTRL meet default hide from view yard frame coded format, then carry out step S12.
In the step s 7, the control code CTRL transmitted in transmission end 110 meets default image frame coded format, namely represent transmission end 110 and just transmitting one in data traffic frame L (1)-L (N), the image data DT-E after many codings (with reference to time point t4-t5 in Fig. 6) is transmitted in transmission end 110.
In step s 8, during image data DT-E after receiving end 120 receives aforesaid coding, through debug module 124, receiving end 120 judges whether at least one in this image data DT-E a bit after coding meets default image data coded format.So-called " image data coded format " means the due coded format of image data DT-E after encoding herein.Such as, when the scrambler 112 of transmission end 110 is 8 bit to 9 bit scrambler, debug module 124 is the coded formats judging whether this little image data DT-E meets 8 bit to 9 bit scramblers and export, to determine whether transmit rub-out signal LK to transmission end 110.Due under normal circumstances each coding after image data DT-E all should meet image data coded format, therefore whether meet image data coded format according to the image data DT-E that receiving end 120 receives, can learn whether display data stream DS-S/DS-P and/or the second clock signal CLK2 makes a mistake.
One in image data DT-E after this bit coding or continuous many persons do not meet default image data coded format, receiving end 120 judges to make a mistake through debug module 124, and carries out step S14.Otherwise then carry out step S9.
It should be noted that, the condition (as the image data DT-E after coding does not meet the number of times of image data coded format continuously) that debug module 124 transmits rub-out signal LK can change according to actual demand, and the present invention is not limited with above-described embodiment.
In step s 9, transmission end 110 end-of-transmission code (EOT) EOL, to receiving end 120, represents this data frame and has transmitted end (with reference to time point t5-t6 in Fig. 6).Then, flow process gets back to step S3, and transmission end 110 starts the horizontal blanking code H-BK (such as with reference to time point t6-t7 in Fig. 6) transmitting a time data frame.
On the other hand, in step slo, the control code CTRL transmitted in transmission end 110 meets default when arranging frame coded format, and namely represent transmission end 110 and just transmitting data traffic frame CN, many setting data CONF (with reference to time point t8-t9 in Fig. 6) are transmitted in transmission end 110.
In step s 11, when receiving end 120 receives aforesaid setting data CONF, whether at least one that receiving end 120 judges in this little setting data CONF through debug module 124 meets default setting data coded format.So-called " setting data coded format " means the predefined coded format of deviser herein, is receiving the setting data with this form, and namely source electrode driver 30 controls accordingly (as adjustment color depth bit etc.).Because each setting data CONF all should meet setting data coded format under normal circumstances, therefore whether meet setting data coded format according to the setting data CONF that receiving end 120 receives, can learn whether display data stream DS-S/DS-P and/or the second clock signal CLK2 makes a mistake.
One in this little setting data CONF or continuous many persons do not meet default setting data coded format, receiving end 120 judges to make a mistake through debug module 124, and carries out step S14.Otherwise then carry out step S9.
It should be noted that, the condition (as setting data CONF does not meet the number of times of setting data coded format continuously) that debug module 124 transmits rub-out signal LK can change according to actual demand, and the present invention is not limited with above-described embodiment.
Again on the one hand, in step s 12, the control code CTRL transmitted in transmission end 110 meets default when hiding from view yard frame coded format, namely represent transmission end 110 and just transmitting one in data traffic frame L (1)-L (N), many vertical blanking code V-BK (with reference to time point t10-t11 in Fig. 6) are transmitted in transmission end 110.
In step s 13, when receiving end 120 receives aforesaid vertical blanking code V-BK, whether receiving end 120 meets through at least one that debug module 124 judges in this little vertical blanking code V-BK default is hidden from view a yard coded format.A yard coded format is hidden from view because each vertical blanking code V-BK under normal circumstances all should meet, therefore whether the vertical blanking code V-BK received according to receiving end 120 meets and hide from view a yard coded format, can learn whether display data stream DS-S/DS-P and/or the second clock signal CLK2 makes a mistake.
One in this little vertical blanking code V-BK or continuous many persons do not meet default when hiding from view yard coded format, and receiving end 120 judges to make a mistake through debug module 124, and carries out step S14.Otherwise flow process gets back to step S3, transmit a time frame data FM to make transmission end 110.
It should be noted that, the condition (as vertical blanking code V-BK does not meet the number of times hiding from view yard coded format continuously) that debug module 124 transmits rub-out signal LK can change according to actual demand, and the present invention is not limited with above-described embodiment.
Through above-mentioned operation, debug module 124 couples of display data stream DS-S/DS-P can be utilized to carry out error detection.When image data DT-E after detecting the horizontal blanking code H-BK in display data stream DS-S/DS-P, vertical blanking code V-BK, control code CTRL, coding or setting data CONF makes a mistake or does not meet default coded format, debug module 124 can notify transmission end 110, with the control making transmission end 110 carry out error exception.By this, the degree of stability of display 10 can be improved.
Although the present invention with embodiment openly as above; but it is also not used to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing various changes and amendment, therefore protection scope of the present invention is when being as the criterion depending on accompanying claims protection domain person of defining.
Claims (12)
1. be applied to a data transmission system for a display, it is characterized in that, comprising:
One transmission end, in order to produce one first clock signal, and in order to provide a display data stream according to this first clock signal; And
One receiving end, is electrically connected this transmission end, and in order to receive this display data stream, wherein this receiving end comprises:
One debug module, in order to according to one second clock signal, judge whether this display data stream that this receiving end receives has mistake, and in order to provide according to judged result a rub-out signal to this transmission end, transmit a clock pulse calibrating signal to make this transmission end through this display data stream; And
One clock data recovery circuit, is electrically connected this debug module, and this clock data recovery circuit is in order to upgrade this second clock signal according to this clock pulse calibrating signal.
2. data transmission system as claimed in claim 1, it is characterized in that, this debug module also hides from view a yard coded format in order to judge whether at least one horizontal blanking code in this display data stream or at least one vertical blanking code meet, to determine whether provide this rub-out signal to this transmission end, and this transmission end is to during a horizontal blanking of display and transmitting this horizontal blanking code and this vertical blanking code during a vertical blanking respectively.
3. data transmission system as claimed in claim 1 or 2, it is characterized in that, this display data stream comprises many data frames, at least one in those data frames comprises many service datas, those service datas comprise a bit synchronization code and a control code, this bit synchronization code is one first cis-position data in those service datas, this control code is the one second cis-position data adjacent to this bit synchronization code in those service datas, and this debug module is also in order to judge whether this receiving end correctly receives this control code, to determine whether provide this rub-out signal to this transmission end.
4. data transmission system as claimed in claim 3, it is characterized in that, this debug module also in order to judge whether these the second cis-position data adjacent to this bit synchronization code in those service datas meet at least one control code coded format, to determine whether this receiving end correctly receives this control code adjacent to this bit synchronization code in this display data stream.
5. data transmission system as claimed in claim 3, it is characterized in that, this debug module is also in order to judge whether this control code meets an image frame coded format, and in order to meet this image frame coded format in this control code, judge whether at least one image data in those service datas meets an image data coded format, to determine whether provide this rub-out signal to this transmission end.
6. data transmission system as claimed in claim 3, it is characterized in that, this debug module is also in order to judge whether this control code meets one and arrange frame coded format, and in order to meet in this control code this frame coded format is set, judge whether at least one setting data in those service datas meets a setting data coded format, to determine whether provide this rub-out signal to this transmission end.
7. be applied to a method of operating for a display, wherein this display comprises a transmission end and a receiving end, it is characterized in that, this method of operating comprises:
Through this transmission end, provide a display data stream according to one first clock signal;
Through this receiving end, receive this display data stream, judge whether this display data stream has mistake according to one second clock signal, and provide a rub-out signal according to judged result;
Through this transmission end, according to this rub-out signal, transmit a clock pulse calibration data by this display data stream; And
Through this receiving end, upgrade this second clock signal according to this clock pulse calibration data.
8. method of operating as claimed in claim 7, is characterized in that, judge whether this display data stream has mistake, and provide the step of this rub-out signal to comprise according to judged result:
Judge whether at least one horizontal blanking code in this display data stream or at least one vertical blanking code meet and hide from view a yard coded format, to determine whether provide this rub-out signal to this transmission end, wherein this transmission end is to during a horizontal blanking of display and transmitting this horizontal blanking code and this vertical blanking code during a vertical blanking respectively.
9. method of operating as claimed in claim 7 or 8, is characterized in that, provide the step of this display data stream to comprise:
This display data stream comprising many data frames is provided, at least one wherein in those data frames comprises many service datas, those service datas comprise a bit synchronization code and a control code, this bit synchronization code is one first cis-position data in those service datas, and this control code is the one second cis-position data adjacent to this bit synchronization code in those service datas;
And judge whether this display data stream has mistake, and provide the step of this rub-out signal to comprise according to judged result:
Judge whether this control code is correctly received, to determine whether provide this rub-out signal to this transmission end.
10. method of operating as claimed in claim 9, is characterized in that, judge whether this receiving end correctly receives this control code adjacent to this bit synchronization code in this display data stream, to determine whether provide this rub-out signal to comprise to the step of this transmission end:
Judge whether these the second cis-position data adjacent to this bit synchronization code in those service datas meet at least one control code coded format, to determine whether this receiving end correctly receives this control code adjacent to this bit synchronization code in this display data stream.
11. methods of operating as claimed in claim 9, is characterized in that, judge that the step whether this control code is correctly received comprises:
Judge whether this control code meets an image frame coded format;
And judge whether this display data stream has mistake, and provide the step of this rub-out signal to comprise according to judged result:
When this control code meets this image frame coded format, judge whether at least one image data in those service datas meets an image data coded format, to determine whether provide this rub-out signal to this transmission end.
12. methods of operating as claimed in claim 9, is characterized in that, judge that the step whether this control code is correctly received comprises:
Judge whether this control code meets one and arrange frame coded format;
And judge whether this display data stream has mistake, and provide the step of this rub-out signal to comprise according to judged result:
When this control code meet this frame coded format is set, judge whether at least one setting data in those service datas meets a setting data coded format, to determine whether provide this rub-out signal to this transmission end.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103112724A TWI521491B (en) | 2014-04-07 | 2014-04-07 | Data transmission system and operating method of display |
| TW103112724 | 2014-04-07 |
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| CN104064161A CN104064161A (en) | 2014-09-24 |
| CN104064161B true CN104064161B (en) | 2016-03-16 |
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| TWI642305B (en) * | 2017-05-10 | 2018-11-21 | 友達光電股份有限公司 | Display panel |
| CN108694917B (en) | 2017-06-09 | 2021-10-22 | 京东方科技集团股份有限公司 | Data transmission method, assembly and display device |
| CN111477158B (en) * | 2020-05-25 | 2024-01-09 | 京东方科技集团股份有限公司 | Data transmission method, data transmission component and display device |
| CN111599300A (en) * | 2020-06-19 | 2020-08-28 | 京东方科技集团股份有限公司 | Signal processing method, signal transmitting and receiving device, and display device |
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| JPS6158342A (en) * | 1984-08-30 | 1986-03-25 | Fujitsu Ltd | Node connection error detection system in optical data highway system |
| JP2613665B2 (en) * | 1990-07-25 | 1997-05-28 | 松下電工株式会社 | Display device |
| CN1139209C (en) * | 2000-10-13 | 2004-02-18 | 凌源通讯股份有限公司 | Synchronous pulse train correcting and error detecting device and method |
| KR100408416B1 (en) * | 2001-09-06 | 2003-12-06 | 삼성전자주식회사 | System and method for digital video signal transmission |
| JP2005301175A (en) * | 2004-04-16 | 2005-10-27 | Sanyo Electric Co Ltd | Video data transmission circuit and video data display system |
| TWI342536B (en) * | 2006-09-11 | 2011-05-21 | Au Optronics Corp | Signal regulator module and related display device |
| US8421779B2 (en) * | 2008-05-29 | 2013-04-16 | Himax Technologies Limited | Display and method thereof for signal transmission |
| CN101634964A (en) * | 2008-07-23 | 2010-01-27 | 佛山市顺德区顺达电脑厂有限公司 | Debugging information processing system and method thereof |
| TWI395191B (en) * | 2008-12-24 | 2013-05-01 | Au Optronics Corp | Lcd devices and driving methods thereof |
| KR101237702B1 (en) * | 2010-11-19 | 2013-02-27 | 주식회사 실리콘웍스 | Circuit for controlling non-signal of plat panel display device |
| CN202275399U (en) * | 2011-06-22 | 2012-06-13 | 北京航天自动控制研究所 | Debugging verification system for embedded software |
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| TWI521491B (en) | 2016-02-11 |
| CN104064161A (en) | 2014-09-24 |
| TW201539408A (en) | 2015-10-16 |
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