CN104051538B - The fin FET devices contacted with body and the method for forming the fin FET devices contacted with the body - Google Patents
The fin FET devices contacted with body and the method for forming the fin FET devices contacted with the body Download PDFInfo
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- CN104051538B CN104051538B CN201410095458.XA CN201410095458A CN104051538B CN 104051538 B CN104051538 B CN 104051538B CN 201410095458 A CN201410095458 A CN 201410095458A CN 104051538 B CN104051538 B CN 104051538B
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- 238000009413 insulation Methods 0.000 claims description 35
- 239000007943 implant Substances 0.000 claims description 28
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to the fin FET devices contacted with body and the method for forming the fin FET devices contacted with the body, fin field effect transistor device provided herein and the method for forming the fin field effect transistor device.In embodiment, fin field effect transistor device includes the Semiconductor substrate with fin.Gate electrode structure is covered in above the fin.Source electrode and drain electrode ring-type and/or elongated area and the source region and drain region of epitaxy growth are formed in the fin, and are set adjacent to the gate electrode structure.Body contact is arranged on the contact surface of the fin, and the source region and drain region of body contact and the ring-type and/or elongated area and epitaxy growth are discretely separated.
Description
Technical field
The present invention relates generally to a kind of fin field-effect transistor (fin FET) device and forms the fin effect crystal
The method of pipe is on a kind of fin FET devices contacted with body especially and forms the fin FET devices contacted with the body
Method.
Background technology
Transistor is (for example, metal oxide semiconductcor field effect transistor (MOSFET) or just simply field-effect transistor
(FET) it is) the core construction square of most of semiconductor integrated circuit (IC).FET includes source electrode and drain region, electric current
Channel can be flowed through therebetween, and the channel is influenceed by the bias for the gate electrode being applied to above the channel.Have
Semiconducter IC (for example, high performance microprocessor) can include millions of FET.For this IC, transistor size is reduced
And therefore increase transistor density, all it is the highest matter of priority of semi-conductor industry all the time.However, semiconductor performance
It must be maintained, even if transistor size reduction is as the same.
Fin field-effect transistor (fin FET) is a type of transistor, and this type, which can provide its own, to be subtracted
Few transistor size can maintain the double goal of performance of transistors again.Fin FET is a kind of three-dimensional of formation in thin fin
Transistor, the thin fin is upwardly extended from Semiconductor substrate.Performance of transistors is typically by measuring its mutual conductance
(transconductance) determine, and the mutual conductance is proportional to the width of the transistor channel., should in fin FET
Transistor channel is that the vertical sidewall and top level for forming or being formed in the fin along the vertical sidewall of the fin are put down
On face, therefore, it may achieve wide channels and high-effect, the face without substantially increasing the substrate surface required by the transistor
Product.
Fin FET is small line width technique (example due to its excellent short channel effect control and adjustment size capability
Such as, about 22 nms and lower) most potential option.In order to be conducive to the application of general purpose, it is desirable to which fin FET has
Different critical voltage (Vt) available for different circuit functions.However, fin FET of the manufacture with different critical voltage is difficult
's.Because the grade of the channel or " fin " width is 5-20 nms, therefore, this size can make it have no idea by changing
Channel doping concentration and effectively adjust Vt.In addition, channel doping can deteriorate mobility, and fin FET therefore can be influenceed to imitate
Energy.A kind of possibility mode for obtaining the fin FET with different Vt is in height-K- metai-gate fin FET techniques, to utilize
Different stack materials.However, the multi-gate storehouse processing procedure needed for fin FET of the production with different Vt is in the manufacture system
It is complicated and expensive in journey.Another mode for obtaining different Vt is by body-bias (body bias).For example, exist
In traditional surface channel nFET, negative body-bias can increase Vt, but positive body-bias can then reduce Vt.
Several methods that body is contacted and introduces fin FET structure are proposed.However, these methods be not it is too complicated,
It is unrealistic in manufacture, otherwise be that fin FET equipment energy characteristics can be by serious influence.For example, it has been suggested that use
The buik silicon (bulk silicon) of Semiconductor substrate is connected to multi-gate (poly by silicon epitaxy (silicon epitaxy)
), and fin is formed at the multi-gate and is covered in above the buik silicon of the Semiconductor substrate gate.However, this method with
Replaceability metal gates (RMG) technique is mismatched, it is therefore desirable to the multiple-grid of silicon epitaxy and the buik silicon of the Semiconductor substrate
The contact area of pole is isolated, and body contact also will physically be isolated with the fin, without directly being contacted with the fin.First
The preceding effort for fin FET formation body contacts, has been avoided because adulterating the fin with the source electrode for forming fin FET and drain electrode
Region, and the situation of body contact is formed on the fin because body contact can not both with fin FET source electrode and
Drain region direct physical contact, and operability can be maintained.
Accordingly, it is desirable to provide fin FET devices and the method for forming this fin FET devices.It also is intended to provide fin FET
Device and the method for forming fin FET devices, fin FET devices and its forming method can be avoided and formation body connects on fin
Related complexity is touched, wherein, the fin is equivalent to contact the transistor electrically communicated with the body.In addition, from next to hair
Bright detailed description and subsidiary claim, and together with reference to appended schema and this background technology of the present invention, sheet
Other desired features and characteristics of invention will be apparent.
The content of the invention
Fin field effect transistor device provided herein and the method for forming the fin field effect transistor device.In embodiment
In, fin field effect transistor device includes the Semiconductor substrate with fin.Gate electrode structure is covered in above the fin.Source
Pole and drain electrode ring-type and/or elongated area and the source region and drain region of epitaxy growth are formed in the fin or the fin
On, and set adjacent to the gate electrode structure.Body contact is arranged on the contact surface of the fin, and the body is contacted
The source region and drain region grown with the ring-type and/or elongated area and the epitaxy is discretely separated.
In another embodiment, fin field effect transistor device includes the Semiconductor substrate with fin.First insulation
Body layer is covered in above the Semiconductor substrate, and the thickness of the height with less than the fin.The fin extend through and
First insulator layer is protruded past, to provide exposed fin part.Gate electrode structure is covered in the fin portion of the exposure
Divide above, and be electrically insulated by gate insulator with the fin.Source electrode and drain electrode ring-type and/or elongated area and epitaxy
The source region of growth and drain region are formed in the fin part of the exposure or on the fin part of the exposure, and adjacent
The nearly gate electrode structure and set.Body contact is arranged on the contact surface of the fin part of the exposure.The body is contacted with being somebody's turn to do
The source region and drain region of epitaxy growth are discretely separated, and are discretely separated with the ring-type and/or elongated area again.
Body contact includes the dopant concentration for the critical voltage for biasing the field-effect transistor.Contact insulation layer is arranged on the fin of the exposure
Upper, between body contact and the ring-type and/or elongated area.Contact coating is arranged on body contact and the contact is exhausted
Above edge layer.
In another embodiment, forming the method for fin field effect transistor device has the semiconductor of fin comprising offer
Substrate.Gate electrode structure formation is covered in above the fin.Above a part for the fin and in the gate electrode structure
Side's patterning implant mask layer, to expose the fin adjacent to the source/drain part of the gate electrode structure, source electrode and drain region
Domain is formed in the source/drain part.In ion implant to the source/drain part of the exposure of the fin, to form neighbour
The source electrode of the nearly gate electrode structure and drain electrode ring-type and/or elongated area.Selectivity removes the implant mask layer, and in choosing
Selecting property is removed after the implant mask layer, forms contact insulation layer above the fin.Pattern and connect above the contact insulation layer
Patterned layer is touched, with the contact portion of the exposure contact insulation layer.The contact portion of the selective etch contact insulation layer, so that
The contact surface of the exposure fin.The body contacts to be formed on the contact surface of the fin, and body contact and the ring-type
And/or elongated area is discretely separated.Source region and drain region are above the source electrode and drain electrode ring-type and/or elongated area
Grow to epitaxy.
Brief description of the drawings
The different embodiment such as this will be described by together with ensuing schema, wherein, identical label represents identical
Component, wherein：
Fig. 1 is the portion that Semiconductor substrate includes the fin being formed within and the gate electrode structure on the fin
The perspective view divided；And
Fig. 2-Figure 12 is line A-A of Fig. 1 Semiconductor substrate along Fig. 1 cross sectional side view, to illustrate according to implementation
The sample method of fin FET device of the example to make occlusion body contact, wherein, body contact is arranged on fin, the fin
It is equivalent to contact the transistor electrically communicated with the body.
Embodiment
Ensuing detailed description is only used as example in itself, without being intended to limit the different implementation such as this
Example or its application and purposes.In addition, being not intended to by appointing appeared in previous background technology and ensuing detailed description
What theoretical constraint.
Fin field-effect transistor (fin FET) device provided herein and the method for forming fin FET devices, the fin
The critical voltage (Vt) of FET device enable transistors, the critical voltage (Vt) optionally can be subject to by biasing body contact
Amendment.Especially, fin FET devices occlusion body is contacted, and body contact is arranged on fin, and the fin is equivalent to be contacted with the body
The transistor electrically communicated, but maintain the operability of the transistor.Method described herein is even in nm-grade scale limit
, also can be by preventing the body from contacting and direct physical contact between the source electrode of the transistor and drain region under system, and enable
What the body was contacted is effectively formed.Because body contact can be effectively formed on fin, and the fin equally contacts electricity with the body
The transistor that property is communicated, also, the operability of the transistor can be maintained again, therefore, the Vt of the transistor can optionally and by
Corrected by biasing body contact.
Reference picture 1, there is provided formed with fin 12 for the exemplary embodiment of method of the foundation to form fin FET devices
In Semiconductor substrate 10 in which or on which.Although not showing, it should be appreciated that the Semiconductor substrate 10 can be according to traditional
Fin FET techniques, and include a plurality of fins 12.Limitation is not intended to, although fin FET devices described herein and side
Method is not limited to any special dimension constraint, and the fin 12 can have the width of nm grade, such as from about 5 to about
20 nms.As used herein, " this term of Semiconductor substrate " will be used for covering being conventionally used in semi-conductor industry
Semi-conducting material." semi-conducting material " is comprising single crystal silicon material (for example, usually used relatively pure or light of semi-conductor industry
The single crystal silicon material of degree doping admixture) mixed together with polycrystalline silicon material, and with other elements (for example, germanium, carbon and fellow)
Silicon.In addition, " semi-conducting material " covers other materials, for example, relatively pure and doping admixture germanium, GaAs, zinc oxide, glass
Glass and fellow.In the embodiment shown by Fig. 1, the Semiconductor substrate 10 is bulk silicon wafer, with the shape of fin 12
Into in the bulk silicon wafer.However, will be appreciated by other embodiments, although do not show in the drawings, the semiconductor
Substrate 10 can be commonly referred to as silicon-on-insulator (SOI) structure, it is then supported comprising the material set on the insulating material
Substrate is supported.For the purpose of illustration, a part 14 for the Semiconductor substrate 10 is only shown in Fig. 1.In embodiment, the fin
Portion 12 is doped with the admixture selected from P-type admixture or N-type admixture.For example, in embodiment, the Semiconductor substrate 10
The part 14 and the fin 12 are doped with P-type admixture, such as, but not limited to expectable formation N-type metal-oxide semiconductor (MOS)
(NMOS) fin FET boron, aluminium, gallium, indium, BF2 and combinations thereof,.But, although do not show, but should be appreciated that the semiconductor
The other parts of substrate also can doped n-type admixture, such as, but not limited to expectable formation P-type metal-oxide semiconductor (MOS)
(PMOS) fin FET phosphorus, arsenic, antimony, and combinations thereof.On this respect, method described herein is adapted to form NMOS
Fin FET or PMOS fin FET, depending on special micro- used material for forming indivedual fin FET.If be produced
Fin FET devices are complementary MOS integrated circuits (CMOS IC), then at least a portion and fin of the Semiconductor substrate 10
12 be that, doped with N-type admixture, and at least a portion of the Semiconductor substrate is doped with P-type admixture.For example, in the fin
In the case that portion 12 includes the admixture, the part of the Semiconductor substrate 10 can be formed in the Semiconductor substrate 10 in the fin 12
In or the Semiconductor substrate on before or after, adulterated by ion implant.Polyion implant step can be used, with up to
Into desired dopant concentration and distribution.The dopant profile can be used as the hope critical voltage for reaching made specific fin FET
A variable.
As shown in Figure 1, gate electrode structure 20 is arranged on the top of fin 12.For example, in embodiment, the
One insulator layer 16 is covered in above the Semiconductor substrate 10, and the thickness of the height with less than the fin 12, so that should
Fin 12 extends through and protrudes past first insulator layer 16, to provide exposed fin part 18.First insulation
Body layer 16 is not particularly limited, and can include oxide, for example, Si oxide.The gate electrode structure 20 is covered in
Above the fin 12, in more specific words it, on the fin part 18 of the exposure.The gate electrode structure 20 is by gate insulator
Layer 22 and be electrically insulated with the fin 12.The gate electrode structure 20 can by traditional handicraft (for example, grid first put or grid after
Put, polysilicon/SiON or high-K/ metai-gates technique) and formed in the top of the fin 12.For example, and such as Fig. 1 institutes
Display, nitride cap (nitride cap) 24 may be provided above the gate electrode structure 20, to promote the gate electrode knot
The formation of structure 20, and give the gate electrode structure 20 there is provided protection during fin FET devices are formed.The nitride
Cap 24 can be formed from any nitride (for example, silicon nitride).In embodiment, and as shown in Figure 1, according to biography
The fin FET techniques of system, the gate electrode structure 20 is on three sides of fin part 18 around the fin part of the exposure
Around 18.The profile of the part 14 along line A-A of the Semiconductor substrate 10 of Fig. 2 diagrammatic illustrations 1, its object is to illustrate
Form the sample method of fin FET devices.
In embodiment, and as shown in Figure 3, the second insulator layer 26 forms the He of fin part 18 in the exposure
The top of nitride cap 24.Second insulator layer 26 can be formed from nitride, the nitride be, for example, with for being formed
The identical nitride of the nitride cap 24, or for for forming low-K thin film (SiCON or SiCN) identical nitride.This second
The part that insulator layer 26 is arranged on the side wall of the gate electrode structure 20 to still having eventually, to be used as fin FET dresses
Described in detail by the first side wall distance piece 26 in putting, following article.In more specific words it, as shown in Figure 4, using be adapted to
Etchant (for example, nitrogen etchant) to etch second insulator layer, part on a horizontal surface is set, and this is second exhausted
Edge body layer 26 is arranged on part on the side wall of the gate electrode structure 20 then still as the first side wall distance piece 26.
Reference picture 5, in embodiment, the first mask layer 28 forms the fin portion in the gate electrode structure 20 and the exposure
Divide 18 tops, its object is to during the not shown part of the Semiconductor substrate of ion implant 30, cover semiconductor lining
Bottom 10 is shown in the fin part 18 of the exposure in the part 14 in Fig. 5.For example, in embodiment, and such as Fig. 5
Shown, the part 14 of the Semiconductor substrate 10 and can be adopted doped with expectable formation NMOS fins FET P-type admixture
With the ion implant 30 shown by Fig. 5, to form PMOS fins FET in the not shown other parts of Semiconductor substrate 10
Extension and/or annular section (not shown).However, will be appreciated by first mask layer 28 can optionally form, and this
The formation of one mask layer 28 is relevant with by the fin FET of formation type.In embodiment, first mask layer 28 is from certain
Material is formed, and this kind of material can be moved from the top of part 14 selectivity of the gate electrode structure 20 and the Semiconductor substrate 10
Remove." selectivity is removed " refers to that a kind of material more another material in special etchant has higher rate of etch.Or,
The material of first mask layer 28 can be removed in the case where structure from below removes minimum material.For example,
In embodiment, first mask layer 28 is formed from erosion resistant, for example photoresistance (photoresist).Complete from
After sub- implant 30, first mask layer is etched and selectively removes with appropriate etchant (for example, oxide etching agent)
28, and the part 14 of the gate electrode structure 20 and the Semiconductor substrate 10 is then selectively cleaned by traditional technique.
In embodiment, and as shown in Figure 6, after first mask layer and selectivity cleaning is selectively removed,
At the top of part 14 (top of fin part 18 comprising the exposure) of the Semiconductor substrate 10 and the first side wall interval
Part 26 and the top of the gate electrode structure 20 patterning implant mask layer 32, to expose the fin part 18 of the exposure adjacent to the grid
The source/drain part of pole electrode structure 20, and fin FET source electrode and drain region will be formed in the source/drain portion
In point.The implant mask layer 32 can be formed with first mask layer by identical material, so that the implant mask layer 32
It is selectively removed.Described in detail by following article, the implant mask layer 32 is normally located at the fin of the exposure
The upper of body contact will be formed in part 18, and cover the part.By this way, by isolation tightly adjacent to this
Source electrode of the Semiconductor substrate 10 formed by the part of one sidewall spacer 26 and drain region are with can effectively maintain this
Body is contacted isolates with the source electrode and drain region, forms as the same when the body is contacted on the fin part 18 of the exposure.
Ion implant 34 then can carried out tightly and implant is into the fin part 18 of the exposure adjacent to the first side wall distance piece 26,
To form source electrode and drain electrode ring-type and/or the extension of the neighbouring the first side wall distance piece 26 by traditional ion implanting processes
Region 38.For simplicity, Fig. 6 generally illustrates the ring-type formed in the Semiconductor substrate 10 and/or elongated area
38, although it is dynamic for will be appreciated by the group structure of specific ring-type and/or elongated area 38, and can be filled with special fin FET
The efficiency put is considered and changed.The implant mask layer 32 isolates the ring-type and/or elongated area 38 and the Semiconductor substrate 10
The formation of specific part, this is especially partially exposed in the pattern of the implant mask layer 32.After ion implant 34 is completed, selection
Property remove the implant mask layer 32, and selectively clean by traditional handicraft the gate electrode structure 20 and the semiconductor is served as a contrast
The part 14 at bottom 10.
In embodiment, and as shown in Figure 7, forming the ring-type and/or elongated area 38 and removing the cloth
Plant after mask layer 32, contact insulation layer 37 is formed (is included in the fin of the exposure in the top of part 14 of the Semiconductor substrate 10
The top of portion part 18) and the top of the first side wall distance piece 26, the ring-type and/or elongated area 38 and the gate electrode structure
20 tops.The contact insulation layer 37 can be formed with second insulator layer 26 by identical material.In embodiment, and
As shown in Figure 8, in the top patterned contact patterned layer 40 of contact insulation layer 37, to expose the contact insulation layer 37
Contact portion, the contact portion is covered in above contact surface 42, and body contact is then formed on the contact surface 42.With regard to this point
For, in order to maintain body contact and the ring-type and/or the interval of elongated area 38, the contact pattern layers 40 are fully covered should
The part (ring-type and/or elongated area 38 are formed in the part) of the previous exposure of exposed fin part 18, and
The fin part 18 of the exposure and the ring-type and/or elongated area 38 tightly neighbouring part are separately covered, as shown in Figure 8.
The contact pattern layers 40 can be formed with first mask layer and the implant mask layer by identical material, so that the contact
Patterned layer 40 is selectively removed.Once after patterning, the pattern in the contact pattern layers 40 can make the contact exhausted
The contact portion (it is exposed by the contact pattern layers 40) of edge layer 37 is selectively removed, so that the exposure exposure
The contact surface 42 of fin part 18, body contact will be formed on the contact surface 42.The nitride etch that can be adapted to
Agent (such as but non-limiting for CF4), by reactive ion etch (RIE), to etch the contact site of the contact insulation layer 37
Point.After the contact portion of the selective etch contact insulation layer 37, the contact pattern layers 40 are selectively removed, and pass through
Traditional handicraft selectively cleans the contact insulation layer 37.
In embodiment, and as shown in Figure 9, body contact 44 is formed in being somebody's turn to do for the fin part 18 of the exposure
Contact on surface 42.Especially, body contact 44 is by the epitaxy on the contact surface 42 of the fin part 18 of the exposure
Grow formed by semi-conducting material, and body contact 44 is only formed in the contact surface 42 of the fin part 18 of the exposure
On, without being formed on the contact insulation layer 37.Although not showing, this of the fin part 18 of the exposure will be appreciated by
Contact surface 42 can in advance be etched before body contact 44 is formed, so that by the depression of body contact 44 in the fin portion of the exposure
Divide in 18.The ring-type and/or the top of elongated area 38 and the fin part 18 of the exposure are arranged on further, since there are tightly
The contact insulation layer 37 of the upper of the neighbouring ring-type and/or elongated area 38, therefore, body contact 44 and the ring-type
And/or elongated area 38 is discretely separated in a suitable manner." discretely separating " means that body contact 44 is not in contact with the ring
Shape and/or elongated area 38, although for device operation, the body is contacted generally close to the ring-type and/or elongated area 38,
To reach low series resistance.The contact insulation layer 37 is finally still arranged on body contact 44 and the ring-type and/or elongated area 38
Between the exposure the top of fin part 18, body contact is electrically insulated with the ring-type and/or elongated area 38.For
The suitable semi-conducting material for forming body contact 44 is included above in relation to those semiconductor materials disclosed by the Semiconductor substrate 10
Material.In embodiment, body contact 44 and the part 14 of the Semiconductor substrate 10 and the fin 12 (in general terms) doped with
The admixture of same type is not N-type, be exactly P-type.For example, if the part 14 of the Semiconductor substrate 10 doped with
P-type admixture, then body contact is also doped with P-type admixture, the P-type admixture that the part 14 of the Semiconductor substrate 10 is adulterated
It can be identical or different admixture type, such as boron that adulterated P-type admixture is contacted with the body.For another example, such as
Really the part 14 of the Semiconductor substrate 10 is doped with N-type admixture, then body contact is also doped with N-type admixture, the semiconductor
It can be identical or different N- that the N-type admixture that the part 14 of substrate 10 is adulterated, which contacts adulterated N-type admixture with the body,
Type admixture, such as carbon.For example, in embodiment, body contact 44 can be formed from N-type or P-type semiconductor, partly be led depending on this
The part 14 of body substrate 10 is depending on N-type or the formation of P-type material.As a specific example, P-type body is contacted
For 44, silicide-germanide can be used.Slightly being referred to as more than, the fin FET Vt can be adjusted by body-bias
It is whole, and body-bias can be completed by setting up from body contact 44 to the high conductivity of device channel.Body contact 44
Low contact resistance can be completed by appropriate doping.On this point, the body contact with dopant concentration can be formed,
The dopant concentration sets up the contact resistance in suitable inferior grade.Higher dopant concentration would generally reduce body contact 44
Series resistance.
In embodiment, and reference picture 10-12, after body contact 44 is formed, the exposure ring-type and/or elongated area
38, with the formation of the ring-type and/or the source region and drain region of the growth of the top enable epitaxy of elongated area 38.However,
In other embodiments, although do not show, will be appreciated by the source region and drain region of epitaxy growth can form the body
Before contact 44, formed in the ring-type and/or the top of elongated area 38.It is further sayed, specific body contact is will be appreciated by
Can the growth of more specific epitaxy source region and drain region formed earlier.For example, in embodiment, PFET epitaxy
The source region and drain region of growth have just been formed before being formed in the source region and drain region that NFET epitaxy grows.
Therefore, NFET body contact has just been formed before being formed in the source region and drain region that NFET epitaxy grows.In addition,
In this embodiment, PFET body contact is just formed after being formed in the source region and drain region that PFET epitaxy grows.
In embodiment, and as shown in Figure 10, contact coating 48 forms exhausted in body contact 44 and the contact
The top of edge layer 37.The contact coating 48 is mainly formed during epitaxy grows the source region and drain region, to shield
Body contact 44.The contact coating 48 can be formed with second insulator layer 26 and the contact insulation layer 37 with identical material,
So that contact coating 48 and the contact insulation layer 37 are able to be removed with same etch agent.In embodiment, and such as Figure 11 institutes
Display, in the top of the contact coating 48 patterning cap patterned layer 50, with exposure, the contact coating 48 is covered in the ring-type
And/or the part above of elongated area 38, and the partial contact coating 48 still insulate in body contact 44 and the contact
The top of layer 37.The cap patterned layer 50 can be with first mask layer, the second implant layer and/or contact pattern layers with identical material shape
Into so that the cap patterned layer 50 is able to selectively remove from the contact coating 48.Pattern in the cap patterned layer 50 connects this
Touch the part exposed in coating 48 by the cap patterned layer 50 and be able to selective removal.Because the contact coating 48 connects with this
Touching insulating barrier 37 can be formed from the same material, and therefore, the contact insulation layer 37 below the contact coating 48 also may be selected
Property remove so that exposure the ring-type and/or elongated area 38 in will be formed the epitaxy growth source region and drain region
Surface.The contact insulation layer 37 and the contact coating 48 are covered in the part above of gate electrode structure 20 also in selection
Property etching during remove, and the contact insulation layer 37 and the contact coating 48 set on a vertical surface (for example, this first
On sidewall spacer 26) part then still leave.In selective etch, the contact coating 48 is exposed by the cap patterned layer 50
The part after, and further etching below the contact insulation layer 37 behind part, the cap patterned layer 50 be selectivity from
Contact coating 48 below this is removed, and the contact coating 48 of exposure is that selectivity is cleaned by traditional handicraft.
In embodiment, and as shown at figure 12, the source region 54 and drain region 56 of epitaxy growth are to be formed
In the ring-type and/or the top of elongated area 38.Especially, the epitaxy growth source region 54 and drain region 56 can by
(in more specific words it, on the surface 52 of the ring-type and/or elongated area 38) epitaxy growth semi-conducting material on the fin 12,
And contact 44 with the body and formed in substantially the same manner.In embodiment, the source region 54 of epitaxy growth and drain electrode
Region 56 is only formed on the surface 52 of the ring-type and/or elongated area 38, without being formed still in body contact 44
On the contact coating 48 of side.By this way, body contact 44 also grows with the epitaxy source region 54 and drain region
Domain 56 is discretely separated.Although not showing, will be appreciated by the surface 52 of the ring-type and/or elongated area 38 can form
Just it is etched before the source region 54 and drain region 56 of epitaxy growth, so that the source region 54 that the epitaxy is grown and leakage
Polar region domain 56 is recessed in the ring-type and/or elongated area 38 and the fin part 18 of the exposure.In addition, the contact coating 48
44 and the top of contact insulation layer 37 can be contacted to the body is still arranged on eventually, and the contact coating 48 contacts 44 in the body
Appropriate interval is still maintained between the source region 54 and drain region 56 that are grown with the epitaxy.For forming epitaxy growth
Source region 54 and drain region 56 suitable material include above in relation to the Semiconductor substrate 10 and for the body contact 44
Those disclosed materials.In addition, the epitaxy growth source region 54 and drain region 56 contacted with the body 44 and this partly lead
The part 14 of body substrate 10 is opposite types, is not N-type, is exactly P-type.For example, if the Semiconductor substrate 10
The part 14 doping P-type admixture is formed by P-type semi-conducting material, then the source region 54 and drain region of epitaxy growth
56 doped n-type admixtures are formed by N-type semi-conducting material.
Although at least one exemplary embodiment has been presented in the previous detailed description of the present invention, it should be appreciated that existing
Variant strong in number.Also it should be appreciated that exemplary embodiment is example, and it is not intended in any way limit this
Scope, application or the group structure of invention.It is that the previous detailed description is convenient by the skilled person for providing this area on the contrary
Policy is guided, with the exemplary embodiment of the implementation present invention.Recognize can to the function of the component described in exemplary embodiment and
Configuration is variously modified, and is not to deviate present invention scope set in subsidiary claim.
Claims (18)
1. a kind of fin field effect transistor device, comprising：
Semiconductor substrate, with fin；
Gate electrode structure, is covered in above the fin；
Source electrode and drain electrode ring-type and/or elongated area and the source region and drain region of epitaxy growth, are formed in the fin
Or on the fin, and set adjacent to the gate electrode structure；
Body is contacted, and is arranged on the contact surface of the fin, wherein, body contact and the ring-type and/or elongated area and this is of heap of stone
The source region and drain region of crystals growth are discretely separated；
Contact insulation layer, is arranged on above the fin, the body is contacted between the ring-type and/or elongated area；And
Coating is contacted, is arranged on above body contact and the contact insulation layer.
2. fin field effect transistor device as claimed in claim 1, wherein, body contact is filled comprising the field-effect transistor is biased
The dopant concentration for the critical voltage put.
3. fin field effect transistor device as claimed in claim 1, again comprising the first insulator layer, is covered in semiconductor lining
Above bottom, and the thickness of the height with less than the fin, wherein, the fin extends through and protrudes past first insulation
Body layer, to provide exposed fin part.
4. fin field effect transistor device as claimed in claim 3, wherein, the source electrode and drain electrode ring-type and/or elongated area,
The source region and drain region of epitaxy growth and body contact are formed in the fin part of the exposure or the exposure
On fin part.
5. fin field effect transistor device as claimed in claim 4, wherein, body contact includes the fin for being only formed in the exposure
The semi-conducting material of epitaxy growth on portion part.
6. fin field effect transistor device as claimed in claim 1, wherein, the fin is doped with selected from P-type admixture or N-type
The admixture of admixture.
7. fin field effect transistor device as claimed in claim 6, wherein, body contact is with the fin doped with same type
Admixture.
8. fin field effect transistor device as claimed in claim 1, wherein, body contact is undoped with and comprising selected from N-
The semi-conducting material of type or P-type semiconductor.
9. a kind of fin field effect transistor device, comprising：
Semiconductor substrate, with fin；
First insulator layer, is covered in above the Semiconductor substrate, and the thickness of the height with less than the fin, wherein,
The fin extends through and protrudes past first insulator layer, to provide exposed fin part；
Gate electrode structure, is covered in above the fin part of the exposure, and electrical with the fin by gate insulator
Insulation；
Source electrode and drain electrode ring-type and/or elongated area and the source region and drain region of epitaxy growth, are formed in the exposure
In fin part, and set adjacent to the gate electrode structure；
Body is contacted, on the contact surface for being arranged on the fin part of the exposure, wherein, the source electrode that body contact grows with the epitaxy
Region and drain region are discretely separated, and wherein, body contact mixing comprising the critical voltage for biasing the field-effect transistor
Matter concentration；
Contact insulation layer, is arranged on the fin upper of the exposure, between body contact and the ring-type and/or elongated area；
And
Coating is contacted, is arranged on above body contact and the contact insulation layer.
10. a kind of method for forming fin field effect transistor device, this method is included：
Semiconductor substrate with fin is provided；
Form the gate electrode structure being covered in above the fin；
Implant mask layer is patterned above a part of fin and above the gate electrode structure, with the exposure fin and the grid
The neighbouring source/drain part of pole electrode structure, source electrode and drain region will be formed in the source/drain part；
By in the source/drain part of the exposure of ion implant to the fin, to form the source of the neighbouring gate electrode structure
Pole and drain electrode ring-type and/or elongated area；
Selectivity removes the implant mask layer；
After selectively the implant mask layer is removed, contact insulation layer is formed above the fin；
The patterned contact patterned layer above the contact insulation layer, with the contact portion of the exposure contact insulation layer；
Contact portion of the selective etch contact insulation layer, with the contact surface of the exposure fin；
Body contact is formed on the contact surface of the fin, wherein, body contact and the ring-type and/or elongated area are discretely
Separate；And
Epitaxy source region and drain region are grown above the source electrode and drain electrode ring-type and/or elongated area.
11. method as claimed in claim 10, wherein, form body contact and connect comprising the body with dopant concentration is formed
Touch, the dopant concentration biases the critical voltage of the fin field effect transistor device.
12. method as claimed in claim 10, wherein there is provided the Semiconductor substrate comprising provide the first insulator layer to this half
Conductor substrate, first insulator layer is covered in above the Semiconductor substrate and has the thickness of the height less than the fin, its
In, the fin extends through and protrudes past first insulator layer, to provide exposed fin part, and wherein, should
Gate electrode structure is covered in above the fin part of the exposure and is electrically insulated by gate insulator with the fin.
13. method as claimed in claim 12, wherein, form the surface of body contact included in the fin part of the exposure
Upper epitaxy grows semi-conducting material.
14. method as claimed in claim 10, multiple be included in is formed after body contact, the exposure source electrode and drain electrode ring-type and/
Or the surface of elongated area.
15. method as claimed in claim 14, wherein, epitaxy grows the source region and the drain region and is included in exposure and is somebody's turn to do
Behind the surface of source electrode and drain electrode ring-type and/or elongated area, only built above the source electrode and drain electrode ring-type and/or elongated area
The crystals growth source region and the drain region.
16. method as claimed in claim 15, grows before the source electrode and the drain region included in epitaxy again, in body contact
Coating is contacted with being formed above the contact insulation layer.
17. method as claimed in claim 10, wherein, scheme above upper and the gate electrode structure of the fin
The caseization implant mask layer include with the implant mask layer be arranged on the body in the fin contact formed upper and
The part is covered, and patterns the implant mask layer.
18. method as claimed in claim 10, wherein, pattern the contact pattern layers and include the patterning contact pattern layers,
To cover the part of the fin, wherein, the ring-type and/or elongated area are formed in the part, and also cover the fin
The neighbouring ring-type and/or the part of elongated area.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361799049P | 2013-03-15 | 2013-03-15 | |
| US61/799,049 | 2013-03-15 | ||
| US14/176,767 | 2014-02-10 | ||
| US14/176,767 US9142674B2 (en) | 2013-03-15 | 2014-02-10 | FINFET devices having a body contact and methods of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104051538A CN104051538A (en) | 2014-09-17 |
| CN104051538B true CN104051538B (en) | 2017-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410095458.XA Expired - Fee Related CN104051538B (en) | 2013-03-15 | 2014-03-14 | The fin FET devices contacted with body and the method for forming the fin FET devices contacted with the body |
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| CN (1) | CN104051538B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227202A (en) * | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | FinFET body contact and method of making same |
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- 2014-03-14 CN CN201410095458.XA patent/CN104051538B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227202A (en) * | 2012-01-31 | 2013-07-31 | 台湾积体电路制造股份有限公司 | FinFET body contact and method of making same |
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