CN104051214A - Using Modeling to Determine Ion Energy Associated with A Plasma System - Google Patents

Using Modeling to Determine Ion Energy Associated with A Plasma System Download PDF

Info

Publication number
CN104051214A
CN104051214A CN201410097194.1A CN201410097194A CN104051214A CN 104051214 A CN104051214 A CN 104051214A CN 201410097194 A CN201410097194 A CN 201410097194A CN 104051214 A CN104051214 A CN 104051214A
Authority
CN
China
Prior art keywords
voltage
electric current
model
impedance matching
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410097194.1A
Other languages
Chinese (zh)
Other versions
CN104051214B (en
Inventor
约翰·C·小瓦尔考
布拉德福德·J·林达克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/184,639 external-priority patent/US9842725B2/en
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to CN201810106696.4A priority Critical patent/CN108447759B/en
Publication of CN104051214A publication Critical patent/CN104051214A/en
Application granted granted Critical
Publication of CN104051214B publication Critical patent/CN104051214B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32174—Circuits specially adapted for controlling the RF discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber

Abstract

Systems and methods for determining ion energy are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model and determining an ion energy from the wafer bias value.

Description

Use a model and determine the ion energy associated with plasma system
Technical field
Definite ion energy associated with plasma system the present invention relates to use a model.
Background technology
In the system based on plasma, at the indoor generation plasma of plasma to carry out various operations on wafer, for example, etching, clean, deposition etc.Plasma is monitored and is controlled, thereby controls the execution of various operations.For example, by measuring the indoor electrostatic chuck biasing of plasma with bias compensation equipment and measuring radio frequency (RF) voltage by the voltage probe of the output with impedance matching circuit, thus monitoring of plasma.The amount that offers the radio-frequency power of plasma chamber by control is controlled plasma.
Yet, with bias compensation equipment and voltage probe, monitor with the performance of control operation and possibly cannot provide gratifying result.In addition, the monitoring of wafer bias and RF voltage may be expensive and time-consuming operation.
Under this background, the execution mode described in the disclosure has been proposed.
Summary of the invention
Embodiment of the present disclosure provides device, the method and computer program of determining the ion energy associated with plasma system for using a model.Should be appreciated that embodiments of the present invention can realize in many ways, for example, with the method on technique, device, system, hardware or computer-readable medium, realize.Some execution modes are described below.
In some embodiments, described for determining the method for ion energy.The method comprises: be identified in the first complex voltage and electric current when described RF generator is coupled to plasma chamber via impedance matching circuit that the outgoing position of radio frequency (RF) generator records.The output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to RF transmission line.Described method also further comprises that described impedance matching model has input and output based on defined electric component generation impedance matching model in described impedance matching circuit.The described input of described impedance matching model receives described the first complex voltage and electric current, and described impedance matching model has one or more elements.Described method also comprises and transmits described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current.Described method also comprises acquisition crest voltage; Based on described the second complex voltage and electric current, determine wafer bias; And determine described ion energy based on described wafer bias and described crest voltage.
In various execution modes, described for determining the plasma system of ion energy.This plasma based turnkey is drawn together: for generation of the RF generator of radio frequency (RF) signal.Described RF generator is associated with voltage and current probe.Described voltage and current probe is configured to measure the first complex voltage and the electric current at the outgoing position of described RF generator.Described plasma system also comprises the impedance matching circuit that is coupled to described RF generator and the plasma chamber that is coupled to described impedance matching circuit via RF transmission line.The output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to described RF transmission line.Described plasma system comprises the processor that is coupled to described RF generator.Described processor is configured to: identify described the first complex voltage and electric current and generate impedance matching model based on defined electric component in described impedance matching circuit.Described impedance matching model has input and output, and the described input of described impedance matching model receives described the first complex voltage and electric current.Described impedance matching model has one or more elements.Described processor is further configured to and transmits described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current; Obtain crest voltage; Based on described the second complex voltage and electric current, determine wafer bias; And determine described ion energy based on described wafer bias and described crest voltage.
Described a kind of for determining the computer system of ion energy.This computer system comprises: processor, the first complex voltage and electric current when described RF generator is coupled to plasma chamber via impedance matching circuit that its outgoing position that is configured to be identified in radio frequency (RF) generator records.The output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to RF transmission line.Described processor is also configured to generate impedance matching model based on defined electric component in described impedance matching circuit.Described impedance matching model has input and output.The described input of described impedance matching model receives described the first complex voltage and electric current.Described impedance matching model has one or more elements.Described processor is also configured to transmit described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current; Obtain crest voltage; Based on described the second complex voltage and electric current, determine wafer bias; And determine described ion energy based on described wafer bias and described crest voltage.Described computer system also comprises the memory device that is coupled to described processor, and described memory device is configured to store described ion energy.
Some advantages of above-mentioned execution mode comprise: determine ion energy and do not need voltage probe to be coupled to the output of impedance matching circuit, and not needing to measure wafer bias with bias compensation equipment.Obtaining voltage probe and bias compensation circuit can be high cost.Comparatively speaking, in the situation that do not need voltage probe is coupled to the output of impedance matching circuit and does not need to use bias compensation circuit to determine ion energy.Do not use cost and time and energy that voltage probe is relevant to voltage probe and bias compensation circuit with the saving of bias compensation circuit energy.
In addition, voltage probe and bias compensation circuit may break down or possibly cannot operate in the processes such as the manufacture of substrate, processing, cleaning.Voltage and current probe meets default formula and than voltage probe more reliably and more accurate, voltage and current probe is combined with precircuit to determine radio frequency (RF) voltage, and determines wafer bias with this RF voltage.Based on this wafer bias and this RF voltage, determine ion energy.Use the measured RF voltage of voltage and current probe and wafer bias to setover than the determined electrostatic chuck of voltage based on being recorded by voltage probe, to ion energy, provide better precision.
According to ensuing detailed description, by reference to the accompanying drawings, other side can become apparent.
Accompanying drawing explanation
By reference to ensuing description, by reference to the accompanying drawings, these execution modes can be understood best.
Fig. 1 be according to the execution mode described in the disclosure for determine the outgoing position of impedance matching model, the outgoing position of the part of radio frequency (RF) mode and at the block diagram of the system of the variable of the outgoing position of electrostatic chuck (ESC) model.
Fig. 2 be according to the execution mode described in the disclosure for determining at the complex voltage of outgoing position of RF mode part and the flow chart of the method for electric current.
Fig. 3 A is that it is for diagram impedance matching circuit according to the block diagram of the system of the execution mode described in the disclosure.
Fig. 3 B is according to the circuit diagram of the impedance matching model of the execution mode described in the disclosure.
Fig. 4 is that it is for diagram RF transmission line according to the figure of the system of the execution mode described in the disclosure.
Fig. 5 A is that it is for the circuit model of diagram RF transmission line according to the block diagram of the system of the execution mode described in the disclosure.
Fig. 5 B is according to figure, its tunnel for diagram RF mode and band (strap) model of the circuit of the execution mode described in the disclosure.
Fig. 5 C is that it is for diagram tunnel and band (strap) model according to the figure of the circuit of the execution mode described in the disclosure.
Fig. 6 is that it is for diagram cylinder and ESC model according to the figure of the circuit of the execution mode described in the disclosure.
Fig. 7 is the block diagram of plasma system that is used for determining variable that comprises filter according to the execution mode described in the disclosure.
Fig. 8 A is according to the figure of the system of the execution mode described in the disclosure, and it improves the model of filter of the precision of variable for diagram.
Fig. 8 B is that it is for the model of diagram filter according to the figure of the system of the execution mode described in the disclosure.
Fig. 9 be according to the execution mode described in the disclosure for utilizing voltage and current probe to measure the block diagram in the system of the variable of the outgoing position of the RF generator of the system of Fig. 1.
Figure 10 is that wherein voltage and current probe and communication equipment are positioned at the outside of RF generator according to the block diagram of the system of the execution mode described in the disclosure.
Figure 11 is according to the block diagram of the system of the execution mode described in the disclosure, has wherein used the value of utilizing the definite variable of the system of Fig. 1.
Figure 12 A be according to the diagram of the execution mode described in the disclosure when x MHz RF generator is opened (on) by using the figure of the correlation between the definite variable of the variable that probe records at the intrasystem node location of Fig. 1 and the method for utilizing Fig. 2.
Figure 12 B works as according to the diagram of the execution mode described in the disclosure ywhen MHz RF generator is opened by using the figure of the correlation between the definite variable of the variable that probe records at the intrasystem node location of Fig. 1 and the method for utilizing Fig. 2.
Figure 12 C be according to the diagram of the execution mode described in the disclosure when z MHz RF generator is opened by using the figure of the correlation between the definite variable of the variable that probe records at the intrasystem node location of Fig. 1 and the method for utilizing Fig. 2.
Figure 13 be according to the execution mode described in the disclosure for determining the flow chart of method of wafer bias of the model node location of impedance matching model, RF mode or ESC model.
Figure 14 is for generating the state diagram of the wafer bias generator of wafer bias according to the diagram of the execution mode described in the disclosure.
Figure 15 be according to the execution mode described in the disclosure for determining along the flow chart of the method for the wafer bias at certain some place in the path between impedance matching model and ESC model.
Figure 16 be according to the execution mode described in the disclosure for determining the block diagram in the system of the wafer bias of the node location of model.
Figure 17 be according to the execution mode described in the disclosure for determining the flow chart in the method for the wafer bias of the model node location of the system of Fig. 1.
Figure 18 is for diagram, not to be by with voltage probe but by determine the block diagram of system of the advantage of wafer bias by the method for Figure 13, Figure 15 or Figure 17 according to the execution mode described in the disclosure.
Figure 19 A be according to the diagram of the execution mode described in the disclosure when y and zMHz RF generator are opened by using the variable that voltage probe records at the node location of the plasma system of Fig. 1 and utilizing the execution mode of the figure of the correlation between the variable of corresponding model node output that Fig. 2,13,15 or 17 method determine.
Figure 19 B be according to the diagram of the execution mode described in the disclosure when x and zMHz RF generator are opened by using the variable that voltage probe records at the node location of the plasma system of Fig. 1 and utilizing the execution mode of the figure of the correlation between the variable of corresponding model node output that Fig. 2,13,15 or 17 method determine.
Figure 19 C be according to the diagram of the execution mode described in the disclosure when x and yMHz RF generator are opened by using the variable that voltage probe records at the node location of the plasma system of Fig. 1 and utilizing the execution mode of the figure of the correlation between the variable of corresponding model node output that Fig. 2,13,15 or 17 method determine.
Figure 20 A be according to the execution mode described in the disclosure for diagram when x MHz RF generator is opened, at the wired wafer bias that utilizes sensor tool to record (wired wafer bias), utilize the definite model wafer bias of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 B be according to the execution mode described in the disclosure for diagram when y MHz RF generator is opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 C be according to the execution mode described in the disclosure for diagram when z MHz RF generator is opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 D be according to the execution mode described in the disclosure for diagram when x and y MHz RF generator are opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 E be according to the execution mode described in the disclosure for diagram when x and z MHz RF generator are opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 F be according to the execution mode described in the disclosure for diagram when y and z MHz RF generator are opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 20 G be according to the execution mode described in the disclosure for diagram when x, y and z MHz RF generator are opened, at the wired wafer bias that utilizes sensor tool to record, utilize the definite model biasing of Figure 13,15 or 17 method and the figure of the correlation between the error in the biasing of this model.
Figure 21 is according to the block diagram of the host computer system of the system of Fig. 1 of the execution mode described in the disclosure.
Figure 22 determines the figure of the function of ion energy from wafer bias and peak amplitude for diagram.
Embodiment
Following execution mode has been described the system and method for determining the ion energy associated with plasma system for using a model.Obviously, these execution modes can be in the situation that do not have some or all in these details to implement.On the other hand, known technological operation is not described in detail in order to avoid unnecessarily makes these execution mode indigestions.
Fig. 1 be for determine the outgoing position of impedance matching model 104, in the output of the part 173 of RF mode 161 (for example, model node N1m) position and in the output of electrostatic chuck (ESC) model 125 (for example, model node N6m) block diagram of the execution mode of the system 126 of the variable of position, RF mode 161 is models of RF transmission line 113.The example of variable comprises complex voltage, telegram in reply stream, complex voltage and electric current, complex power, ion energy, wafer bias etc.RF transmission line 113 has output, for example node N2.Complex voltage and electric current V that voltage and current (VI) probe 110 is for example measured, in output (, the node N3) position of x MHz RF generator xMHz, I xMHzwith for example, the first complex voltage and electric current.It should be noted that V xMHzrepresentative voltage amplitude, I xMHzrepresent current amplitude, and represent V xMHzand I xMHzbetween phase place.Impedance matching model 104 has output, for example, and model node N4m.
In addition, voltage and current probe 111 is measured ycomplex voltage and the electric current V of the outgoing position of MHz RF generator (for example, node N5) yMHz, I yMHzwith it should be noted that V yMHzrepresentative voltage amplitude, I yMHzrepresent current amplitude, and represent V yMHzand I yMHzbetween phase place.
In some embodiments, node is that the input point of equipment is, the point in the output point of equipment or equipment.Equipment as used herein is described below.
In various execution modes, voltage magnitude comprises zero-peak amplitude or peak-peak amplitude or root mean square (RMS) amplitude, and it belongs to one or more radio frequency values of RF signal.In some embodiments, current amplitude comprises zero-peak amplitude or peak-peak amplitude or RMS amplitude, and it belongs to one or more radio frequency values of RF signal.In some embodiments, power magnitude is the long-pending of phase place between voltage magnitude, current amplitude, this current amplitude and this voltage magnitude.
The example of x MHz comprises 2MHz, 27MHz and 60MHz.The example of y MHz comprises 2MHz, 27MHz and 60MHz.X MHz is different from y MHz.For example, when x MHz is 2MHz, y MHz is 27MHz or 60MHz.When x MHz is 27MHz, y MHz is 60MHz.
Each VI probe 110 and 111 example comprise the VI probe that meets default formula.The example of default formula comprises the standard of being followed for the association of the standard of transducer by exploitation.Another example of default formula comprises USA National Institute of Standard and Technology (NIST) standard.Shown in voltage and current probe 110 or 111 according to NIST standard, calibrate.In this diagram, thereby voltage and current probe 110 or 111 is coupled and meets NIST standard with calibration voltage and current probe 110 or 111 with open circuit, short circuit or known load.First voltage and current probe 110 or 111 can be coupled with open circuit, follows and short circuit coupling, thereby is then coupled based on NIST standard calibration voltage and current probe 110 with known load.Thereby voltage and current probe 110 or 111 can be coupled to known load, open circuit and short circuit in any order according to NIST standard calibration voltage and current probe 110 or 111.The example of known load comprises the load of 50 ohm, the load of 100 ohm, load, static load, direct current (DC) load, the resistor of 200 ohm, etc.Shown each voltage and current probe 110 and 111 can the standard of reviewing be calibrated according to NIST-.
Voltage and current probe 110 is coupled to the output of x MHz RF generator, for example node N3.The output of x MHz RF generator, node N3 for example, the input 153 of being coupled to impedance matching circuit 114 via cable 150.In addition, voltage and current probe 111 is coupled to the output of yMHz RF generator, for example node N5.Another input 155 of impedance matching circuit 114 is coupled in the output of y MHz RF generator (for example node N5) via cable 152.
The input that RF transmission line 113 is coupled in the output of impedance matching circuit 114 (for example node N4).RF transmission line 113 comprises part 169 and another part 195.The input of part 169 is inputs of RF transmission line 113.The input that part 195 is coupled in the output of part 169 (for example node N1).Plasma chamber 175 is coupled in the output of part 195 (for example node N2).The output of part 195 is the output of RF transmission line 113.The example of part 169 comprises RF cylinder and RF band (strap).RF cylinder is coupled to RF band.The example of part 195 comprises RF bar and/or for supporting the strutting piece of plasma chamber 175, such as cylinder etc.
Plasma chamber 175 comprises electrostatic chuck (ESC) 177, top electrode 179 and other parts (not shown), other parts for example around the upper dielectric collar of top electrode 179, around the top electrode extension of dielectric collar on this, around the lower dielectric collar of the bottom electrode of ESC177, around the bottom electrode extension of this lower dielectric collar, upper plasma forbidden zone (PEZ) ring, lower PEZ ring, etc.Top electrode 179 is positioned at the opposite of ESC177 and towards ESC177.Workpiece 131, such as semiconductor wafer etc., is supported on the upper surface 183 of ESC177.Upper surface 183 comprises the output N6 of ESC177.Workpiece 131 is placed on output N6.In process of production, on workpiece 131, carry out various technique, such as chemical vapour deposition (CVD), clean, deposition, sputter, etching, Implantation, resist, peel off etc.On workpiece 131, develop integrated circuit, such as application-specific integrated circuit (ASIC) (ASIC), programmable logic device (PLD) etc., and described integrated circuit is used in various electronic products, for example cell phone, tablet computer, smart phone, computer, notebook computer, the network equipment, etc.Each in bottom electrode and top electrode 179 is made by metal (such as aluminium, aluminium alloy, copper etc.).
In one embodiment, top electrode 179 comprises the hole of being coupled to central gas feed arrangement (not shown).Central authorities' gas feed arrangement receives one or more process gas from gas supply source (not shown).The example of process gas comprises oxygen-containing gas, such as O 2.Other example of process gas comprises fluoro-gas, for example tetrafluoromethane (CF 4), sulphur hexafluoride (SF 6), perfluoroethane (C 2f 6) etc.Top electrode 179 ground connection.ESC177 is coupled to x MHz RF generator and y MHz RF generator via impedance matching circuit 114.
When process gas is supplied between top electrode 179 and ESC177 and when x MHz RF generator and/or y MHz RF generator provide RF signal to ESC177 via impedance matching circuit 114 and RF transmission line 113, described process gas is lighted with at the interior generation plasma of plasma chamber 175.
When x MHz RF generator produces RF signal and via node N3, impedance matching circuit 114 and RF transmission line 113, RF signal offered to ESC177 and when y MHz generator generation RF signal and while RF signal being offered to ESC177 via node N5, impedance matching circuit 114 and RF transmission line 113, the complex voltage at voltage and current probe 110 measured node N3 places and electric current and complex voltage and the electric current at voltage and current probe 111 measured node N5 places.
The complex voltage being recorded by voltage and current probe 110 and 111 and electric current are provided for the storage hardware unit (HU) for storing of host computer system 130 from corresponding voltage and current probe 110 and 111 via corresponding communication equipment 185 and 189.For example, the complex voltage being recorded by voltage and current probe 110 and electric current offer host computer system 130 via communication equipment 185 and cable 191 and the complex voltage and the electric current that by voltage and current probe 111, are recorded offer host computer system 130 via communication equipment 189 and cable 193.The example of communication equipment comprises ethernet device, the equipment of Ethernet auto-control technology (EtherCAT), the parallel interface equipment of the serial interface devices of serially-transmitted data, parallel transmission data, USB (USB) interface equipment that data transaction is become to Ethernet data bag and Ethernet data bag is converted to data, etc.
The example of host computer system 130 comprises computer, for example desktop computer, notebook computer, tablet computer, etc.Shown host computer system 130 comprises processor and storage HU162.Processor as used herein can be CPU (CPU), microprocessor, application-specific integrated circuit (ASIC) (ASIC), programmable logic device (PLD) etc.The example of storage HU comprises read-only memory (ROM), random access storage device (RAM) or their combination.Storage HU can be flash memory, memory disk redundant array (RAID), hard disk, etc.
Impedance matching model 104 is stored in storage HU162.Impedance matching model 104 has the feature with the feature similarity of impedance matching circuit 114, for example, and electric capacity, inductance, complex power, complex voltage and electric current, etc.For example, impedance matching model 104 has capacitor and/or the inductor identical with capacitor in impedance matching circuit 114 and/or inductor quantity, and this capacitor and/or inductor are connected to each other in the identical mode of the mode with impedance matching circuit 114 (such as series, parallel etc.).For instance, when impedance matching circuit 114 comprises the capacitor with inductor series coupled, impedance matching model 104 also comprises the capacitor with inductor series coupled.
As an example, impedance matching circuit 114 comprises one or more electric component and impedance matching model 104 comprises the design of impedance matching circuit 114, the model that for example computer generates.The model that computer generates can be generated by the input signal based on receiving from user by input hardware unit by processor.Described input signal comprises with which electric component (such as capacitor, inductor etc.) is included relevant signal with electric component model coupled to each other and mode (such as series, parallel etc.).As another example, impedance matching circuit 114 comprises that hardware between hardware electric component and described electric component connects and impedance matching model 104 comprises that the software that software is expressed and hardware connects of hardware electric component expresses.As another example, impedance matching model 104 utilizes software program to design and impedance matching circuit 114 is made on printed circuit board (PCB).Electric component as used herein can comprise resistor, capacitor, inductor, the connector between resistor, the connector between inductor, the connector between capacitor, and/or the connector between the combination of resistor, inductor and capacitor.
Similarly, cable model 163 has similar feature to cable 150, and cable model 165 has similar feature to cable 152.As an example, the inductance of cable model 163 is identical with the inductance of cable 150.As another example, cable model 163 is the model that generates of the computer of cable 150 and model that computer that cable model 165 is cables 152 generates.
Similarly, RF mode 161 has similar feature to RF transmission line 113.For example, RF mode 161 has resistor, capacitor and/or the inductor identical with resistor, capacitor and/or inductor quantity in RF transmission line 113, and described resistor, capacitor and/or inductor are connected to each other in the identical mode of the mode with RF transmission line 113 (such as series, parallel etc.).In order to further illustrate, when RF transmission line 113 comprises the capacitor with inductor parallel coupled, RF mode 161 also comprises the capacitor with inductor parallel coupled.Again for example, RF transmission line 113 comprises one or more electric components and RF mode 161 comprises the design of RF transmission line 113, the model that for example computer generates.
In some embodiments, RF mode 161 relates to the impedance transformation that computer computing and that relate to the connection determined between these elements (such as series, parallel etc.) of the feature (for example, electric capacity, resistance, inductance, their combination etc.) of element (such as capacitor, inductor, resistor, their combination etc.) generates.
Complex voltage based on receiving from voltage and current probe 110 via cable 191 and the features such as electric capacity, inductance of electric current and the elements such as inductor, capacitor in impedance matching model 104, the processor of host computer system 130 for example calculate, at the complex voltage of output (the model node N4m) position of impedance matching model 104 and electric current V, I and , for example the second complex voltage and electric current.In the storage HU162 that is stored in host computer system 130 at complex voltage and the electric current at model node N4m place and/or another storage HU, in CD, flash memory etc.Multiple V, I and comprise the phase place between voltage magnitude V, current amplitude I and this voltage and current
The output of impedance matching model 104 is coupled to the input of RF mode 161, and RF mode 161 is stored in storage hardware unit 162.Impedance matching model 104 also has input, node N3m for example, and it is used to be received in complex voltage and the electric current that node N3 place records.
RF mode 161 comprises part 173, another part 197 and output N2m, and output N2m is coupled with model node N6m by ESC model 125.ESC model 125 is models of ESC177.For example, ESC model 125 has the feature with the feature similarity of ESC177.For example, ESC model 125 has inductance, electric capacity, resistance or their combination identical with inductance, electric capacity, resistance or their combination of ESC177.
The input of part 173 is inputs of RF mode 161.The input of part 197 is coupled in the output of part 173.Part 172 has the feature with the feature similarity of part 169, and part 197 has the feature with the feature similarity of part 195.
Complex voltage and electric current based on recording at model node N4m place, the processor of host computer system 130 for example calculate, at the complex voltage of output (, the model node N1m) position of the part 173 of RF mode 161 and electric current V, I and the 3rd complex voltage and electric current for example.At the definite complex voltage in model node N1m place and electric current, be stored in storage HU162 and/or such as CD, flash memory etc. of another storage HU(of host computer system 130) in.
In some execution modes, replace determining the 3rd complex voltage and electric current or be additional to and determine the 3rd complex voltage and electric current, the complex voltage of the outgoing position of the processor of host computer system 130 based at impedance matching model 104 and electric current and complex voltage and electric current that in the input of RF mode 161 and the feature calculation of the element between the point in part 173, the point in part 173 (such as node etc.) is located, for example in the middle of complex voltage and electric current V, I and
In various execution modes, replace determining the 3rd complex voltage and electric current or be additional to and determine the 3rd complex voltage and electric current, the complex voltage of the outgoing position of the processor of host computer system 130 based at impedance matching model 104 and electric current and complex voltage and electric current that in the input of RF mode 161 and the feature calculation of the element between the point in part 197, the point in part 197 (such as node etc.) is located, for example in the middle of complex voltage and electric current V, I and
It should be noted that, in some embodiments, the feature of element of the complex voltage of the outgoing position based at x MHz RF generator and electric current, cable model 163 and the feature calculation of impedance matching model 104 are at complex voltage and the electric current of the outgoing position of impedance matching model 104.
Although shall also be noted that showing two generators is coupled to impedance matching circuit 114, in one embodiment, the RF generator of any amount (for example, single generator, three generators etc.) is coupled to plasma chamber 175 via impedance matching circuit.For example, 2MHz generator, 27MHz generator and 60MHz generator can be coupled to plasma chamber 175 via impedance matching circuit.For example, although the contact of above-mentioned execution mode is used the complex voltage and the electric current that record at node N3 place to be described, in various execution modes, above-mentioned execution mode also can be used complex voltage and the electric current recording at node N5 place.
Fig. 2 is for determining Fig. 1 at RF mode part 173() the complex voltage of outgoing position and the flow chart of the execution mode of the method for electric current 102.Method 102 is by host computer system 130(Fig. 1) processor carry out.In operation 106, from storage HU162(Fig. 1) in be identified in complex voltage and the electric current that node N3 records, for example the first complex voltage and electric current.For instance, from voltage and current probe 110(Fig. 1) receive the first complex voltage and electric current is determined.As another example, based on voltage and current probe 110, be stored in storage HU162(Fig. 1) in homogeneity (identity), the first complex voltage and electric current are associated and determine with described homogeneity.
Further, in operation 107, based on impedance matching circuit 114(Fig. 1) electric component generate impedance matching model 104(Fig. 1).For example, the feature of the connection between the electric component of impedance matching circuit 114 and described electric component is via being offered the processor of host computer system 130 by user with the input hardware unit of host computer system 130 couplings.Receiving on the basis of described connection and described feature, processor generate have the feature identical with the feature of the electric component of impedance matching circuit 114 element and have with described electric component between the described element that is connected identical connection between generate and connect.
The input of impedance matching model 163, for example node N3m, receives the first complex voltage and electric current.For example, the processor of host computer system 130 from storage HU162 access (such as reading etc.) the first complex voltage and electric current input that the first complex voltage and electric current are offered to impedance matching model 104 to process the first complex voltage and electric current.
In operation 116, input (for example node N3m(Fig. 1) by the first complex voltage and electric current from impedance matching model 104) transmit by impedance matching model 104(Fig. 1) the output (for example node N4m(Fig. 1) of one or more elements arrival impedance matching models 104) to determine the second complex voltage and electric current, the second complex voltage and electric current are positioned at the outgoing position of impedance matching model 104.For instance, with reference to figure 3B, when 2MHz RF generator be open (such as operation, that connect, be coupled to equipment such as the impedance matching circuit 104 such as plasma system 126 etc.) time, the electric capacity based on capacitor 253, the electric capacity based on capacitor C5 and the first complex voltage based on receiving in input 255 places and electric current are determined the intermediate node for example at node 251() complex voltage located and electric current Vx1, Ix1 and for example, in the middle of complex voltage and electric current, it comprises the phase place between voltage magnitude Vx1, current amplitude Ix1 and this complex voltage and electric current in addition, based on complex voltage and electric current Vx1, Ix1 and and the inductance based on inductor L3 is determined at the complex voltage at node 257 places and electric current Vx2, Ix2 and complex voltage and electric current Vx2, Ix2 and comprise the phase place between voltage magnitude Vx2, current amplitude Ix2 and this voltage and current when 27MHz RF generator and 60MHz RF generator be close (such as in non-operating state, power-off, with impedance matching circuit 104 decoupling zeros etc.) time, complex voltage and electric current V2, I2 and be determined to be in the second complex voltage and the electric current at output 259 places, output 259 is impedance matching model 104(Fig. 1) output (for example model node N4m(Fig. 1)) example.Complex voltage and electric current V2, I2 and based on complex voltage and electric current Vx2, Ix2 and and the inductance based on inductor L2 is determined.Complex voltage and electric current V2, I2 and comprise the phase place between voltage magnitude V2, current amplitude I2 and this voltage and current
Similarly, when 27MHz RF generator be open and 2MHz and 60MHz RF generator be close time, at the output complex voltage at 259 places and electric current V27, I27 and complex voltage based on receiving in node 261 places and the feature of electric current and inductor LPF2, capacitor C3, capacitor C4 and inductor L2 are determined.Complex voltage and electric current V27, I27 and comprise the phase place between voltage magnitude V27, current amplitude I27 and this voltage and current the complex voltage receiving in node 261 places and electric current with at node N5(Fig. 1) complex voltage and the electric current locating to record be identical.When 2MHz and 27MHz RF generator the two be all open and 60MHz RF generator be close time, complex voltage and electric current V2, I2, v27, I27 and it is the example of the second complex voltage and electric current.In addition, similarly, when 60MHz RF generator be open and 2MHz and 27MHz RF generator be close time, at the output complex voltage at 259 places and electric current V60, I60 and complex voltage based on receiving in node 265 places and the feature of electric current and inductor LPF1, capacitor C1, capacitor C2, inductor L4, capacitor 269 and inductor L1 are determined.Complex voltage and electric current V60, I60 and comprise the phase place between voltage magnitude V60, current amplitude I60 and this voltage and current when 2MHz, 27MHz and 60MHz RF generator are all while opening, complex voltage and electric current V2, I2, v27, I27, v60, I60 and it is the example of the second complex voltage and electric current.
In operation 117, based on RF transmission line 113(Fig. 1) electric component generate RF mode 161(Fig. 1).For example, the feature of the connection between the electric component of RF transmission line 113 and described electric component is via being offered the processor of host computer system 130 by user with the input equipment of host computer system 130 couplings.Receiving on the basis of described connection and described feature, processor generate have the feature identical with the feature of the electric component of RF transmission line 113 element and between described element, generate with described electric component between be connected identical connection.
In operation 119, the second complex voltage and electric current are transmitted to the output (for example model node N1m(Fig. 1) that arrives RF mode part 173 by one or more element of RF mode part 173 from the input of RF mode 113) to determine the 3rd complex voltage and the electric current at the outgoing position of RF mode part 173.For instance, with reference to figure 5B, when 2MHz RF generator be open and 27 and 60MHz RF generator be close time, the complex voltage of the inductance based on inductor Ltunnel, the electric capacity based on capacitor Ctunnel and the example based on as the second complex voltage and electric current and electric current V2, I2 and (Fig. 3 B) determines the intermediate node for example at node 293() complex voltage located and electric current Vx4, Ix4 and for example, in the middle of complex voltage and electric current.It should be noted that Ltunnel be RF tunnel computer-generated model inductance and Ctunnel is the electric capacity of RF tunnel model.In addition, based on complex voltage and electric current Vx4, Ix4 and and the inductance based on inductor Lstrap is determined at the complex voltage at output 297 places of tunnel and band model 210 and electric current V21, I21 and output 297 is part 173(Fig. 1) output (for example model node N1m(Fig. 1)) example.It should be noted that Lstrap is the inductance of the computer-generated model of RF band.When 2MHz RF generator be open and 27 and 60MHz RF generator be close time, complex voltage and electric current V21, I21 and be determined to be in the 3rd complex voltage and the electric current at output 297 places.
Similarly, when 27MHz RF generator be open and 2 and 60MHz RF generator be close time, at the output complex voltage at 297 places and electric current V271, I271 and based at the output complex voltage at 259 places and electric current V27, I27 and the feature of (Fig. 3 B) and inductor Ltunnel, capacitor Ctunnel and inductor Lstrap is determined.When 2MHz and 27MHz RF generator the two be all open and 60MHz RF generator be close time, complex voltage and electric current V21, I21, v271, I271 and it is the example of the 3rd complex voltage and electric current.
In addition, similarly, when 60MHz RF generator is opened and 2 and during the power-off of 27MHz RF generator, at the complex voltage at output 297 places and electric current V601, I601 and complex voltage based on receiving in node 259 places and electric current V60, I60 and the feature of (Fig. 3 B) and inductor Ltunnel, capacitor Ctunnel and inductor Lstrap is determined.When 2MHz, 27MHz and 60MHz RF generator are all while opening, complex voltage and electric current V21, I21, v271, I271, v601, I601 and it is the example of the 3rd complex voltage and electric current.Method 102 finishes after operation 119.
Fig. 3 A is the block diagram of the execution mode of system 123, and it is for diagram impedance matching circuit 122.Impedance matching circuit 122 is impedance matching circuit 114(Fig. 1) example.Impedance matching circuit 122 comprise between electric component be connected in series and/or electric component between be connected in parallel.
Fig. 3 B is the circuit diagram of the execution mode of impedance matching model 172.Impedance matching model 172 is impedance matching model 104(Fig. 1) example.As shown in the figure, impedance matching model 172 comprises the capacitor with capacitor C 1 to C9, has the inductor of the inductance of LPF1, LPF2 and L1 to L4.It should be noted that in Fig. 3 B, inductor and/or capacitor mode coupled to each other is exemplary.For example, inductor and/or capacitor shown in Fig. 3 B can be coupled to each other in the mode of series connection and/or parallel connection.In addition, in some embodiments, impedance matching model 172 comprises capacitor and/or the inductor different from capacitor shown in Fig. 3 B and/or inductor quantity.
Fig. 4 is the figure of the execution mode of system 178, and it is for diagram RF transmission line 181, and RF transmission line 181 is RF transmission line 113(Fig. 1) example.RF transmission line 181 comprises cylinder 148, for example tunnel.In cylinder 148 hollow, be provided with insulator 189 and RF bar 142.The combination of cylinder 148 and RF bar 142 is RF transmission line 113(Fig. 1) part 169(Fig. 1) example.By bolt B 1, B2, B3 and B4, RF transmission line 181 is fixed (bolt) to impedance matching circuit 114.In one embodiment, RF transmission line 181 is fixed (bolt) to impedance matching circuit 114 by the bolt of any amount.In some embodiments, replace bolt or except bolt, the connector of any other form (for example, glue, screw etc.) is used to RF transmission line 181 to be connected to impedance matching circuit 114.
RF transmission pole 142 is coupled with the output of impedance matching circuit 114.In addition, RF band 144(is also referred to as RF spoon) be coupled with RF bar 142 and RF bar 199, a part for RF bar 199 is for example positioned at strutting piece 146(, cylinder) in.The strutting piece 146 that comprises RF bar 199 is examples of part 195 (Fig. 1).In one embodiment, cylinder 148, RF bar 142, RF with 144, strutting piece 146 and RF bar 199 be combined to form RF transmission line 181, RF transmission line 181 is RF transmission line 113(Fig. 1) example.Strutting piece 146 provides support for plasma chamber.Strutting piece 146 is connected to the ESC177 of plasma chamber.RF signal from x MHz generator via cable 150, impedance matching circuit 114, RF bar 142, RF be with 144 and RF bar 199 be provided for ESC177.
In one embodiment, ESC177 comprises heating element and the electrode on the top of this heating element.In one embodiment, ESC177 comprises heating element and bottom electrode.In one embodiment, ESC177 comprises bottom electrode and is embedded in the heating element in the hole being formed in bottom electrode, such as winding wire etc.In some embodiments, electrode is made by metal (such as aluminium, copper etc.).It should be noted that RF transmission line 181 provides the bottom electrode of RF signal to ESC177.
Fig. 5 A is the block diagram of the execution mode of system 171, and it is for diagram RF transmission line 113(Fig. 1) circuit model 176.For instance, circuit model 176 comprises the connection between connection, the connection between capacitor and/or inductor and the capacitor between inductor and/or capacitor, inductor.The example connecting comprises series connection and/or is connected in parallel.Circuit model 176 is RF mode 161(Fig. 1) example.
Fig. 5 B is the figure of the execution mode of circuit 180, and it is for diagram tunnel and band model 210, and tunnel and band model 210 are RF transmission line model 161(Fig. 1) part 173(Fig. 1) example.Circuit 180 comprises impedance matching model 172 and tunnel and band model 210.Tunnel and band model 210 comprise inductor Ltunnel and Lstrap and capacitor Ctunnel.It should be noted that inductor Ltunnel represents cylinder 148(Fig. 4) and the inductance of RF bar 142 and capacitor Ctunnel represents the electric capacity of cylinder 148 and RF bar 142.In addition, inductor Lstrap represents RF band 144(Fig. 4) inductance.
In one embodiment, tunnel and band model 210 comprise the inductor of any amount and/or the capacitor of any amount.In this embodiment, tunnel and band model 210 comprise any mode (such as series, parallel etc.) of a capacitor and another capacitor-coupled, inductor and capacitor-coupled and/or an inductor and the coupling of another inductor.
Fig. 5 C is the figure of the execution mode of circuit 300, and it is for diagram tunnel and band model 302, and tunnel and band model 302 are RF transmission line model 161(Fig. 1) part 173(Fig. 1) example.Tunnel and band model 302 are coupled to impedance matching model 172 via output 259.Tunnel and band model 302 include the inductor of 20 nanohenrys (NH) inductance and have the capacitor of 15 pico farads (pF), 31pF, 15.5pF and 18.5pF electric capacity.Tunnel and band model 302 are coupled to RF cylinder via node 304, and RF cylinder is coupled to ESC177 (Fig. 1).RF cylinder is the example of part 195 (Fig. 1).
It should be noted that in some embodiments, inductor and the capacitor of tunnel and band model 302 have other value.For example, 20nH inductor have scope between 15 and 20nH between or between 20 and 25nH between inductance.As another example, two or more in the inductor of tunnel and band model 302 have different induction.As another example, 15pF capacitor has the electric capacity of scope between electric capacity 8pF and 25pF, 31pF capacitor has the electric capacity of scope between 15pF and 45pF, 15.5pF capacitor has the electric capacity of scope between 9pF and 20pF, and 18.5pF capacitor has the electric capacity of scope between 10pF and 27pF.
In various execution modes, at tunnel and band model 302, comprise any amount of inductor and comprise the capacitor of any amount at tunnel and band model 302.
Fig. 6 is the schematic diagram for an execution mode of the circuit 310 of diagram cylinder and ESC model 312, and cylinder and ESC model 312 are combinations of inductor 313 and capacitor 316.Cylinder and ESC model 312 comprise type cylinder models and ESC model, and ESC model is the example of ESC model 125 (Fig. 1).Type cylinder models is the example of the part 197 (Fig. 1) of RF mode 161 (Fig. 1).Cylinder and ESC model 312 have feature like the feature class with the combination of part 195 and ESC177 (Fig. 1).For example, cylinder and ESC model 312 have the resistance identical with the resistance of the combination of part 195 and ESC177.As another example, cylinder and ESC model 312 have the inductance identical with the inductance of the combination of part 195 and ESC177.As another example, cylinder and ESC model 312 have the electric capacity identical with the electric capacity of the combination of part 195 and ESC177.As another example, cylinder and ESC model 312 have inductance, resistance, electric capacity or their combination identical with inductance, resistance, electric capacity or their combination of the combination of part 195 and ESC177.
Cylinder and ESC model 312 are coupled to tunnel and band model 302 by node 318.Node 318 is examples of model node N1m (Fig. 1).
It should be noted that in some embodiments, in cylinder and ESC model 312, use and there is the inductor that inductance is not 44 milihenries (mH).For example, use and there is the inductor of inductance range from 35mH to 43.9mH or from 45.1mH to 55mH.In various execution modes, use and there is the capacitor that electric capacity is not 550pF.For example, substitute 550pF capacitor, use have capacitance range between 250 and 550pF between or between 550 and 600pF between capacitor.
The combined impedance of the combination of the processor computation model 172 of host computer system 130 (Fig. 1), tunnel and band model 302 and cylinder and ESC model 312, for example, total impedance etc.By combined impedance be used as input at the definite complex voltage in model node 318 places and electric current by the processor of host computer system 130 and calculate complex voltage and the impedance at node N6m place.The output that it should be noted that cylinder and ESC model 312 is model node N6m.
Fig. 7 is the block diagram for the execution mode of the system 200 of definite variable.System 200 comprises plasma chamber 135, and plasma chamber 135 further comprises ESC201 and has input 285.Plasma chamber 135 is plasma chamber 175(Fig. 1) example and ESC201 is ESC177(Fig. 1) example.ESC201 comprises heating element 198.In addition, ESC201 by edge ring (ER) 194 around.ER194 comprises heating element 196.In one embodiment, ER194 contributes near the etch rate drift edge of the workpiece 131 being supported by ESC201 of uniform etch-rate and minimizing.
Power source 206 via filter 208 provide power to heating element 196 with heating heating element 196 and power source 204 via filter 202 provide power to heating element 198 with heating heating element 198.In one embodiment, single power source provide power to heating element 196 and 198 the two.Filter 208 filters out the power signal of the preset frequency that is received from power source 206 and filter 202 filters out the power signal of the preset frequency that is received from power source 204.
Thereby heating element 198 further maintains the environment in plasma chamber 135 temperature of hope by the power signal heating that is received from power source 204 the electrode of ESC198 is maintained to the temperature of hope.In addition, thus heating element 196 further maintains the environment in plasma chamber 135 temperature of hope by the power signal heating that is received from power source 206 ER194 is maintained to the temperature of hope.
It should be noted that in one embodiment, ER194 and ESC201 comprise the heating element of any amount and the heating element of any type.For example, ESC201 comprises inductive heating element or metallic plate.In one embodiment, each in ESC201 and ER194 includes one or more cooling element that allows cold water etc. to pass through, and one or more pipe for example, to maintain plasma chamber 135 temperature of hope.
Further, it should be noted that in one embodiment, system 200 comprises the filter of any amount.For example, power source 204 and 206 is via single filter coupled to ESC201 and ER194.
Fig. 8 A is the figure of the execution mode of system 217, and it is for diagram filter 202 and 208(Fig. 7) model to improve the precision of variable.System 217 comprises tunnel and the band model 210 that is coupled to model 216 via type cylinder models 211, and model 216 comprises capacitor and/or inductor and the connection between them of filter 202 and 208.Model 216 is stored in storage HU162(Fig. 1) and/or other storage HU in.The capacitor of model 216 and/or inductor are coupled to each other in modes such as parallel way, series system or its combination.Model 216 represents electric capacity and/or the inductance of filter 202 and 208.
In addition, system 217 comprises type cylinder models 211, and type cylinder models 211 is RF bar 199(Fig. 4) and strutting piece 146(Fig. 4) computer-generated model.Type cylinder models 211 has feature like the feature class with the electric component of RF bar 199 and strutting piece 146.Type cylinder models 211 comprises connection, the connection between capacitor and/or capacitor between one or more capacitor, one or more inductor, inductor and the connection between the combination of inductor.
The combined impedance of processor computation model 216 host computer system 130(Fig. 1), tunnel and band model 210 and type cylinder models 211, such as total impedance etc.Combined impedance provides complex voltage and the impedance at node N2m place.During variable by determining at node N2m place, comprise model 216 and tunnel and band model 210, the precision of described variable is enhanced.The output that it should be noted that model 216 is model node N2m.
Fig. 8 B is the figure of the execution mode of system 219, and it is for diagram filter 202 and 208(Fig. 7) model to improve the precision of variable.System 219 comprises tunnel and band model 210 and model 218, and model 218 is coupled in parallel to tunnel and band model 210.Model 218 is model 216(Fig. 8 A) example.Model 218 comprises inductor Lfilter, and inductor Lfilter represents the combination inductance of filter 202 and 208.Model 218 also comprises capacitor Cfilter, and capacitor Cfilter represents the direct combination capacitor of filter 202 and 208.
Fig. 9 is for utilizing VI probe 238 to measure the block diagram at the execution mode of the system 236 of the variable at output 231 places of RF generator 220.Output 231 is node N3(Fig. 1) or node N5(Fig. 1) example.RF generator 220 is examples of x MHz generator or yMHz generator (Fig. 1).Host computer system 130 produces has two or more multi-mode digital pulse signal 213 provide it to digital signal processor (DSP) 226.In one embodiment, digital pulse signal 213 is transistor-transistor logic (TTL) signals.The example of described state comprises state, high state and the low state that state that conducting state and cut-off state, numerical value are 1 and numerical value are 0, etc.
In another embodiment, replace host computer system 130, clock oscillator (for example crystal oscillator) is used to produce simulated clock simulation clock signal, and this simulated clock simulation clock signal is converted to the digital signal that is similar to digital pulse signal 213 by analog to digital converter.
Digital pulse signal 213 is sent to DSP226.DSP226 receives the state of digital pulse signal 213 discriminating digit pulse signal 213.For example, DSP226 determines that digital pulse signal 213 has the first magnitude during first group of time period, such as value 1, high state magnitude etc., and during second group of time period, there is the second magnitude, such as value 0, low state magnitude etc.DSP226 determines that digital pulse signal 213 has state S1 and during second group of time period, has state S0 during first group of time period.The example of state S0 comprises state and the cut-off state that low state, value are 0.The example of state S1 comprises state and the conducting state that high state, value are 1.Again for example, DSP226 compares to determine that by the value of the magnitude of digital pulse signal 213 and pre-stored the magnitude at digital pulse signal 213 during first group of time period is greater than the value of pre-stored and is not more than the value of pre-stored in the magnitude of digital pulse signal 213 during state S0 during second group of time period.In the execution mode of clock oscillator, DSP226 receives simulated clock simulation clock signal from clock oscillator, converts this analog signal to digital form, then identifies two states S0 and S1 in use.
When state is identified as S1, DSP226 provides performance number P1 and/or frequency value F 1 to parameter controller 222.In addition,, when state is identified as S0, DSP226 provides performance number P0 and/or frequency value F 0 to parameter controller 224.The example that is used for the parameter controller of tuned frequency comprises automatic-frequency tuner (AFT).
It should be noted that parameter controller 222, parameter controller 224 and DSP226 are the parts of control system 187.For example, parameter controller 222 and parameter controller 224 are the logical blocks as the part of the computer program carried out by DSP226, such as resonant tank etc.In some embodiments, computer program is for example embodied in, in non-volatile computer-readable medium (storing HU).
In one embodiment, replace parameter controller, use controllers such as hardware control, ASIC, PLD.For example, use hardware control to replace parameter controller 222, use another hardware control to replace parameter controller 224.
When received power value P1 and/or frequency value F 1, parameter controller 222 offers performance number P1 and/or frequency value F 1 driver 228 of driver and amplifier system (DAS) 232.The example of driver comprises analog line driver, current driver, voltage driver, transistor, etc.Driver 228 produces the amplifier 230 that has the RF signal of performance number P1 and/or frequency value F 1 and this RF signal is offered to DAS232.
In one embodiment, driver 228 produce have as the driving power value of the function of performance number P1 and/or there is the RF signal as the driving frequency value of the function of frequency value F 1.For example, driving power value within the scope of the performance number P1 of some (such as 1 to 5 etc.) watt and driving frequency value in frequency value F 1 scope of some (such as 1 to 5 etc.) Hz.
Amplifier 230 amplifications have the RF signal of performance number P1 and/or frequency value F 1 and produce corresponding to the RF signal 215 that is received from the RF signal of driver 228.For example, RF signal 215 has the high quantity of power of amount of specific power value P1.Again for example, RF signal 215 has the quantity of power identical with the amount of performance number P1.RF signal 215 sends ESC177(Fig. 1 to via cable 217 and impedance matching circuit 114).
Cable 217 is cable 150 or cable 152(Fig. 1) example.For example, when RF generator 220 is the example of x MHz RF generator (Fig. 1), cable 217 is examples of cable 150, and when RF generator 220 is the example of y MHz RF generator (Fig. 1), cable 217 is examples of cable 152.
When performance number P1 and/or frequency value F 1 are offered DAS232 and RF signal 215 and produced by parameter controller 222, VI probe 238 is measured the value at the variable at output 231 places with cable 217 couplings.VI probe 238 is VI probe 110 or VI probe 111(Fig. 1) example.VI probe 238 sends to host computer system 130 via communication equipment 233 by the value of variable, for host computer system 130 manner of execution 102(Fig. 3) and method as herein described 340,351 and 363(Figure 13,15 and 17).Communication equipment 233 is communication equipment 185 or 189(Fig. 1) example.Communication equipment 233 adopts such as Ethernets, EtherCAT, USB, serial, parallel, package (packetization), the agreements such as (depacketization) of unpacking data is sent to host computer system 130 from VI probe 238.In various execution modes, host computer system 130 comprises the communication equipment of the agreement that employing communication equipment 233 adopts.For example, when communication equipment 233 adopts packetizing protocol, the communication equipment of host computer system 130 adopts shrinkwrap agreement.Again for example, when communication equipment 233 adopts serial transmission protocol, the communication equipment of host computer system 130 adopts serial transmission protocol.
Similarly, when received power value P0 and/or frequency value F 0, parameter controller 224 offers driver 228 by performance number P0 and/or frequency value F 0.Driver 228 produces to be had the RF signal of performance number P0 and/or frequency value F 0 and this RF signal is offered to amplifier 230.
In one embodiment, driver 228 produce have as the driving power value of the function of performance number P0 and/or there is the RF signal as the driving frequency value of the function of frequency value F 0.For example, driving power value for example, within the scope of the performance number P0 of some (1 to 5) watt and driving frequency value for example, in frequency value F 0 scope of some (1 to 5) Hz.
Amplifier 230 amplifications have the RF signal of performance number P0 and/or frequency value F 0 and produce corresponding to the RF signal 221 that is received from the RF signal of driver 228.For example, RF signal 221 has the high quantity of power of amount of specific power value P0.Again for example, RF signal 221 has the quantity of power identical with the amount of performance number P0.RF signal 221 sends known load 112(Fig. 2 to via cable 217 and impedance matching circuit 114).
When performance number P0 and/or frequency value F 0 are offered DAS232 and RF signal 221 and produced by parameter controller 222, VI probe 238 is measured the value at the variable at output 231 places.VI probe 238 sends to host computer system 130 by the value of variable, for host computer system 130 manner of execution 102(Fig. 2), method 340(Figure 13), method 351(Figure 15) or method 363(Figure 17).
It should be noted that in one embodiment VI probe 238 and DSP226 decoupling zero.In some embodiments, VI probe 238 is coupled to DSP226.Further, it should be noted that at the RF signal 215 producing during state S1 and the RF signal 221 that produces are parts of combination RF signal during state S0.For example, RF signal 215 is the parts with the combination RF signal of the quantity of power higher than RF signal 221, and RF signal 221 is another part of combination RF signal.
Figure 10 is the block diagram of the execution mode of system 250, and wherein VI probe 238 and communication equipment 233 are positioned at the outside of RF generator 220.In Fig. 1, VI probe 110 is positioned at x MHz RF generator to measure the variable at the outgoing position of x MHz RF generator.VI probe 238 is positioned at the outside of RF generator 220 to measure the variable at output 231 places of RF generator 220.VI probe 238 be associated with the output 231 of RF generator 220 (for example, coupling).
Figure 11 is the block diagram of the execution mode of system 128, wherein utilizes the value of the system 126 determined variablees of Fig. 1 to be used.System 128 comprises m MHz RF generator, n MHz RF generator, impedance matching circuit 115, RF transmission line 287 and plasma chamber 134.Plasma chamber 134 can be similar to plasma chamber 175.
It should be noted that in one embodiment, the x MHz RF generator of Fig. 2 is similar to m MHz RF generator and the y MHz RF generator of Fig. 2 is similar to n MHz RF generator.For example, x MHz equals m MHz and y MHz equals n MHz.Again for example, x MHz generator has similar frequency with m MHz generator and y MHz generator has similar frequency with n MHz generator.The example of similar frequencies is for example, when x MHz is in the window (window) of m MHz frequency when (, within the scope of kHz or Hz).In some embodiments, the x MHz RF generator of Fig. 2 y MHz RF generator not similar with m MHz RF generator and Fig. 2 is not similar with n MHz RF generator.
Be furthermore noted that, in various execution modes, the transducers different from being used in sensor type in each of x MHz and y MHz RF generator are used in each of m MHz and n MHz RF generator.For example, the transducer of not following NIST standard is used in m MHz RF generator.Again for example, the voltage sensor of a measuring voltage is used in m MHz RF generator.
Further, it should be noted that in one embodiment, impedance matching circuit 115 is similar to impedance matching circuit 114(Fig. 1).For example, the impedance phase of the impedance of impedance matching circuit 114 and impedance matching circuit 115 is same.Again for example, the impedance of impedance matching circuit 115 (for example,, in 10-20% of the impedance of impedance matching circuit 114) in the window of the impedance of impedance matching circuit 114.In some embodiments, impedance matching circuit 115 is not similar with impedance matching circuit 114.
Impedance matching circuit 115 comprises electric component (such as inductor, capacitor etc.) so that be coupled in the impedance of the power source of impedance matching circuit 115 and mate with the impedance phase that is coupled in the load of circuit 115.For example, impedance matching circuit 114 makes to be coupled in the impedance in source (such as m MHz generator, n MHz RF generator with by the combination of the cable of m MHz generator and the coupling of nMHz RF generator) of impedance matching circuit 114 and the impedance matching of load (such as the combination of plasma chamber 134 and RF transmission line 287 etc.).
It should be noted that in one embodiment, RF transmission line 287 is similar to RF transmission line 113(Fig. 1).For example, the impedance phase of the impedance of RF transmission line 287 and RF transmission line 113 is same.Again for example, the impedance of RF transmission line 287 (for example,, in 10-20% of the impedance of RF transmission line 113) in the window of the impedance of RF transmission line 113.In various execution modes, RF transmission line 287 is not similar with RF transmission line 113.
Plasma chamber 134 comprises ESC192, top electrode 264 and other parts (not shown), other parts for example around the upper dielectric collar of top electrode 264, around the top electrode extension of upper dielectric collar, around the lower dielectric collar of the bottom electrode of ESC192, around the bottom electrode extension of lower dielectric collar, upper plasma forbidden zone (PEZ) ring, lower PEZ ring, etc.Top electrode 264 is positioned at the opposite of ESC192 and towards ESC192.Workpiece 262, such as semiconductor wafer etc., is supported on the upper surface 263 of ESC192.Each in the bottom electrode of top electrode 264 and ESC192 is made by metal (such as aluminium, aluminium alloy, copper etc.).
In one embodiment, top electrode 264 comprises the hole of being coupled to central gas feed arrangement (not shown).Central authorities' gas feed arrangement receives one or more process gas from gas supply source (not shown).Top electrode 264 ground connection.ESC192 is coupled to m MHz RF generator and n MHz RF generator via impedance matching circuit 115.
When process gas is supplied between top electrode 264 and ESC192 and when m MHz RF generator and/or n MHz RF generator are via impedance matching circuit 115 supply power during to ESC192, described process gas is lighted with at the interior generation plasma of plasma chamber 134.
It should be noted that system 128 does not have probe (for example, metering outfit, VI probe, voltage probe etc.) to measure output 283 places at impedance matching circuit 115, the some place on RF transmission line 287 or at the variable at ESC192 place.Whether as desired variate-value at model node N1m, N2m, N4m and N6m place is used to determine system 128 operation.
In various execution modes, system 128 does not have wafer bias transducer (for example, original position direct current (DC) probe pins (pick-up pin)) and is used to measure the related hardware at the wafer bias at ESC192 place.Do not use wafer bias transducer and related hardware to save cost.
Shall also be noted that in execution mode, system 128 comprises the RF generator that is coupled to impedance matching circuit of any amount.
Figure 12 A, 12B and 12C are illustrated in by using voltage probe at system 126(Fig. 1) in impedance matching circuit 114(Fig. 1) output (such as the node N4) voltage (such as RMS voltage, crest voltage etc.) locating to record and utilize method 102(Fig. 2) definite at corresponding model node, export Figure 26 8,272 of the correlation between the voltage that (such as node N4m) locate (such as crest voltage etc.) and the figure of 275 execution mode.In addition, Figure 12 A, 12C and 12E are illustrated in by using current probe at system 126(Fig. 1) output (such as the node N4) electric current locating to record (such as root mean square (RMS) electric current etc.) and utilize method 102(Fig. 2) definite in correspondence, export Figure 27 0,274 of the correlation between the electric current that (such as node N4m) locate (such as RMS electric current etc.) and the figure of 277 execution mode.
Utilize the definite voltage of method 102 to be plotted on the x axle in each Figure 26 8,272 and 275 and utilize the voltage that voltage probe records to be plotted on the y axle in each Figure 26 8,272 and 275.Similarly, utilize the definite electric current of method 102 to be plotted on the x axle in each Figure 27 0,274 and 277 and utilize the electric current that current probe records to be plotted on the y axle in each Figure 27 0,274 and 277.
When x MHz RF generator, open and y MHz RF generator and z MHz RF generator (for example 60MHz RF generator) while closing, voltage is plotted in Figure 26 8.In addition, when y MHz RF generator, open and x and z MHz RF generator while closing, voltage is plotted in Figure 27 2.In addition, when z MHz RF generator, open and x and y MHz RF generator while closing, voltage is plotted in Figure 27 5.
Similarly, when x MHz RF generator, open and y MHz RF generator and z MHz RF generator while closing, electric current is plotted in Figure 27 0.In addition, when y MHz RF generator, open and x and z MHz RF generator while closing, electric current is plotted in Figure 27 4.In addition, when z MHz RF generator, open and x and y MHz RF generator while closing, electric current is plotted in Figure 27 7.
Visible in each Figure 26 8,272 and 275, draw the voltage on y axle in the drawings and draw between the voltage on x axle in the drawings and have near-linear dependency.Similarly, visible in each Figure 27 0,274 and 277, there is near-linear dependency being plotted in the electric current on y axle and being plotted between the electric current on x axle.
Figure 13 is the flow chart of execution mode of the method 340 of the biasing located of the model node (for example, model node N4m, model node N1m, model node N2m, model node N6m etc.) for determining at plasma system 126 (Fig. 1).It should be noted that in some embodiments, wafer bias is direct current (DC) voltage by the plasma generation producing in plasma chamber 175 (Fig. 1).In these execution modes, wafer bias is for example present in, for example, on the surface (, upper surface) of the upper and/or workpiece 131 (Fig. 1) in the surface (, upper surface 183) of ESC177 (Fig. 1).
Shall also be noted that model node N1m and N2m are on RF mode 161 (Fig. 1) and model node N6m is on ESC model 125 (Fig. 1).Method 340 is to be carried out by the processor of host computer system 130 (Fig. 1).In method 340, executable operations 106.
In addition, in operation 341, (for example generate corresponding one or more device, impedance matching circuit 114, RF transmission line 113, ESC177, their combination etc.) one or more models, for example, impedance matching model 104, RF mode 161, ESC model 125 (Fig. 1), their combination etc.For example, generate ESC model 125, make it there is similar feature to ESC177 (Fig. 1).
In operation 343, the complex voltage identifying in operation 106 and electric current are transmitted by one or more elements of described one or more models, to determine complex voltage and the electric current in the output of described one or more models.For example, from the first complex voltage and electric current, determine the second complex voltage and electric current.Again for example, from the first complex voltage and electric current, determine the second complex voltage and electric current and determine the 3rd complex voltage and electric current from the second complex voltage and electric current.As another example, from the first complex voltage and electric current, determine the second complex voltage and electric current, from the second complex voltage and electric current, determine the 3rd complex voltage and electric current, and the 3rd complex voltage and electric current transmission are determined to the 4th complex voltage and the electric current at model node N2m place by the part 197 of RF mode 161 (Fig. 1).In this example, the 4th complex voltage and electric current are by the 3rd complex voltage and electric current transmission are determined by the impedance of the element of part 197.As another example, RF mode 161 provides the algebraically transfer function of being carried out by the processor of host computer system 130 so that the complex voltage that the one or more outputs at one or more RF generators are recorded and electric current are transferred to electrical node along RF mode 161, for example, model node N1m, model node N2m etc.
Another example as operation 343, from the first complex voltage and electric current, determine the second complex voltage and electric current, from the second complex voltage and electric current, determine the 3rd complex voltage and electric current, from the 3rd complex voltage and electric current, determine the 4th complex voltage and electric current, and the 4th complex voltage and electric current transmission are determined to the 5th complex voltage and the electric current at model node N6m place by ESC model 125.In this example, the 5th complex voltage and electric current are by the 4th complex voltage and electric current transmission for example, are determined by the impedance of the element (, electric capacity, inductance etc.) of ESC model 125.
In operation 342, the complex voltage of the output based at one or more models and the voltage magnitude of electric current, at the complex voltage of this output and the current amplitude of electric current and in the power magnitude of complex voltage and the electric current of this output, to determine the wafer bias in this output.For example, wafer bias is that the current amplitude of voltage magnitude, the second complex voltage and electric current and the power magnitude of the second complex voltage and electric current based on the second complex voltage and electric current determined.In order to further illustrate, open-minded at x MHz RF generator, and when y MHz and z MHz RF generator are closed, the processor of host computer system 130 (Fig. 1) determines that the conduct first of locating at model node N4m (Fig. 1) is long-pending, second long-pending, the wafer bias of the summation of the 3rd long-pending and constant.In this explanation, first long-pending be voltage magnitude long-pending of the first coefficient and the second complex voltage and electric current, second long-pending be current amplitude long-pending of the second coefficient and the second complex voltage and electric current, and the 3rd long-pending be the subduplicate long-pending of the square root of the 3rd coefficient and the power magnitude of the second complex voltage and electric current.
As example, power magnitude is the power magnitude of transmitted power, and the power transmitting is determined poor as between forward power and reflection power by the processor of host computer system 130.Forward power is by one or more RF generators of system 126 (Fig. 1), to be supplied to the power of plasma chamber 175 (Fig. 1).Reflection power is from plasma chamber 175, to reflect back into the power of one or more RF generators of system 126 (Fig. 1).As example, the power magnitude of complex voltage and electric current is determined amassing as the current amplitude of complex voltage and electric current and the voltage magnitude of complex voltage and electric current by the processor of host computer system 130.In addition, be used for determining that the coefficient of wafer bias and each in constant are positive number or negative.As another example of determining wafer bias, when xMHz RF generator open-minded, and y and z MHz RF generator are when close, wafer bias at model Nodes is expressed as ax*Vx+bx*Ix+cx*sqrt (Px)+dx, wherein " ax " is the first coefficient, " bx " is the second coefficient, " dx " is constant, " Vx " is at the complex voltage of model Nodes and the voltage magnitude of electric current, " Ix " is at the complex voltage of model Nodes and the current amplitude of electric current, and " Px " is the power magnitude at complex voltage and the electric current of model Nodes.It should be noted that " sqrt " is square root calculation, its processor by host computer system 130 is carried out.In some embodiments, power magnitude Px is the long-pending of current amplitude Ix and voltage magnitude Vx.
In various execution modes, for the coefficient of definite wafer bias, by the processor of host computer system 130 (Fig. 1), based on projective techniques, determined.In projective techniques, wafer bias transducer, for example, wafer bias pin etc., measure for example, wafer bias on surface at ESC177 (, upper surface 183 (Fig. 1), etc.) for the first time.In addition,, in projective techniques, the complex voltage that the output based at RF generator records and electric current, determine voltage magnitude, current amplitude and the power magnitude of the model Nodes in plasma system 126.For example, processor by host computer system 130 (is for example sent to model node by the complex voltage of locating to record at node N3 (Fig. 1) for the first time and electric current, model node N4m, model node N1m, model node N2m or model node N6m (Fig. 1) etc.), to determine the primary complex voltage at model Nodes and electric current.Voltage magnitude and current amplitude are obtained according to the primary complex voltage at model Nodes and electric current by the processor of host computer system 130.In addition, power magnitude calculates as the long-pending processor by host computer system 130 of primary current amplitude and voltage magnitude.
Similarly, in this example, at node N3 place to complex voltage and the extra one or many of current measurement, and measured complex voltage and electric current are transmitted, to determine complex voltage and the electric current for example, located at this model node (, model node N4m, model node N1m, model node N2m or model node N6m etc.) of the one or many that this is extra.In addition, according to the definite complex voltage of this extra one or many and electric current, obtain voltage magnitude, current amplitude and the power magnitude of this extra one or many.By the processor of host computer system 130 by mathematical function (for example, PLS, linear regression etc.) be applied to for the first time and voltage magnitude, current amplitude, power magnitude and measured wafer bias that extra one or many obtains, with Coefficient of determination ax, bx, cx and constant dx.
Another example as operation 342, when y MHz RF generator opens and x and zMHz RF generator while cutting out, wafer bias is defined as ay*Vy+by*Iy+cy*sqrt (Py)+dy, wherein " ay " is coefficient, " by " is coefficient, and " dy " is constant, and " Vy " is the voltage magnitude of the second complex voltage and electric current, " Iy " is the current amplitude of the second complex voltage and electric current, and " Px " is the power magnitude of the second complex voltage and electric current.Power magnitude Py is the long-pending of current amplitude Iy and voltage magnitude Vy.Another example as operation 342, when z MHz RF generator open-minded, and x and y MHz RF generator are when close, wafer bias is confirmed as az*Vz+bz*Iz+cz*sqrt (Pz)+dz, and wherein " az " is coefficient, and " bz " is coefficient, " dz " is constant, " Vz " is the voltage magnitude of the second complex voltage and electric current, and " Iz " is the current amplitude of the second complex voltage and electric current, and " Pz " is the power magnitude of the second complex voltage and electric current.Power magnitude Pz is the long-pending of current amplitude Iz and voltage magnitude Vz.
As operation another example of 342, when x and y MHz RF generator open-minded, and z MHz RF generator is when cut out, that wafer bias is confirmed as is first long-pending, the summation of second long-pending, the 3rd long-pending, the 4th long-pending, the 5th long-pending, the 6th long-pending and constant.First long-pending be the long-pending of the first coefficient and voltage magnitude Vx, second long-pending be the long-pending of the second coefficient and current amplitude Ix, the 3rd long-pending be the subduplicate long-pending of the 3rd coefficient and power magnitude Px, the 4th long-pending be the long-pending of Quaternary system number and voltage magnitude Vy, the 5th long-pending be the long-pending of the 5th coefficient and current amplitude Iy, and the 6th long-pending be the subduplicate long-pending of the 6th coefficient and power magnitude Py.When x and y MHz RF generator open-minded, and zMHz RF generator is when cut out, wafer bias is expressed as axy*Vx+bxy*Ix+cxy*sqrt (Px)+dxy*Vy+exy*Iy+fxy*sqrt (Py)+gxy, wherein " axy ", " bxy ", " cxy ", " dxy ", " exy ", " fxy ", " dxy ", " exy " and " fxy " are coefficients, and " gxy " is constant.
Another example as operation 342, when y and z MHz RF generator open-minded, and x MHz RF generator is when cut out, wafer bias is confirmed as ayz*Vy+byz*Iy+cyz*sqrt (Py)+dyz*Vz+eyz*Iz+fyz*sqrt (Pz)+gyz, wherein " ayz ", " byz ", " cyz ", " dyz ", " eyz " and " fyz " are coefficients, and " gyz " is constant.Another example as operation 342, when x and z MHz RF generator open-minded, and y MHz RF generator is when cut out, wafer bias is confirmed as axz*Vx+bxz*Ix+cxz*sqrt (Px)+dxz*Vz+exz*Iz+fxz*sqrt (Pz)+gxz, wherein " axz ", " bxz ", " cxz ", " dxz ", " exz " and " fxz " are coefficients, and gxz is constant.
As operation another example of 342, when x, y and z MHz RF generator are opened, that wafer bias is confirmed as is first long-pending, the summation of second long-pending, the 3rd long-pending, the 4th long-pending, the 5th long-pending, the 6th long-pending, the 7th long-pending, the 8th long-pending, the 9th long-pending and constant.First long-pending be the long-pending of the first coefficient and voltage magnitude Vx, second long-pending be the long-pending of the second coefficient and current amplitude Ix, the 3rd long-pending be the subduplicate long-pending of the 3rd coefficient and power magnitude Px, the 4th long-pending be the long-pending of Quaternary system number and voltage magnitude Vy, the 5th long-pending be the long-pending of the 5th coefficient and current amplitude Iy, the 6th long-pending be the subduplicate long-pending of the 6th coefficient and power magnitude Py, the 7th long-pending be the long-pending of the 7th coefficient and voltage magnitude Vz, the 8th long-pending be the long-pending of the 8th coefficient and current amplitude Iz, and the 9th long-pending be the subduplicate long-pending of the 9th coefficient and power magnitude Pz.When x, y and z MHz RF generator are opened, wafer bias is expressed as axyz*Vx+bxyz*Ix+cxyz*sqrt (Px)+dxyz*Vy+exyz*Iy+fxyz*sqrt (Py)+gxyz*Vz+hxyz*Iz+ixyz*sqrt (Pz)+jxyz, wherein " axyz ", " bxyz ", " cxyz ", " dxyz ", " exyz ", " fxyz ", " gxyz ", " hxyz " and " ixyz " are coefficients, and " jxyz " is constant.
As another example of determining at the wafer bias of the output of one or more models, the voltage and current amplitude at the wafer bias at model node N1m place based on definite at model node N1m place is determined by the processor of host computer system 130.In order to further illustrate, the second complex voltage and electric current transmit along part 173 (Fig. 1), to determine complex voltage and the electric current at model node N1m place.To be similar to from the first complex voltage and electric current, determine that the mode of the mode of the second complex voltage and electric current determines complex voltage and the electric current at model node N1m from the second complex voltage and electric current.For example, the feature of the second complex voltage and the electric current element based on part 173 transmits along part 173, to determine complex voltage and the electric current at model node N1m place.
Based at model node N1m place definite complex voltage and electric current, wafer bias is determined at model node N1m place by the processor of host computer system 130.For example, to be similar to from the second complex voltage and electric current, determine in the mode of the mode of the wafer bias of model node N4m, from the complex voltage at model node N1m and electric current, determine the wafer bias at model node N1m place.Illustrate, when x MHz RF generator opens and y MHz and z MHz RF generator while cutting out, the processor of host computer system 130 (Fig. 1) determines that the wafer bias at model node N1m place is summation first long-pending, second long-pending, the 3rd long-pending and constant.In this example, first long-pending be the first coefficient and amassing at the complex voltage at model node N1m place and the voltage magnitude of electric current, second long-pending be the second coefficient and long-pending at the complex voltage at model node N1m place and the current amplitude of electric current, and the 3rd be long-pendingly the square root of the 3rd coefficient and amass at the subduplicate of the complex voltage at model node N1m place and the power magnitude of electric current.When x MHz RF generator opens and y and z MHz RF generator while cutting out, wafer bias at model node N1m place is expressed as ax*Vx+bx*Ix+cx*sqrt (Px)+dx, wherein ax is the first coefficient, bx is the second coefficient, cx is the 3rd coefficient, and dx is constant, and Vx is the voltage magnitude at model node N1m place, Ix is the current amplitude at model node N1m place, and Px is the power magnitude at model node N1m place.
Similarly, complex voltage based at model node N1m place and electric current and based on x, the generator of opening in y and zMHzRF generator, determine wafer bias ay*Vy+by*Iy+cy*sqrt (Py)+dy, az*Vz+bz*Iz+cz*sqrt (Pz)+dz, axy*Vx+bxy*Ix+cxy*sqrt (Px)+dxy*Vy+exy*Iy+fxy*sqrt (Py)+gxy, axz*Vx+bxz*Ix+cxz*sqrt (Px)+dxz*Vz+exz*Iz+fxz*sqrt (Pz)+gxz, ayz*Vy+byz*Iy+cyz*sqrt (Py)+dyz*Vz+eyz*Iz+fyz*sqrt (Pz)+gyz, and axyz*Vx+bxyz*Ix+cxyz*sqrt (Px)+dxyz*Vy+exyz*Iy+fxyz*sqrt (Py)+gxyz*Vz+hxyz*Iz+ixyz*sqrt (Pz)+jxyz.
As the another example of determining at the wafer bias of the output of one or more models, with with based on determining the similar mode of mode at the wafer bias at model node N1m place in the definite voltage and current amplitude in model node N1m place, based on determining the wafer bias at model node N2m place in the definite voltage and current amplitude in model node N2m place by the processor of host computer system 130.In order to further illustrate, at model node N2m place, determine wafer bias ax*Vx+bx*Ix+cx*sqrt (Px)+dx, ay*Vy+by*Iy+cy*sqrt (Py)+dy, az*Vz+bz*Iz+cz*sqrt (Pz)+dz, axy*Vx+bxy*Ix+cxy*sqrt (Px)+dxy*Vy+exy*Iy+fxy*sqrt (Py)+gxy, axz*Vx+bxz*Ix+cxz*sqrt (Px)+dxz*Vz+exz*Iz+fxz*sqrt (Pz)+gxz, ayz*Vy+byz*Iy+cyz*sqrt (Py)+dyz*Vz+eyz*Iz+fyz*sqrt (Pz)+gyz, and axyz*Vx+bxyz*Ix+cxyz*sqrt (Px)+dxyz*Vy+exyz*Iy+fxyz*sqrt (Py)+gxyz*Vz+hxyz*Iz+ixyz*sqrt (Pz)+jxyz.
As the another example of determining at the wafer bias of the output of one or more models, with with based on determining the similar mode of mode at the wafer bias at model node N2m place in the definite voltage and current amplitude in model node N2m place, based on determining the wafer bias at model node N6m place in the definite voltage and current amplitude in model node N6m place by the processor of host computer system 130.In order to further illustrate, at model node N6m place, determine wafer bias ax*Vx+bx*Ix+cx*sqrt (Px)+dx, ay*Vy+by*Iy+cy*sqrt (Py)+dy, az*Vz+bz*Iz+cz*sqrt (Pz)+dz, axy*Vx+bxy*Ix+cxy*sqrt (Px)+dxy*Vy+exy*Iy+fxy*sqrt (Py)+gxy, axz*Vx+bxz*Ix+cxz*sqrt (Px)+dxz*Vz+exz*Iz+fxz*sqrt (Pz)+gxz, ayz*Vy+byz*Iy+cyz*sqrt (Py)+dyz*Vz+eyz*Iz+fyz*sqrt (Pz)+gyz, and axyz*Vx+bxyz*Ix+cxyz*sqrt (Px)+dxyz*Vy+exyz*Iy+fxyz*sqrt (Py)+gxyz*Vz+hxyz*Iz+ixyz*sqrt (Pz)+jxyz.
It should be noted that in some embodiments, wafer bias is stored in storage HU162 (Fig. 1).
Figure 14 is the state diagram that is illustrated in the execution mode of the wafer bias generator 340 of realizing in host computer system 130 (Fig. 1).When all x, y and z MHz RF generator are closed, wafer bias is zero or minimum at model Nodes, model node as, model node N4m, N1m, N2m, N6m (Fig. 1), etc.When x, y or z MHz RF generator open-minded, and remaining x, y and z MHz RF generator are when close, wafer bias generator 340 at model node (is for example determined, model node N4m, N1m, N2m, N6m, etc.) wafer bias located is the summation of the first long-pending a*V, the second long-pending b*I, the 3rd long-pending c*sqrt (P) and constant d, wherein V is at the complex voltage of model Nodes and the voltage magnitude of electric current, I is the current amplitude of complex voltage and electric current, P is the power magnitude of complex voltage and electric current, a is coefficient, b is coefficient, c is coefficient, and d is constant.In various execution modes, in the power magnitude of model Nodes, be the current amplitude of this model Nodes and long-pending at the voltage magnitude of this model Nodes.In some embodiments, power magnitude is the amplitude of transmitted power.
Work as x, in y and z MHz RF generator two are open-minded, x, when all the other in y and z MHz RF generator are closed, wafer bias generator 340 is determined at model node (as, model node N4m, N1m, N2m, N6m etc.) wafer bias of locating is the first long-pending a12*V1, the second long-pending b12*I1, the 3rd long-pending c12*sqrt (P1), the 4th long-pending d12*V2, the 5th long-pending e12*I2, the summation of the 6th long-pending f12*sqrt (P2) and constant g12, wherein " V1 " is by being transmitted in voltage that the output of the RF generator of opening in RF generator records and definite at the complex voltage of model Nodes and the voltage magnitude of electric current, " I1 " is by being transmitted in electric current that the output of a RF generator of opening records and definite complex voltage and the current amplitude of electric current, " P1 " is defined as the long-pending complex voltage of V1 and I1 and the power magnitude of electric current, " V2 " is by being transmitted in voltage that the output of the 2nd RF generator of opening in RF generator records and definite at the complex voltage of model Nodes and the voltage magnitude of electric current, " I2 " is by being transmitted in electric current that the output of the 2nd RF generator of opening records and definite complex voltage and the current amplitude of electric current, " P2 " is the long-pending power magnitude that is defined as V2 and I2, " a12 ", " b12 ", " c12 ", " d12 ", each in " e12 " and " f12 " is coefficient, and " g12 " is constant.
As all x, when y and z MHz RF generator are all opened, wafer bias generator 340 is for example determined, at model node (, model node N4m, N1m, N2m, N6m etc.) wafer bias of locating is as the first long-pending a123*V1, the second long-pending b123*I1, the 3rd long-pending c123*sqrt (P1), the 4th long-pending d123*V2, the 5th long-pending e123*I2, the 6th long-pending f123*sqrt (P2), the 7th long-pending g123*V3, the 8th long-pending h123*I3, the summation of the 9th long-pending i123*sqrt (P3) and constant j123, wherein " V1 " is by being transmitted in voltage that the output of the RF generator in RF generator records and definite at the complex voltage of model Nodes and the voltage magnitude of electric current, " I1 " is by being transmitted in electric current that the output of a RF generator records and definite complex voltage and the current amplitude of electric current, " P1 " is defined as the long-pending complex voltage of V1 and I1 and the power magnitude of electric current, " V2 " is by being transmitted in voltage that the output of the 2nd RF generator in RF generator records and definite at the complex voltage of model Nodes and the voltage magnitude of electric current, " I2 " is by being transmitted in electric current that the output of the 2nd RF generator records and definite complex voltage and the current amplitude of electric current, " P2 " is defined as the long-pending complex voltage of V2 and I2 and the power magnitude of electric current, " V3 " is by being transmitted in voltage that the output of the 3rd RF generator in RF generator records and definite at the complex voltage of model Nodes and the voltage magnitude of electric current, " I3 " is by being transmitted in electric current that the output of the 3rd RF generator records and definite complex voltage and the current amplitude of electric current, " P3 " is defined as the long-pending complex voltage of V3 and I3 and the power magnitude of electric current, " a123 ", " b123 ", " c123 ", " d123 ", " e123 ", " f123 ", " g123 ", each in " h123 " and " i123 " is coefficient, and " j123 " is constant.
Figure 15 is for determining along at model node N4m(Figure 16) and ESC model 125(Figure 16) between the flow chart of execution mode of method 351 of the wafer bias located of the point (Figure 16) in path 353.Figure 15 describes with reference to Figure 16, and Figure 16 is for determining the block diagram at the execution mode of the system 355 of the wafer bias of the output of model.
In operation 357, detect the output of x, y or z MHz RF generator, to identify generator output complex voltage and electric current.For example, voltage and current probe 110(Fig. 1) measure at node N3(Fig. 1) complex voltage and the electric current located.In this example, by host computer system 130(Fig. 1) by communicator 185(Fig. 1) from voltage and current probe 110, receive complex voltage and electric current, to store storage HU162(Fig. 1 into) in.In addition, in this example, the processor of host computer system 130 identifies complex voltage and electric current from storage HU162.
In operation 359, the processor of host computer system 130 uses generator output complex voltage and electric current, to determine complex voltage and the electric current in the projection at the some place in the path 353 along between model node N4m and model node N6m.Path 161 extends to model node N6m from model node N4m.For example, the 5th complex voltage and electric current are to determine according to the complex voltage and the electric current that record in the output of x MHz RF generator, yMHz RF generator or z MHz RF generator.As another example, the complex voltage recording at node N3 or node N5 place and electric current transmit via impedance matching model 104, to determine complex voltage and the electric current of locating at model node N4m (Fig. 1).In this example, at the complex voltage at model node N4m place and electric current via one or more elements of RF mode 161 (Figure 16) and/or send complex voltage and the electric current at certain the some place that determines in path 353 via one or more elements of ESC model 125 (Figure 16).
In operation 361, the complex voltage of the processor of host computer system 130 definite projection using the some place on path 353 and electric current as the input of function so that the complex voltage of projection and electric current are mapped to the wafer bias value at the node N6m place of ESC model 125 (Figure 15).For example, when x, y or z MHz RF generator are opened, wafer bias at model node N6m place is defined as to the summation of the first long-pending a*V, the second long-pending b*I, the 3rd long-pending c*sqrt (P) and constant d, wherein, V is at the complex voltage of projection at model node N6m place and the voltage magnitude of electric current, I is at the complex voltage of projection at model node N6m place and the current amplitude of electric current, P is in the complex voltage of projection at model node N6m place and the power magnitude of electric current, a, b and c are coefficients, and d is constant.
As another example, work as x, two RF generators in y and z MHz RF generator are open-minded, and x, when all the other the RF generators in y and z MHz RF generator cut out, the wafer bias at model node N6m place is defined as to the first long-pending a12*V1, the second long-pending b12*I1, the 3rd long-pending c12*sqrt (P1), the 4th long-pending d12*V2, the 5th long-pending e12*I2, the summation of the 6th long-pending f12*sqrt (P2) and constant g12, wherein V1 is the voltage magnitude at model node N6m place of the result opened as the RF generator in described two RF generators, I1 is the current amplitude at model node N6m place of the result opened as a RF generator, P1 is the power magnitude at model node N6m place of the result opened as a RF generator, V2 is the voltage magnitude at model node N6m place of the result opened as the 2nd RF generator in described two RF generators, I2 is the current amplitude at model node N6m place of the result opened as the 2nd RF generator, and P2 is the power magnitude at model node N6m place of the result opened as the 2nd RF generator, a12, b12, c12, d12, e12, and f12 is coefficient, g12 is constant.
As another example, as all x, when y and z MHz RF generator are all opened, wafer bias at model node N6m place is defined as to the first long-pending a123*V1, the second long-pending b123*I1, the 3rd long-pending c123*sqrt (P1), the 4th long-pending d123*V2, the 5th long-pending e123*I2, the 6th long-pending f123*sqrt (P2), the 7th long-pending g123*V3, the 8th long-pending h123*I3, the summation of the 9th long-pending i123*sqrt (P3) and constant j123, V1 wherein, I1, P1, V2, I2 and P2 as above formerly described in example, V3 is the voltage magnitude at model node N6m place of the result opened as the 3rd RF generator in RF generator, I3 is the current amplitude at model node N6m place of the result opened as the 3rd RF generator, and P3 is the power magnitude at model node N6m place of the result opened as the 3rd RF generator, a123, b123, c123, d123, e123, f123, g123, h123 and i123 are coefficients, and j123 is constant.
As another example, for determine the function of wafer bias be characteristic value and constant with.Characteristic value comprises amplitude, for example, and amplitude V, I, P, V1, I1, P1, V2, I2, P2, V3, I3, P3 etc.Characteristic value also comprises coefficient, for example, and coefficient a, b, c, a12, b12, c12, d12, e12, f12, a123, b123, c123, d123, e123, f123, g123, h123, i123 etc.The example of constant comprises constant d, constant g12, constant j123 etc.
It should be noted that coefficient and the constant in characteristic value in characteristic value comprise empirical model data.For example, wafer bias use wafer bias transducer is located to measure at ESC177 (Fig. 1) and is repeatedly obtained.In addition, in this example, for the number of times of measuring wafer bias, for example, by by complex voltage and electric current from one or more RF generators (, x MHz RF generator, y MHz RF generator, z MHz RF generator etc.) one or more nodes (node N3 for example, N5 etc.) via one or more models (for example transmit, impedance matching model 104, model part 173, RF mode 161, ESC model 125 (Fig. 1)) to arrive the point on path 353 (Figure 16), thus determine complex voltage and the electric current at this some place of 353 (Figure 16) along path.In addition, in this example, by the processor of host computer system 130 by statistical method (for example, PLS, the Return Law etc.) be applied to measured wafer bias and be applied to according to voltage magnitude, current amplitude and the power magnitude obtained at complex voltage and the electric current at this some place, to determine coefficient in characteristic value and the constant in characteristic value.
In various execution modes, for determining that the function of wafer bias is characterized in that: the summation to the value of the physical attribute of delegated path 353.The physical attribute in path 353 is the values that for example, draw from test data (, empirical model data etc.).The example of the physical attribute in path 353 comprises electric capacity, inductance and their combination etc. of the element on path 353.As mentioned above, along the electric capacity of the element in path 353 and/or inductive impact, use the voltage and current at the some place on path 353 that projective techniques determines by rule of thumb, and the coefficient in effect characteristics value and the constant in characteristic value then.
In some embodiments, for determining that the function of wafer bias is multinomial.
Figure 17 be method 363 for determining the flow chart at the execution mode of the wafer bias of the model Nodes of system 126 (Fig. 1).Figure 17 describes with reference to figure 1 and Figure 16.Method 363 is carried out by the processor of host computer system 130 (Fig. 1).In operation 365, the one or more communication equipments from generator system receive by host computer system 130 for one or more complex voltages and electric current, and this generator system comprises one or more in x MHz RF generator, y MHz RF generator and z MHz RF generator.For example, from communication equipment 185 (Fig. 1), be received in complex voltage and the electric current that node N3 records.As another example, from communication equipment 189 (Fig. 1), be received in complex voltage and the electric current that node N5 records.As another example, the complex voltage and the electric current that are received in complex voltage that node N3 place records and electric current and record at node N5 place.The output that it should be noted that generator system comprises one or more in the output node of node N3, N5 and z MHz RF generator.
In operation 367, one or more complex voltages and the electric current of the output based at described generator system, for example, determine at the point in the path 353 (Figure 16) (on path 353) along between impedance matching model 104 and ESC model 125 (Figure 16) complex voltage and the electric current projecting.For example, at the complex voltage of the output of described generator system and electric current via impedance matching model 104 (Figure 16) projection to determine complex voltage and the electric current at model node N4m place.As another example, part 173 (Fig. 1) projection at the complex voltage of the output of described generator system and electric current via impedance matching model 104 and RF mode 161, to determine complex voltage and the electric current of locating at model node N1m (Fig. 1).As another example, at the complex voltage of the output of described generator system and electric current via impedance matching model 104 and 161 projections of RF mode, to determine complex voltage and the electric current of locating at model node N2m (Fig. 1).As another example, at the complex voltage of the output of described generator system and electric current via impedance matching model 104, RF mode 161 and 125 projections of ESC model, to determine complex voltage and the electric current of locating at model node N6m (Fig. 1).
In operation 369, by uses project answer V & I as the input calculating of function the wafer bias at 353 the some place along path.For example, open-minded at x, y or z MHz RF generator, and all the other RF generators in x, y and z MHz RF generator are when cut out, wafer bias at this some place is determined by function, this function is the summation of the first long-pending a*V, the second long-pending b*I, the 3rd long-pending c*sqrt (P) and constant d, wherein, V is at the complex voltage of projection at this some place and the voltage magnitude of electric current, I is at the complex voltage of projection at this some place and the current amplitude of electric current, P is in the complex voltage of projection at this some place and the power magnitude of electric current, a, b and c are coefficients, and d is constant.
As another example, work as x, two RF generators in y and z MHz RF generator are open-minded, and x, when all the other the RF generators in y and z MHz RF generator cut out, the wafer bias at this some place is defined as to the first long-pending a12*V1, the second long-pending b12*I1, the 3rd long-pending c12*sqrt (P1), the 4th long-pending d12*V2, the 5th long-pending e12*I2, the summation of the 6th long-pending f12*sqrt (P2) and constant g12, wherein V1 is the voltage magnitude at this some place of the result opened as the RF generator in described two RF generators, I1 is the current amplitude at this some place of the result opened as a RF generator, P1 is the power magnitude at this some place of the result opened as a RF generator, V2 is the voltage magnitude at this some place of the result opened as the 2nd RF generator in described two RF generators, I2 is the current amplitude at this some place of the result opened as the 2nd RF generator, and P2 is the power magnitude at this some place of the result opened as the 2nd RF generator, a12, b12, c12, d12, e12, and f12 is coefficient, g12 is constant.
As another example, as all x, when y and z MHz RF generator are all opened, wafer bias at this some place is defined as to the first long-pending a123*V1, the second long-pending b123*I1, the 3rd long-pending c123*sqrt (P1), the 4th long-pending d123*V2, the 5th long-pending e123*I2, the 6th long-pending f123*sqrt (P2), the 7th long-pending g123*V3, the 8th long-pending h123*I3, the summation of the 9th long-pending i123*sqrt (P3) and constant j123, V1 wherein, I1, P1, V2, I2 and P2 as above formerly described in example, V3 is the voltage magnitude at this some place of the result opened as the 3rd RF generator in RF generator, I3 is the current amplitude at this some place of the result opened as the 3rd RF generator, and P3 is the power magnitude at this some place of the result opened as the 3rd RF generator, a123, b123, c123, d123, e123, f123, g123, h123 and i123 are coefficients, and j123 is constant.
Figure 18 is not to be by using voltage probe 332 for diagram, for example, voltage sensor etc., but by using method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17), determine the block diagram of execution mode of system 330 of the advantage of wafer bias.
Voltage probe 332 is coupled to node N1, to determine the voltage at node N1 place.In some embodiments, voltage probe 332 is coupled to another node, and for example, node N2, N4 etc., to determine the voltage at another Nodes.Voltage probe 332 comprises a plurality of circuit, such as RF splitter (splitter) circuit, filter circuit 1, filter circuit 2, filter circuit 3 etc.
In addition, x and y MHz RF generator are coupled to host computer system 334, and host computer system 334 comprises noise or signal determination module 336.But it should be noted that this module can be processor, ASIC, PLD, the software of being carried out by processor or their combination.
Voltage probe 332 measuring voltage amplitudes, host computer system 334 is used this voltage magnitude, to determine wafer bias.Module 336 determines that the voltage magnitude being recorded by voltage detector 332 is signal or noise.When determining that the voltage magnitude being recorded by voltage detector 332 is signal, host computer system 334 is determined wafer bias.
System 126 (Fig. 1) is to have cost-benefitly with respect to system 330, and saves time and energy with respect to system 330.System 330 comprises voltage probe 332, and voltage probe 332 does not need in the system that is included in 126.Node N4, the N1 or the N2 place that there is no need voltage probe to be coupling in system 126 determine wafer bias.In system 126, wafer bias is determined based on impedance matching model 104, RF mode 161 and/or ESC model 125 (Fig. 1).In addition, system 330 comprises module 336, and module 336 does not need in the system that is included in 126 yet.There is no need to take time and judge that with energy complex voltage and electric current are signal or noise.Need to not make such judgement by host computer system 130 (Fig. 1).
Figure 19 A, 19B and Figure 19 C show the execution mode of Figure 32 8,332 and 336, with explanation in the output in part 195 (Fig. 1) recording by use voltage probe (for example, node N1) voltage of locating (for example, crest voltage etc.) and by using method 102 (Fig. 2) carry out definite (for example exporting at corresponding model node, node N1m) voltage of locating (for example, crest voltage etc.) correlation between, for example, linear relationship etc.In each Figure 32 8,332 and 336, measured voltage is plotted on y axle, and the definite voltage of using method 102 is plotted on x axle.
In addition, Figure 19 A, 19B and Figure 19 C show the execution mode of Figure 33 0,334 and 338, with explanation by use wafer bias that wafer bias probe locates to record at output N6 (Fig. 1) with for example, by definite (the exporting at corresponding model node of using method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17), node N6m) correlation between the wafer bias of locating, for example, linear relationship etc.In each Figure 33 0,334 and 338, the wafer bias that uses wafer bias probe to record is plotted on y axle, and using method 340, method 351 or the definite wafer bias of method 363 are plotted on x axle.
When y and z MHz RF generator, open and x MHz RF generator while closing, voltage and wafer bias are plotted in Figure 32 8 and 330.In addition, when x and z MHz RF generator, open and y MHz RF generator while closing, voltage and wafer bias are plotted in Figure 33 2 and 334.In addition, when x and y MHz RF generator, open and z MHz RF generator while closing, voltage and wafer bias are plotted in Figure 33 6 and 338.
Figure 20 A is illustrated in the wired wafer bias that uses sensor tool (such as metering outfit, probe, transducer, wafer bias probe etc.) to record, and utilizes the figure of the execution mode that has Figure 27 6 of correlation and 278 between the error in the definite model wafer bias of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and model biasing.The wired wafer bias being plotted in Figure 27 6 is located to record at point (such as node on the upper surface 183 (Fig. 1) of the node on RF transmission line 113, ESC177 etc.), and the model being plotted in Figure 27 6 is biased in path 353(Figure 16) on corresponding model points ((Fig. 1) such as model node N4m, model node N1m, model node N2m, model node N6m) locate to be determined.Wired wafer bias is drawn along the y axle in Figure 27 6, and model biasing is drawn along the x axle in Figure 27 6.
When x MHz RF generator, open and y and z MHz RF generator while closing, wired wafer bias and model biasing are plotted in Figure 27 6.In addition, the model biasing of Figure 27 6 utilizes equation a2*V2+b2*I2+c2*sqrt (P2)+d2 to determine, wherein " * " representative is taken advantage of, and " sqrt " represents square root, " V2 " represents along path 353(Figure 16) the voltage at this some place, I2 represents the electric current at this some place, P2 represents the power at this some place, and " a2 " is coefficient, and " b2 " is coefficient, " c2 " is coefficient, and " d2 " is constant value.
Figure 27 8 has drawn error on y axle, and this error is the error in model biasing at this some place, and on x axle, has drawn the model biasing at this some place.Model error is the error in model biasing, such as variance, standard deviation etc.When x MHz RF generator, open and y and z MHz RF generator while closing, model error and model biasing are plotted in Figure 27 8.
Figure 20 B is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 28 0 of correlation and 282 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 28 0 and 282 with Figure 27 6 and 278(Figure 20 A) similarly mode draw, different, Figure 28 0 and 282 opens and x and z MHz RF generator are drawn while closing at y MHz RF generator.In addition, Figure 28 0 and the biasing of 282 model utilize equation a27*V27+b27*I27+c27*sqrt (P27)+d27 to determine, wherein " V27 " representative is along path 353(Figure 16) the voltage magnitude at some place, " I27 " representative is at the current amplitude at this some place, " P27 " representative is in the power magnitude at this some place, and " a27 " is coefficient, and " b27 " is coefficient, " c27 " is coefficient, and " d27 " is constant value.
Figure 20 C is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 28 4 of correlation and 286 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 28 4 and 286 is to be similar to Figure 27 6 and 278(Figure 20 A) mode draw, different, Figure 28 4 and 286 opens and x and y MHz RF generator are drawn while closing at z MHz RF generator.In addition, Figure 28 4 and the biasing of 286 model utilize equation a60*V60+b60*I60+c60*sqrt (P60)+d60 to determine, wherein " V60 " representative is along path 353(Figure 16) the voltage magnitude at some place, " I60 " representative is at the current amplitude at this some place, " P60 " representative is in the power magnitude at this some place, and " a60 " is coefficient, and " b60 " is coefficient, " c60 " is coefficient, and " d60 " is constant value.
Figure 20 D is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 28 8 of correlation and 290 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 28 8 and 290 is to be similar to Figure 27 6 and 278(Figure 20 A) mode draw, different, Figure 28 8 and 290 opens and z MHz RF generator draws while cutting out at x and y MHz RF generator.In addition, Figure 28 8 and the biasing of 290 model utilize equation a227*V2+b227*I2+c227*sqrt (P2)+d227*V27+e227*I27+f227*sqrt (P27)+g227 to determine, wherein " a227 ", " b227 ", " c227 ", " d227 ", " e227 " and " f227 " are coefficients, and " g227 " is constant value.
Figure 20 E is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 29 2 of correlation and 294 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 29 2 and 294 is to be similar to Figure 27 6 and 278(Figure 20 A) mode draw, different, Figure 29 2 and 294 opens and y MHz RF generator draws while cutting out at x and z MHz RF generator.In addition, Figure 29 2 and the biasing of 294 model utilize equation a260*V2+b260*I2+c260*sqrt (P2)+d20*V60+e260*I60+f260*sqrt (P60)+g260 to determine, wherein " a260 ", " b260 ", " c260 ", " d260 ", " e260 " and " f260 " are coefficients, and " g260 " is constant value.
Figure 20 F is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 29 6 of correlation and 298 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 29 6 and 298 is to be similar to Figure 27 6 and 278(Figure 20 A) mode draw, different, Figure 29 6 and 298 opens and x MHz RF generator draws while cutting out at y and z MHz RF generator.In addition, Figure 29 6 and the biasing of 298 model utilize equation a2760*V27+b2760*I27+c2760*sqrt (P27)+d2760*V60+e2760*I60+f2760*sqrt (P60)+g2760 to determine, wherein " a2760 ", " b2760 ", " c2760 ", " d2760 ", " e2760 " and " f2760 " are coefficients, and " g2760 " is constant value.
Figure 20 G is illustrated in wired wafer bias, utilizes the figure of the execution mode that has Figure 30 2 of correlation and 304 between the definite model biasing of method 340 (Figure 13), method 351 (Figure 15) or method 363 (Figure 17) and the error in model biasing.Figure 30 2 and 304 is to be similar to Figure 27 6 and 278(Figure 20 A) mode draw, different, Figure 30 2 and 304 draws when x, y and z MHz RF generator are opened.In addition, Figure 30 2 and the biasing of 304 model utilize equation a22760*V2+b22760*I2+c22760*sqrt (P2)+d22760*V60+e22760*I60+f22760*sqrt (P60)+g22760*V27+h22760*I27+i22760*sqrt (P27)+j22760 to determine, wherein " a22760 ", " b22760 ", " c22760 ", " d22760 ", " e22760 ", " f22760 " " g22760 ", " h22760 " and " i22760 " are coefficients, and " j22760 " is constant value.
Figure 21 is the block diagram of the execution mode of host computer system 130.Host computer system 130 comprises processor 168, storage HU162, input HU380, output HU382, I/O (I/O) interface 384, I/O interface 386, network interface controller (NIC) 388 and bus 392.Processor 168, storage HU162, input HU380, output HU382, I/O interface 384, I/O interface 386 and NIC388 intercouple by bus 392.The example of input HU380 comprises mouse, keyboard, stylus etc.The example of output HU382 comprises display, loud speaker or their combination.Display can be liquid crystal display, light emitting diode indicator, cathode ray tube, plasma scope, etc.The example of NIC388 comprises network interface unit, network adapter etc.
The compatible interface providing being coupled between the hardware of this interface is provided the example of I/O interface.For example, I/O interface 384 converts the signal that is received from input HU380 to form, amplitude and/or speed with bus 392 compatibilities.Again for example, I/O interface 386 converts the signal that is received from bus 392 and the form of exporting HU382 compatibility, amplitude and/or speed to.
It should be noted that in some embodiments, wafer bias is used to determine the clamp voltage that workpiece 131 (Fig. 1) is clamped to ESC177 (Fig. 1).For example, when wafer bias is not when plasma chamber 175 (Fig. 1) exists, two electrodes of ESC177 inside have opposite polarity matching voltage, so that workpiece 131 is clamped to ESC177.In this example, when wafer bias is present in plasma chamber 175 when interior, the voltage that offers two electrodes has different amplitudes, to compensate existing wafer bias.In various execution modes, the biasing that wafer bias is located at ESC177 (Fig. 1) for compensation.
Be also noted that, than using voltage, use three parameters (for example, the phase place between current amplitude, voltage magnitude and electric current and voltage etc.) to be identified for compensation and can determine better wafer bias at the wafer bias of the biasing at ESC177 place.For example, compare with the relation between RF voltage and nonlinear plasma state (regime), use wafer bias and the nonlinear plasma state (regime) that three calculation of parameter go out to there is stronger correlation.As another example, use the wafer bias of three calculation of parameter more accurate than using the definite wafer bias of voltage probe.
Figure 22 is the schematic diagram of execution mode of determining the function of ion energy for explanation from wafer bias and peak amplitude.Ion energy definite is the processor 168(Figure 21 by host computer system 130) carry out.For example, this ion energy be calculated as coefficient " C1 " be multiplied by wafer bias at model node N6m place (for example, modeled biasing etc.) and coefficient " C2 " be multiplied by one or more RF generators voltage peak amplitude and.The example of coefficient " C1 " comprises negative real number, and the example of coefficient " C2 " comprises arithmetic number.
In various execution modes, coefficient " C1 " is arithmetic number.In various execution modes, coefficient " C2 " is negative real number.Coefficient " C1 " and " C2 ", wafer bias and peak amplitude are stored in storage HU162 (Figure 21).The example of peak amplitude comprises peak-peak amplitude and zero-peak amplitude.
In some embodiments, for the peak amplitude of determining ion energy by the processor 168 of host computer system 130 from model node N6m(Fig. 1) complex voltage and electric current obtain.In various execution modes, for determining that the peak amplitude of ion energy is from model node N2m or model node N1m or model node N4m(Fig. 1 by the processor 168 of host computer system 130) complex voltage and electric current obtain.
In various execution modes, for calculating the peak amplitude of ion energy, by one end, be coupled to node N1, node N2(Fig. 1) or node N6(Fig. 1) and the other end voltage and current probe measurement of being coupled to processor 168.The voltage and current probe that is coupled to node N1, node N2 or node N6 can be distinguished between x and the frequency of y MHz RF generator.
In some embodiments, for determining that peak amplitude and the wafer bias of ion energy is all at model Nodes.For example,, for determining that the peak amplitude of ion energy is from obtaining at complex voltage and the electric current of model node N6m, for determining that the wafer bias of ion energy calculates at model node N6m place.Again for example, for determining that the peak amplitude of ion energy is from obtaining at complex voltage and the electric current of model node N2m, for determining that the wafer bias of ion energy calculates at model node N2m place.
In various execution modes, for determining that the peak amplitude of ion energy is to obtain from complex voltage and the electric current of the first model Nodes, definite at the second model Nodes for determining the wafer bias of ion energy, rather than determine at the first model Nodes.For example,, for determining that the peak amplitude of ion energy is from obtaining at complex voltage and the electric current of model node N6m, for determining that the wafer bias of ion energy calculates at model node N2m place.Again for example, for determining that the peak amplitude of ion energy is from obtaining at complex voltage and the electric current of model node N2m, for determining that the wafer bias of ion energy calculates at model node N6m place.
In some embodiments, for calculating the peak amplitude of ion energy, be the voltage of for example, locating in one or more outputs (, node N3, node N5 etc. (Fig. 1)) of one or more x and y MHz RF generator.In using the execution mode of a plurality of RF generators, for example, in x and two execution modes that all use of y MHz RF generator, by the voltage and current probe measurement crest voltage that is coupled to node N3 and processor 168, by the voltage and current probe measurement crest voltage that is coupled to node N5 and processor 168, and processor 168 calculates the algebraic combination (for example, and, mean value etc.) of the crest voltage recording in output, to calculate for calculating the peak amplitude of ion energy.The example that is coupled to any one the voltage and current probe in node N3 and N5 comprises NIST probe.
In some embodiments, not to use peak amplitude, but use root-mean-square amplitude.
In various execution modes, the processor 168 of host computer system 130 determines ion energy as wafer bias and the function that is used for calculating the RF voltage (as Vx, Vy, Vz etc.) of wafer bias.For example, the processor of host computer system 130 determines that ion energy is:
Ei=(-1/2)Vdc+(1/2)Vpeak
Wherein Ei is ion energy, and Vdc is wafer bias current potential, and Vpeak is for calculating zero-crest voltage of wafer bias current potential.Vpeak is crest voltage, for example, and voltage Vx, Vy or Vz.
In various execution modes, ion energy is the energy of the ion that forms in the plasma of plasma chamber.
In some embodiments, when a plurality of RF generators are opened, the Vpeak that is used for calculating wafer bias has the RF generator of low-limit frequency in all RF generators.For example, Vpeak equals Vx.In various execution modes, when a plurality of RF generators are opened, the Vpeak that is used for calculating wafer bias is the RF generator with highest frequency.For example, Vpeak equals Vz.In various execution modes, when a plurality of RF generators are opened, the Vpeak that is used for calculating wafer bias is the RF generator with the frequency between low-limit frequency and highest frequency.For example, Vpeak equals Vy.In some embodiments, Vpeak is the crest voltage of statistical value (for example, intermediate value, mean value etc.) of the peak value RF voltage of the RF generator opened.The ion energy calculating by this way does not need to measure Vpeak with expensive voltage probe equipment, does not need to measure wafer bias with bias compensation circuit yet.May be inaccurate for measuring the voltage probe of Vpeak.An example of bias compensation circuit comprises carborundum pin.Use the definite ion energy of various execution mode of the present disclosure to cause low measurement time between failures (MTBF).
It should be noted in the discussion above that in some embodiments, the value of ion energy is stored in storage HU162.
It is also noted that, although aforementioned operation is described with reference to parallel-plate plasma chamber (such as capacitance coupling plasma chamber etc.), but in some embodiments, aforementioned operation can be applicable to the plasma chamber of other type, the plasma chamber that for example comprises inductively coupled plasma (ICP) reactor, transformer coupled plasma (TCP) reactor, conductor instrument, dielectric instrument, the plasma chamber that comprises electron cyclotron resonace (ECR) reactor, etc.For example, x MHz RF generator and y MHz RF generator are coupled in the indoor inductor of ICP plasma.
Should also be noted that, although operation is above described to be carried out by the processor of host computer system 130 (Fig. 1), but in some embodiments, operation can be carried out or be carried out by a plurality of processors of a plurality of host computer systems by one or more processors of host computer system 130.
It should be noted that, although aforementioned embodiments relates to, provide RF signal to ESC177(Fig. 1 and 18) bottom electrode and ESC192(Figure 11) bottom electrode and relate to make top electrode 179 and 264(Fig. 1 and 11) ground connection, but in some embodiments, RF signal is provided in top electrode 179 and 264, simultaneously ESC177 and 163 bottom electrode ground connection.
Execution mode described herein can be implemented by various computer system configurations, computer system configurations comprises hand-hold type hardware cell, microprocessor system, based on consumption electronic product microprocessor or programmable, microcomputer, mainframe computer, etc.Described execution mode also can be implemented in distributed computing environment (DCE), and in distributed computing environment (DCE), task is carried out by the teleprocessing hardware cell linking by network.
On the basis of above-mentioned execution mode, should be appreciated that described execution mode can adopt the various computer implemented operation that relates to the data that are stored in computer system.These operations are the operations that need the physical manipulation of physical quantity.Any one in the operation of a part for the described execution mode of formation described herein is useful machine operation.Described execution mode also relates to for carrying out hardware cell or the device of these operations.Described device can be special-purpose computer special configuration.When being defined as special-purpose computer, this computer also can be carried out other processing, program execution or the routine that is not private part, still can carry out dedicated operations simultaneously.In some embodiments, described operation can be by general-purpose computer processes, and this all-purpose computer is stored in computer storage, buffer memory or one or more computer program of obtaining by network optionally activates or configures.When data obtain by network, these data can for example, be processed by other computer on this network (cloud computing resources).
One or more execution mode also can be made as the computer-readable code on nonvolatile computer-readable medium.Nonvolatile computer-readable medium is data-storable arbitrary data storage hardware unit, and these data later can be by computer system reads.The example of nonvolatile computer-readable medium comprises hard disk drive, network attached storage (NAS), ROM, RAM, CD ROM(CD-ROM), recordable CD(CD-R), erasable CD(CD-RW), tape and other optics and non-optical data storage hardware unit.Nonvolatile computer-readable medium can comprise the computer-readable tangible medium being distributed in network coupled computer system, makes computer-readable code be stored and carry out with distribution mode.
Although the operation of the method in the flow chart of Fig. 2, Figure 13, Figure 15 and Figure 17 is above described with particular order, but be to be understood that other house-keeping can carry out between operation, or operation can be adjusted and make them occur in the slightly different time, or can be distributed on and allow occurring to process in the system of operation to processing the relevant various time intervals, as long as the processing of overlap-add operation is performed in the way you want.
One or more feature of any execution mode can but not deviate from the scope of describing in the various execution modes described in the disclosure with one or more Feature Combination of any other execution mode.
Although describe to a certain extent aforementioned embodiments in detail for the clear object of understanding, it is evident that, can implement within the scope of the appended claims some change and modification.Therefore, embodiments of the present invention should be considered to be illustrative rather than restrictive, and these execution modes are not limited to details given in this article, but can in the scope of claims and equivalent, modify.

Claims (23)

1. for determining a method for ion energy, the method comprises:
Be identified in the first complex voltage and electric current when described RF generator is coupled to plasma chamber via impedance matching circuit that the outgoing position of radio frequency (RF) generator records, the output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to RF transmission line;
Based on defined electric component in described impedance matching circuit, generate impedance matching model, described impedance matching model has input and output, the described input of described impedance matching model receives described the first complex voltage and electric current, and described impedance matching model has one or more elements;
Transmit described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current;
Obtain crest voltage;
Based on described the second complex voltage and electric current, determine wafer bias; And
Based on described wafer bias and described crest voltage, determine described ion energy.
2. method according to claim 1, the current amplitude of voltage magnitude, described second complex voltage and electric current and the power magnitude of described second complex voltage and electric current of wherein said wafer bias based on described the second complex voltage and electric current,
Wherein determine that described wafer bias comprises:
Based on described voltage magnitude and described current amplitude, calculate described power magnitude; And
Calculate first long-pending, second long-pending, the 3rd long-pending and constant and, wherein said first long-pending be the long-pending of described voltage magnitude and the first coefficient, described second long-pending be the long-pending of described current amplitude and the second coefficient, the described the 3rd long-pending be the long-pending of the square root of described power magnitude and the 3rd coefficient.
3. method according to claim 1, wherein said RF generator comprises the RF generator of 2 megahertzes, the RF generator of 27 megahertzes, or the RF generator of 60 megahertzes.
4. method according to claim 1, it further comprises:
Based on defined circuit block in described RF transmission line, generate RF mode, described RF mode has input and output, the output of described impedance matching model is coupled in the input of described RF mode, described RF mode has part, and wherein said wafer bias is determined in the output of the part of described RF mode.
5. method according to claim 1, it further comprises:
Based on defined electric component in described RF transmission line, generate RF mode, described RF mode has input and output, the output of described impedance matching model is coupled in the input of described RF mode, and wherein said wafer bias is determined in the output of described RF mode.
6. method according to claim 5, wherein, the electric component of described RF transmission line comprises the combination of capacitor, inductor or capacitor and inductor, described RF mode comprises one or more elements, wherein, the described element of described RF mode has the feature with the feature similarity of the electric component of described RF transmission line.
7. according to the process of claim 1 wherein that received described the first complex voltage and electric current record in the output of described RF generator with voltage and current probe, described voltage and current probe is according to default formula calibration.
8. method according to claim 7, wherein said default formula is standard.
9. method according to claim 8, wherein, wherein said standard is USA National Institute of Standard and Technology (NIST) standard, thereby wherein said voltage and current probe and open circuit, short circuit or load coupling meet NIST standard to calibrate described voltage and current probe.
10. method according to claim 1, wherein said the second composite voltage and electric current comprise the phase place between magnitude of voltage, current value and this magnitude of voltage and this current value.
11. methods according to claim 1, the described element of wherein said impedance matching model comprises the combination of capacitor, inductor or capacitor and inductor, the electric component of wherein said impedance matching circuit comprises the combination of capacitor, inductor or capacitor and inductor, and the described element of wherein said impedance matching model has the feature with the feature similarity of the described electric component of described impedance matching circuit.
12. methods according to claim 1, wherein said wafer bias is used in system, and wherein said system comprises RF transmission line, but is not included in the voltage probe on described RF transmission line.
13. methods according to claim 1, it also comprises:
Electric component based on limiting in described RF transmission line generates RF mode, and described RF mode has input and output, and the described output of described impedance matching model is coupled in the described input of described RF mode; And
The feature of the electrostatic chuck based on described plasma chamber generates electrostatic chuck (ESC) model, described ESC model has input, the described output of described RF mode is coupled in the described input of described ESC model, and wherein, described wafer bias is determined in the described output of described ESC model.
14. methods according to claim 1, wherein transmit from the described input of described impedance matching model the described output that arrives described impedance matching model by described one or more elements by described the first complex voltage and electric current and comprise to determine the second complex voltage and electric current:
The described input that is coupling in described impedance matching model based on described the first complex voltage and electric current and described impedance matching model and the feature of the one or more elements between intermediate node are determined middle complex voltage and the electric current in the described intermediate node in described impedance matching model; And
The feature of the one or more elements based between complex voltage in the middle of described and the described output that is coupling in described intermediate node and described impedance matching model of electric current and described impedance matching model is determined described the second complex voltage and electric current.
15. methods according to claim 1, wherein said RF mode comprises RF tunnel model and RF band model, described RF tunnel model and the coupling of described RF band model.
16. methods according to claim 1, wherein determine that described ion energy comprises:
First of design factor and described wafer bias amasss;
Second of design factor and described crest voltage amasss; And
Calculate described first long-pending and described second long-pending and.
17. methods according to claim 1, wherein obtain described crest voltage and comprise from described the second complex voltage and electric current and obtain described crest voltage.
18. methods according to claim 17, wherein obtain described crest voltage and comprise the measured value that receives described crest voltage.
19. 1 kinds of plasma systems for definite ion energy, it comprises:
For generation of the RF generator of radio frequency (RF) signal, described RF generator is associated with voltage and current probe, and wherein said voltage and current probe is configured to measure the first complex voltage and the electric current at the outgoing position of described RF generator;
Be coupled to the impedance matching circuit of described RF generator;
Via RF transmission line, be coupled to the plasma chamber of described impedance matching circuit, the output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to described RF transmission line; And
Be coupled to the processor of described RF generator, described processor is configured to:
Identify described the first complex voltage and electric current;
Based on defined electric component in described impedance matching circuit, generate impedance matching model, described impedance matching model has input and output, the described input of described impedance matching model receives described the first complex voltage and electric current, and described impedance matching model has one or more elements;
Transmit described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current;
Obtain crest voltage;
Based on described the second complex voltage and electric current, determine wafer bias; And
Based on described wafer bias and described crest voltage, determine described ion energy.
20. plasma systems according to claim 19, wherein, described RF generator is configured to operate under the frequency of 2 megahertzes or 27 megahertzes or 60 megahertzes.
21. plasma systems according to claim 19, wherein said processor is configured to:
First of design factor and described wafer bias amasss;
Second of design factor and described crest voltage amasss; And
Calculate described first long-pending and described second long-pending and.
22. 1 kinds of computer systems for definite ion energy, described computer system comprises:
Processor, it is configured to:
Be identified in the first complex voltage and electric current when described RF generator is coupled to plasma chamber via impedance matching circuit that the outgoing position of radio frequency (RF) generator records, the output that described impedance matching circuit has the input of the described output of being coupled to described RF generator and is coupled to RF transmission line;
Based on defined electric component in described impedance matching circuit, generate impedance matching model, described impedance matching model has input and output, the described input of described impedance matching model receives described the first complex voltage and electric current, and described impedance matching model has one or more elements;
Transmit described the first complex voltage and the electric current described element by described impedance matching model to determine the second complex voltage and electric current;
Obtain crest voltage;
Based on described the second complex voltage and electric current, determine wafer bias; And
Based on described wafer bias and described crest voltage, determine described ion energy; With
Be coupled to the memory device of described processor, described memory device is configured to store described ion energy.
23. computer systems according to claim 22, wherein said processor is configured to:
First of design factor and described wafer bias amasss;
Second of design factor and described crest voltage amasss; And
Calculate described first long-pending and described second long-pending and.
CN201410097194.1A 2013-03-15 2014-03-17 The ion energy for determining to associate with plasma system using model Active CN104051214B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810106696.4A CN108447759B (en) 2013-03-15 2014-03-17 Method and system for determining ion energy associated with a plasma system using a model

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361799969P 2013-03-15 2013-03-15
US61/799,969 2013-03-15
US14/184,639 US9842725B2 (en) 2013-01-31 2014-02-19 Using modeling to determine ion energy associated with a plasma system
US14/184,639 2014-02-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201810106696.4A Division CN108447759B (en) 2013-03-15 2014-03-17 Method and system for determining ion energy associated with a plasma system using a model

Publications (2)

Publication Number Publication Date
CN104051214A true CN104051214A (en) 2014-09-17
CN104051214B CN104051214B (en) 2018-03-13

Family

ID=51503908

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201410097194.1A Active CN104051214B (en) 2013-03-15 2014-03-17 The ion energy for determining to associate with plasma system using model
CN201810106696.4A Active CN108447759B (en) 2013-03-15 2014-03-17 Method and system for determining ion energy associated with a plasma system using a model

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201810106696.4A Active CN108447759B (en) 2013-03-15 2014-03-17 Method and system for determining ion energy associated with a plasma system using a model

Country Status (3)

Country Link
KR (1) KR102162429B1 (en)
CN (2) CN104051214B (en)
TW (1) TWI647735B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150301100A1 (en) * 2014-04-21 2015-10-22 Lam Research Corporation Using modeling for identifying a location of a fault in an rf transmission system for a plasma system
CN107154334A (en) * 2016-03-04 2017-09-12 朗姆研究公司 Reduce the system and method for the power reflected towards high-frequency RF generator
CN107293467A (en) * 2016-04-13 2017-10-24 朗姆研究公司 Reduce the system and method for reflection power using radio frequency value during state changes

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170330764A1 (en) * 2016-05-12 2017-11-16 Lam Research Corporation Methods and apparatuses for controlling transitions between continuous wave and pulsing plasmas
US10734195B2 (en) * 2017-06-08 2020-08-04 Lam Research Corporation Systems and methods for transformer coupled plasma pulsing with transformer coupled capacitive tuning switching
US11476145B2 (en) * 2018-11-20 2022-10-18 Applied Materials, Inc. Automatic ESC bias compensation when using pulsed DC bias
CN114217101B (en) * 2021-10-30 2023-06-13 荣耀终端有限公司 Radio frequency test probe structure and radio frequency test system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5971591A (en) * 1997-10-20 1999-10-26 Eni Technologies, Inc. Process detection system for plasma process
US20060278608A1 (en) * 2003-05-16 2006-12-14 Hoffman Daniel J Method of determining plasma ion density, wafer voltage, etch rate and wafer current from applied bias voltage and current
CN101489345A (en) * 2008-01-14 2009-07-22 北京北方微电子基地设备工艺研究中心有限责任公司 Radio frequency automatic impedance matching method and radio frequency automatic impedance matcher
CN101989524A (en) * 2009-08-03 2011-03-23 北京北方微电子基地设备工艺研究中心有限责任公司 Impedance matcher and plasma processing equipment
CN102652266A (en) * 2010-12-07 2012-08-29 朗姆研究公司 Plasma processing system control based on RF voltage

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3176128B2 (en) * 1992-06-25 2001-06-11 株式会社ダイヘン Output voltage measuring device for impedance matching device
US6449568B1 (en) * 1998-02-27 2002-09-10 Eni Technology, Inc. Voltage-current sensor with high matching directivity
US6441620B1 (en) * 2000-06-20 2002-08-27 John Scanlan Method for fault identification in a plasma process
US6873114B2 (en) * 2002-09-26 2005-03-29 Lam Research Corporation Method for toolmatching and troubleshooting a plasma processing system
US7901952B2 (en) * 2003-05-16 2011-03-08 Applied Materials, Inc. Plasma reactor control by translating desired values of M plasma parameters to values of N chamber parameters
JP5150053B2 (en) * 2006-02-03 2013-02-20 株式会社日立ハイテクノロジーズ Plasma processing equipment
CN103456591B (en) * 2012-05-31 2016-04-06 中微半导体设备(上海)有限公司 The inductively coupled plasma process chamber of automatic frequency tuning source and biased radio-frequency power supply

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5971591A (en) * 1997-10-20 1999-10-26 Eni Technologies, Inc. Process detection system for plasma process
US20060278608A1 (en) * 2003-05-16 2006-12-14 Hoffman Daniel J Method of determining plasma ion density, wafer voltage, etch rate and wafer current from applied bias voltage and current
CN101489345A (en) * 2008-01-14 2009-07-22 北京北方微电子基地设备工艺研究中心有限责任公司 Radio frequency automatic impedance matching method and radio frequency automatic impedance matcher
CN101989524A (en) * 2009-08-03 2011-03-23 北京北方微电子基地设备工艺研究中心有限责任公司 Impedance matcher and plasma processing equipment
CN102652266A (en) * 2010-12-07 2012-08-29 朗姆研究公司 Plasma processing system control based on RF voltage

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150301100A1 (en) * 2014-04-21 2015-10-22 Lam Research Corporation Using modeling for identifying a location of a fault in an rf transmission system for a plasma system
US10950421B2 (en) * 2014-04-21 2021-03-16 Lam Research Corporation Using modeling for identifying a location of a fault in an RF transmission system for a plasma system
CN107154334A (en) * 2016-03-04 2017-09-12 朗姆研究公司 Reduce the system and method for the power reflected towards high-frequency RF generator
CN107154334B (en) * 2016-03-04 2019-03-19 朗姆研究公司 Reduce the system and method for the power reflected towards high-frequency RF generator
CN107293467A (en) * 2016-04-13 2017-10-24 朗姆研究公司 Reduce the system and method for reflection power using radio frequency value during state changes
CN107293467B (en) * 2016-04-13 2019-05-28 朗姆研究公司 Reduce the system and method for reflection power using radio frequency value during state transformation

Also Published As

Publication number Publication date
KR102162429B1 (en) 2020-10-07
CN108447759A (en) 2018-08-24
TWI647735B (en) 2019-01-11
CN104051214B (en) 2018-03-13
KR20140113602A (en) 2014-09-24
CN108447759B (en) 2020-07-24
TW201503216A (en) 2015-01-16

Similar Documents

Publication Publication Date Title
CN104051215A (en) Determining A Malfunctioning Device in A Plasma System
CN103984790A (en) Using modeling to determine wafer bias associated with a plasma system
US10707056B2 (en) Using modeling to determine ion energy associated with a plasma system
CN104051214A (en) Using Modeling to Determine Ion Energy Associated with A Plasma System
KR102438859B1 (en) System, method and apparatus for refining rf transmission system models
CN103871810B (en) Method and system for determining value of variable on radio frequency (RF) transmission model
CN105006419B (en) Location of fault in the RF Transmission systems of plasma system is determined using model
US9508529B2 (en) System, method and apparatus for RF power compensation in a plasma processing system
KR20160046748A (en) System, method and apparatus for improving accuracy of rf transmission models for selected portions of an rf transmission path
JP2014195044A5 (en)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant