CN104036812A - Comparator with improved time constant - Google Patents
Comparator with improved time constant Download PDFInfo
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- CN104036812A CN104036812A CN201310067310.0A CN201310067310A CN104036812A CN 104036812 A CN104036812 A CN 104036812A CN 201310067310 A CN201310067310 A CN 201310067310A CN 104036812 A CN104036812 A CN 104036812A
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- output terminal
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Abstract
The invention provides a comparator with an improved time constant and an apparatus used for comparing input of differential input signals. The apparatus comprises a CMOS read amplifier (which is provided with a first input terminal, a second input terminal, a first output terminal and a second output terminal), a first output circuit (which is provided with a first load capacitor), a second output circuit (which is provided with a second load capacitor) and an isolation circuit. The isolation circuit is connected with and arranged between the first output terminal of the CMOS read amplifier and the first output circuit and connected with and arranged between the second output terminal of the CMOS read amplifier and the second output circuit. The isolation circuit isolates the first and second load capacitors from the CMOS read amplifier.
Description
Technical field
Relate generally to comparer of the present invention, and relate more specifically to the comparer based on read-out amplifier.
Background technology
Comparer is non-linear circuit, and it is generally used for detecting the sign difference between two or more signals, and in many application analytic signals, in storer and analog to digital converter (ADC).For example, the 50(of read-out amplifier shown in Fig. 1 for example, it can be as the comparer in memory application).Particularly, this read-out amplifier 50 is the cmos circuits as regeneration time clock comparer.It comprises the PMOS of X-bracing and nmos pass transistor Q2 conventionally to Q5, and the input of the difference of nmos pass transistor Q7 and Q8 is right, and clock circuit (it generally includes PMOS transistor Q1 and Q6 and nmos pass transistor Q9).When this clock signal clk is logic low potential or " 0 ", output terminal R and S can be precharged to the voltage on power supply rail VDD, when clock signal clk is logic high potential or " 1 ", in the output valve of terminal R and S, according to the input value at input end INM and INP, resolve so.If the voltage on input end INP is greater than the voltage on terminal INM, terminal S and R are resolved respectively as " 1 " and " 0 " so; On the contrary, when the voltage on the input end on INP is less than the voltage on terminal INM, terminal S and R resolve to respectively " 0 " and " 1 ".In addition, transistor Q9 connects differential pair Q7 and Q8 and disconnect with earth potential (power supply rail) according to clock signal clk.
Being used for describing read-out amplifier 50 behavioural traits is its " time constants ", the correlativity of the propagation delay (or " clock postpones to Q ") in its indication input amplitude.Conventionally, because the magnitude of the difference of voltage between terminal INM and INP is less, therefore exist longer delay for resolving the value on terminal R and S.This relation can be represented as follows:
(1)T
PROP=max(t
FIXED,t
FIXED-τ*ln(|V
IN|))
T wherein
pROPpropagation delay, t
fIXEDbe that the fixedly comparer for example, with voltage on () change in process, temperature and power supply rail VDD relevant postpones, τ is time constant, and | V
iN| be the value (it typically is differential signal) of the voltage difference between end INM and INP.Conventionally, equation (1) is applicable to about 100mV or the signal of magnitude still less, once and this difference enough large, propagation delay T
pROPbe saturated to fixedly comparer and postpone t
fIXED.Therefore,, for some application, expectation reduces this propagation delay T
pROPthereby, for low amplitude value signal, resolve quickly comparative result.
Some examples of conventional system are: U.S. Patent number 4,274,013; U.S. Patent number 4,604,533; U.S. Patent number 5,627,789; U.S. Patent number 5,901,088; U.S. Patent number 7,688,125; " A4mW3-tap10Gb/s Decision Feedback Equalizer " 2011IEEE54th International Midwest Symposium on Circuits and Systems (MWSCAS) with people such as Payandehnia, September23,2011, pp.1-4.
Summary of the invention
Therefore, embodiments of the invention provide device.This device comprises CMOS read-out amplifier, and it has first input end, the second input end, the first output terminal and the second output terminal; The first output circuit, has the first load capacitance; The second output circuit, has the second load capacitance; And buffer circuit, it is connected between first output terminal and the first output circuit of CMOS read-out amplifier, and it is connected between the second output terminal of CMOS read-out amplifier and the second output terminal of CMOS read-out amplifier, wherein buffer circuit is by the first and second load capacitances and the isolation of CMOS read-out amplifier.
According to embodiments of the invention, the first and second output circuits further comprise respectively the first and second phase inverters.
According to embodiments of the invention, CMOS read-out amplifier is controlled by clock signal, and wherein this buffer circuit further comprises: pre-charge circuit, and it is coupled to the first and second phase inverters, and is controlled by clock signal; With the first isolated component, it is connected between first output terminal and the first phase inverter of CMOS read-out amplifier; With the second isolated component, it is connected between second output terminal and the second phase inverter of CMOS read-out amplifier.
According to embodiments of the invention, this pre-charge circuit comprises further: the first MOS transistor, and it is coupled to the first phase inverter in its drain electrode; With the second MOS transistor, it is coupled to the second phase inverter in its drain electrode.
According to embodiments of the invention, the first and second isolated components comprise respectively the first and second resistors further.
According to embodiments of the invention, this clock signal further comprises the first clock signal, and wherein the first and second isolated components further comprise respectively the first and second switches by second clock signal controlling, and there is the non-overlapped cycle between the activation of the CMOS read-out amplifier of being realized by clock signal and the activation of the first and second switches of being realized by second clock signal.
According to embodiments of the invention, this read-out amplifier further comprises: clock circuit, thus it is configured reception the first clock signal; Difference input transistors pair, thus it is configured reception differential input signal; First pair of X-bracing transistor, it is connected to difference input transistors pair; With second pair of X-bracing transistor, it is connected to first pair of X-bracing transistor.
According to embodiments of the invention, provide device.This device comprises: AFE (analog front end) (AFE); Analog to digital converter (ADC), it is coupled to AFE, and wherein AFE has a plurality of dispensers (slicer), and wherein each dispenser comprises: CMOS read-out amplifier, it has first input end, the second input end, the first output terminal and the second output terminal; The first output circuit, has the first load capacitance; The second output circuit, it has the second load capacitance; Buffer circuit, it is connected between first output terminal and the first output circuit of CMOS read-out amplifier, and it is connected between the second output terminal of CMOS read-out amplifier and the second output terminal of CMOS read-out amplifier, wherein buffer circuit is by the first and second load capacitances and the isolation of CMOS read-out amplifier; And decision zeedback equalizer (DFE), it is coupled to ADC.
According to embodiments of the invention, provide device.This device comprises serializer; Transmitter, it is coupled to this serializer; Communication media, it is coupled to this transmitter; Receiver, it has: AFE; ADC, it is coupled to AFE, and wherein ADC has a plurality of dispensers, and wherein each dispenser comprises: read-out amplifier, it has: the first power supply rail; The second power supply rail; The first output terminal; The second output terminal; X-bracing PMOS transistor pair, its each be coupled to the first and second output terminals and be coupled to the first power supply rail; X-bracing nmos pass transistor pair, its each be coupled to the first and second output terminals; Nmos pass transistor difference input is right, its each be connected to communication channel and X-bracing nmos pass transistor pair; The first clock nmos pass transistor, it is connected between the first power supply rail and the first output terminal, thereby and its be configured receive clock signal; Second clock nmos pass transistor, it is connected between the first power supply rail and the second output terminal, thereby and its be configured receive clock signal; With the 3rd clock nmos pass transistor, its be connected in nmos pass transistor difference input to and the second power supply rail between, thereby and its be configured receive clock signal; The first output circuit, it has the first load capacitance; The second output circuit, it has the second load capacitance; Buffer circuit, it is connected between first output terminal and the first output circuit of read-out amplifier, and it is connected between the second output terminal of read-out amplifier and the second output terminal of read-out amplifier, wherein buffer circuit is by the first and second load capacitances and read-out amplifier isolation; And DFE, it is coupled to ADC; And deserializer, it is coupled to DFE.
According to embodiments of the invention, buffer circuit further comprises: pre-charge circuit, and it is coupled to the first and second phase inverters, and is controlled by clock signal; With the first isolated component, it is connected between first output terminal and the first phase inverter of read-out amplifier; With the second isolated component, it is connected between second output terminal and the second phase inverter of read-out amplifier.
According to embodiments of the invention, this pre-charge circuit comprises further: the first precharge PMOS transistor, and it is coupled to the first phase inverter in its drain electrode; With the second precharge PMOS transistor, it is coupled to the second phase inverter in its drain electrode.
In order better to understand detailed description of the present invention below, above-mentioned device of the present invention and the technological merit summarized quite widely.Extra feature of the present invention and advantage can be described hereinafter, and it has formed the theme of claim of the present invention.It should be appreciated by those skilled in the art that disclosed concept and specific embodiment can easily be utilized as the basis of revising or be designed for other structures of carrying out the identical object of the present invention.Those skilled in the art also should be realized that, these equivalent constructions do not depart from spirit of the present invention and the protection domain proposing in claim.
Accompanying drawing explanation
In order to understand more completely the present invention and advantage thereof, with reference now to the following description associated with accompanying drawing, wherein:
Fig. 1 is the diagram of the example of conventional cmos read-out amplifier;
Fig. 2 is according to the diagram of the example of the system of embodiments of the invention;
Fig. 3 is the diagram of example of at least a portion ADC of Fig. 2;
Figure 4 and 5 are diagrams of example of the dispenser of Fig. 3; With
Fig. 6 is the example of sequential chart of the dispenser of Fig. 5.
Embodiment
With reference now to accompanying drawing,, wherein for the sake of clarity described element do not need to draw in proportion and wherein in several figure similar or similar element by same reference numbers, indicated.
As mentioned above, expectation reduces propagation delay T in some applications
pROP.This can be by regulating timeconstantτ to complete.The example of this application is the dispenser based on read-out amplifier in serializer/de-serializers (SERDES) system 100 that can find out from Fig. 2 and 3.Be in operation, serializer 102 is converted to serial data stream by parallel data stream.Then, this serial data is launched device 104 and it typically is communication media by channel 106(, as twisted-pair feeder) be transmitted into receiver 108.Then the AFE (analog front end) of receiver 108 (AFE) 112 can be from channel 106 restoring signals, and then this signal can it adopt dispenser 202-1 to 202-N by ADC114(conventionally, and it can be several ADC) digitizing.Then DFE116 filtering and balanced digitized signal (that is, compensation intersymbol interference or ISI), and deserializer 110 makes the output parallelization from DFE116.In this system 100, dispenser 202-1 is used the comparer based on read-out amplifier to 202-N, so that dispenser can be benefited from the adjustment of timeconstantτ.
Get back to Fig. 1, timeconstantτ is relevant with electric capacity.Particularly, this constant τ and the transconductance g to Q5 divided by transistor Q2
mload capacitance C
lOAD(that is, τ α C
lOAD/ g
m) proportional.This load capacitance C
lOADthe intrinsic-OR internal capacitance C of read-out amplifier 50 normally
iNTwith the external capacitive C on terminal R and S
eXTand.In order to reduce timeconstantτ, should reduce load capacitance C
lOAD, and increase transconductance g
m.Increase transconductance g
mcan mean that transistor Q1 should increase size to Q9, but the increase of size is limited, because internal capacitance C
iNTproportional to the size of Q9 with transistor Q1.Therefore, only increase transistor Q1 and can not obtain the effect of wanting to the size of Q9, so dispenser 202-1 adopts the comparer based on read-out amplifier, wherein external capacitive C to 202-N
eXTwith internal capacitance C
iNTdisconnect or isolation, so that load capacitance C
lOADbe approximately equal to internal capacitance C
iNT.
In Fig. 4, can find out that this dispenser 202-1 is to the example (it is 202-A by label) of 202-N.As shown in this example, external capacitive C
eXTcome from the output circuit load of (it is comprised of phase inverter 206 and 208 conventionally in this example).Buffer circuit 204-A is connected between terminal R and S and phase inverter 206 and 208.This buffer circuit 204-A is comprised of pre-charge circuit (being PMOS transistor Q10 and Q11) and resistor R1 and R2 conventionally.This pre-charge circuit (it is controlled by clock signal clk) is normally used for the external capacitive C that precharge is provided by phase inverter 206 and 208
eXT, and resistor R1 and R2(its as isolated component) by external capacitive C
eXTwith internal capacitance C
iNTisolation.In addition, because transistor Q10 and Q11 are external capacitive C
eXTprecharge is provided, so transistor Q1 and Q6 can reduce, drives intensity (being size), this reduces internal capacitance C
iNTand further reduce timeconstantτ.
Dispenser 202-1 shown in Figure 5 is to another example (it is 202-B by label) of 202-N.Dispenser 202-B is similar to dispenser 202-A, except buffer circuit 204-A is isolated circuit 204-B, replaces.In buffer circuit 204-B, interrupteur SW 1 and SW2 are used as isolated component.These interrupteur SW 1 and SW2 by clock signal clk ' control.As shown in Figure 6, generated clock signal CLK' so that the activation of the read-out amplifier 50 of being realized by clock signal clk and by clock signal clk ' there is the non-overlapped cycle between the interrupteur SW 1 that realizes and the activation of SW2.During these non-overlapped cycles, isolate this external capacitive C
eXT, this allows timeconstantτ by internal capacitance C
iNTset.Output circuit (being phase inverter 206 and 208) after time point (once read-out amplifier 50 has been resolved the value on terminal R and S) be coupled to terminal R and S.
Owing to adopting these dispensers 202-1 to 202-N, can realize several advantages.The first, the propagation delay of shortening allows this dispenser 202-1 to move at a relatively high speed (being that clock frequency CLK is higher) to 202-N.The second, can reduce comparer metastability.And the 3rd, the bit error rate (BER) (BER) of improvement ADC114 and whole transceiver system.
Therefore with reference to some preferred embodiment of the present invention, the present invention is described, it should be noted that the disclosed embodiments are actually illustrative rather than restriction, and above-mentioned, expect various variations, modification, change and replacement in open, and can adopt in some cases devices more of the present invention and do not need other devices of corresponding use.What therefore, be applicable to is that claim is widely interpreted and consistent with protection scope of the present invention.
Claims (20)
1. a device, comprises:
CMOS read-out amplifier, it has first input end, the second input end, the first output terminal and the second output terminal;
The first output circuit, it has the first load capacitance;
The second output circuit, it has the second load capacitance; With
Buffer circuit, it is connected between first output terminal and described the first output circuit of described CMOS read-out amplifier, and it is connected between the second output terminal of described CMOS read-out amplifier and the second output terminal of described CMOS read-out amplifier, wherein said buffer circuit is by described the first load capacitance and described the second load capacitance and the isolation of described CMOS read-out amplifier.
2. device according to claim 1, wherein said the first and second output circuits comprise respectively the first and second phase inverters further.
3. device according to claim 2, wherein said CMOS read-out amplifier is controlled by clock signal, and wherein said buffer circuit further comprises:
Pre-charge circuit, it is coupled to described the first phase inverter and described the second phase inverter, and it is controlled by described clock signal; With
The first isolated component, it is connected between first output terminal and described the first phase inverter of described CMOS read-out amplifier; With
The second isolated component, it is connected between second output terminal and described the second phase inverter of described CMOS read-out amplifier.
4. device according to claim 3, wherein said pre-charge circuit further comprises:
The first MOS transistor, it is coupled to described the first phase inverter in its drain electrode; With
The second MOS transistor, it is coupled to described the second phase inverter in its drain electrode.
5. device according to claim 4, wherein said the first isolated component and described the second isolated component further comprise respectively the first resistor and the second resistor.
6. device according to claim 4, wherein said clock signal further comprises the first clock signal, and wherein said the first isolated component and described the second isolated component further comprise respectively the first switch and the second switch by second clock signal controlling, and wherein between the activation of the described CMOS read-out amplifier of being realized by described clock signal and described the first switch of being realized by described second clock signal and the activation of described second switch, there is the non-overlapped cycle.
7. device according to claim 4, wherein said read-out amplifier comprises further:
Clock circuit, thus it is configured and receives described the first clock signal;
Difference input transistors pair, thus it is configured reception differential input signal;
First pair of X-bracing transistor, it is coupled to described difference input transistors pair; With
Second pair of X-bracing transistor, it is coupled to described first pair of X-bracing transistor.
8. a device, comprises:
AFE (analog front end) is AFE;
Analog to digital converter is ADC, and it is coupled to described AFE, and wherein said ADC has a plurality of dispensers, and wherein each dispenser comprises:
CMOS read-out amplifier, it has first input end, the second input end, the first output terminal and the second output terminal;
The first output circuit, it has the first load capacitance;
The second output circuit, it has the second load capacitance;
Buffer circuit, it is connected between first output terminal and described the first output circuit of described CMOS read-out amplifier, and it is connected between the second output terminal of described CMOS read-out amplifier and the second output terminal of described CMOS read-out amplifier, wherein said buffer circuit is by described the first load capacitance and described the second load capacitance and the isolation of described CMOS read-out amplifier; With
Decision zeedback equalizer is DFE, and it is coupled to described ADC.
9. device according to claim 8, wherein said the first output circuit and described the second output circuit further comprise respectively the first phase inverter and the second phase inverter.
10. device according to claim 9, wherein said CMOS read-out amplifier is controlled by clock signal, and wherein said buffer circuit further comprises:
Pre-charge circuit, it is connected between described the first phase inverter and described the second phase inverter, and it is controlled by described clock signal; With
The first isolated component, it is connected between first output terminal and described the first phase inverter of described CMOS read-out amplifier; With
The second isolated component, it is connected between second output terminal and described the second phase inverter of described CMOS read-out amplifier.
11. devices according to claim 10, wherein said pre-charge circuit further comprises:
The first MOS transistor, it is coupled to described the first phase inverter in its drain electrode; With
The second MOS transistor, it is coupled to described the second phase inverter in its drain electrode.
12. devices according to claim 11, wherein said the first isolated component and described the second isolated component further comprise respectively the first resistor and the second resistor.
13. devices according to claim 11, wherein said clock signal further comprises the first clock signal, and wherein said the first isolated component and described the second isolated component further comprise respectively the first switch and the second switch by second clock signal controlling, and wherein between the activation of the described CMOS read-out amplifier of being realized by described clock signal and described the first switch of being realized by described second clock signal and the activation of described second switch, there is the non-overlapped cycle.
14. devices according to claim 11, wherein said read-out amplifier further comprises:
Clock circuit, thus it is configured and receives described the first clock signal;
Difference input transistors pair, thus it is configured reception differential input signal;
First pair of X-bracing transistor, it is coupled to described difference input transistors pair; With
Second pair of X-bracing transistor, it is coupled to described first pair of X-bracing transistor.
15. 1 kinds of devices, comprise:
Serializer;
Transmitter, it is coupled to described serializer;
Communication media, it is coupled to described transmitter;
Receiver, it has:
AFE；
ADC, it is coupled to described AFE, and wherein said ADC has a plurality of dispensers, and wherein each dispenser comprises:
Read-out amplifier, has:
The first power supply rail;
The second power supply rail;
The first output terminal;
The second output terminal;
X-bracing PMOS transistor pair, its each be coupled to described the first output terminal and described the second output terminal and be coupled to described the first power supply rail;
X-bracing nmos pass transistor pair, its each be coupled to described the first output terminal and described the second output terminal;
Difference input NMOS transistor pair, its each be coupled to described communication channel and described X-bracing nmos pass transistor pair;
The first clock nmos pass transistor, it is connected between described the first power supply rail and described the first output terminal, thereby and its be configured receive clock signal;
Second clock nmos pass transistor, it is connected between described the first power supply rail and described the second output terminal, thereby and its be configured and receive described clock signal; With
The 3rd clock nmos pass transistor, its be connected in described difference input NMOS transistor to and described the second power supply rail between, thereby and its be configured and receive described clock signal;
The first output circuit, it has the first load capacitance;
The second output circuit, it has the second load capacitance;
Buffer circuit, it is connected between first output terminal and described the first output circuit of described read-out amplifier, and it is connected between the second output terminal of described read-out amplifier and the second output terminal of described read-out amplifier, wherein said buffer circuit is by described the first load capacitance and described the second load capacitance and the isolation of described read-out amplifier; With
DFE, it is coupled to described ADC; And deserializer, it is coupled to described DFE.
16. devices according to claim 15, wherein said the first output circuit and described the second output circuit further comprise respectively the first phase inverter and the second phase inverter.
17. devices according to claim 16, wherein said buffer circuit comprises:
Pre-charge circuit, it is connected between described the first phase inverter and described the second phase inverter, and it is controlled by described clock signal; With
The first isolated component, it is connected between first output terminal and described the first phase inverter of described read-out amplifier; With
The second isolated component, it is connected between second output terminal and described the second phase inverter of described read-out amplifier.
18. devices according to claim 10, wherein said pre-charge circuit further comprises:
The first precharge PMOS transistor, it is coupled to described the first phase inverter in its drain electrode; With
The second precharge PMOS transistor, it is coupled to described the second phase inverter in its drain electrode.
19. devices according to claim 18, wherein said the first isolated component and described the second isolated component further comprise respectively the first resistor and the second resistor.
20. devices according to claim 18, wherein said clock signal further comprises the first clock signal, and wherein said the first isolated component and described the second isolated component further comprise respectively the first switch and the second switch by second clock signal controlling, and wherein between the activation of the described read-out amplifier of being realized by described clock signal and described the first switch of being realized by described second clock signal and the activation of described second switch, there is the non-overlapped cycle.
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