CN104035878A - Storage control device, storage device, information processing system, and storage control method - Google Patents

Storage control device, storage device, information processing system, and storage control method Download PDF

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Publication number
CN104035878A
CN104035878A CN201410069124.5A CN201410069124A CN104035878A CN 104035878 A CN104035878 A CN 104035878A CN 201410069124 A CN201410069124 A CN 201410069124A CN 104035878 A CN104035878 A CN 104035878A
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part unit
unit
data
write
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CN104035878B (en
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中西健一
藤波靖
石井健
岩城宏行
森健太郎
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Sony Corp
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Sony Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)

Abstract

The invention relates to a storage control device, a related storage device, an information processing system and a storage control method used in the devices. The storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer. According to the invention, the write processing operation can be continued as far as possible even when the partial of the write unit is in a busy state.

Description

Memory controller part, memory device, information handling system and storage controlling method
Technical field
The present invention relates to memory controller part.More specifically, the present invention relates to memory controller part, memory device, for the information handling system of storer and the disposal route of this device and system.
Background technology
In information handling system, dynamic RAM (Dynamic Random Access Memory, DRAM) etc. is used as working storage.This DRAM is typical volatile memory, once power supply quits work, the content of its storage will disappear.Meanwhile, in recent years, nonvolatile memory (NVM) is widely used.This nonvolatile memory falls into the general classification of the nonvolatile RAM (NVRAM) of the flash memory corresponding as the data access of unit with size of data taking large and high random access that can be taking little size of data as unit.Here, the typical case of flash memory can comprise NAND type flash memory.On the other hand, the example of nonvolatile RAM can comprise ReRAM (resistance-type RAM), PCRAM (phase-change type RAM) and MRAM (reluctance type RAM) etc.
In the processing that writes data into memory cell, imagination nonvolatile memory in write step, write data into memory cell and in verification step from memory cell reading out data and by read data and the data that write are compared to implement checking.In the time of write store unit, repeat these steps until confirmed Data Matching according to the data comparative result in the verification step after write step.Because memory cell has the variation of certain limit in characteristic, and in the quantity of these steps, found similar variation, therefore, the rush hour appearing at during write operation is not regular time section yet.Correspondingly, for the rush hour that writes of nonvolatile memory, specify representative value and maximal value to be used as general standard.Representative value by write operation during the average frequency of good authentication decide, and the maximum frequency that maximal value is repeated by write step and verification step decides.If these steps are repeated to maximum times, the memory cell of authentication failed can be judged as defective unit conventionally so.
Due to the variation on this write time, the write performance of nonvolatile memory is owing to having the unit of long write time and deteriorated.Typically, in nonvolatile memory, simultaneously to formed and be commonly referred to as the unit's of writing enforcement write operation of page by multiple memory cells.Thereby, even if only have several memory cells in page, because above-mentioned variation has the long write time, being also difficult to start writing of lower one page before completing the writing of these memory cells, this causes whole the deteriorated of handling property that write.For adopting polylith (multi-bank) structure, (it has and uses page as so same the nonvolatile memory of multiple non-volatile memory block (memory bank) of the unit of writing.Due to variation increased certain piece page the write time, and therefore any other piece that has completed write operation starts the state writing of lower one page until this piece completes its write operation in waiting, this has caused deteriorated on write performance of whole nonvolatile memory.More specifically, no matter which kind of situation, although the state of the page of piece that has completed write operation in only starting write operation in the time receiving next data, but next data entry still rests on armed state until all pieces all complete its write operation, and this has caused write performance decline.
On the contrary, following methods has been proposed,, by preventing that data transmission period from becoming the expense (for example,, with reference to Japanese uncensored patented claim 2003-196989) while starting next write operation writing the internal buffer that during the rush hour, next data writing is transferred to nonvolatile memory.In addition, for polylith structure, following methods is proposed, that is, and by being each expense (for example,, with reference to Japanese uncensored patented claim 2007-080475) while providing impact damper to reduce to start write operation.
But, during writing the rush hour, data writing is transferred in the prior art of impact damper, be difficult to prevent by the reduction that writes the speed that the rush hour causes increasing.In addition, providing for each in the prior art of impact damper, the reason of the reduction that writes the speed that the rush hour causes increasing because serving as reasons, has only obtained and identical above effect.In addition, this prior art comprises the impact damper with page size for each, and its shortcoming is that the size of each impact damper also increases along with the increase of the quantity of piece in the big or small increase of the page as the unit of writing and nonvolatile memory.
In the at present available nonvolatile memory with flash memory representative, the representative value of the rush hour can be that about hundreds of microsecond arrives the order of magnitude of several milliseconds, and the rush hour does not change with the multiple of representative value, but change with meticulousr chronomere.Correspondingly, time of representative value has more mastery than the time span changing, and by absorbing the effect of the performance improvement that this variation realizes little.On the contrary, in the NVRAM as new pattern high speed nonvolatile memory, can be as small as the value of approximately tens of nanoseconds to the order of magnitude of several microseconds because write the rush hour, and the variation of the rush hour is also equivalent to the time of almost identical order of magnitude length, rush hour variation is significant on the impact of write performance.In addition, because the size of the page as the unit of writing is little, and provide high-speed interface, so shorten significantly by the rush hour that provides impact damper as above to allow to be hidden.
Summary of the invention
In view of this, even if expect to provide the technology that also continues as much as possible to write processing operation while being placed in busy state in the part unit of writing.
According to embodiments of the invention, a kind of memory controller part is provided, it comprises: part unit buffer, it is for keeping being assigned at least one data of part unit, and the unit of writing of storer is divided into multiple described part units; And request generating unit, even if it is in the situation that described storer is indicated arbitrary part unit in busy state, in the time that described part unit buffer can keep being assigned to the data of this part unit, still generate the write request of the said write unit of described storer.Even if this has brought the function that also generates as much as possible write request in the time that existence is indicated as the part unit in busy state.
According to embodiments of the invention, a kind of storage controlling method is provided, it comprises: even if storer instruction is by dividing arbitrary part unit in the part unit forming in busy state to the unit of writing of storer, the data that can keep being assigned to this part unit in part unit buffer, still generate the write request of the said write unit of described storer; And in the case of the generation of said write request, execution writes control, so that described part unit buffer keeps being assigned to the data that are indicated as the part unit in busy state, and will be assigned to the data transmission that is not indicated as the part unit in described busy state to described storer.Even if this has brought the function that also generates as much as possible write request in the time that existence is indicated as the part unit in busy state.
Advantageously, memory controller part also comprises: write control part, it for making described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described storer in the case of the generation of said write request.This has brought the function of carrying out distribute data according to the busy state of part unit.
Advantageously, in the time that the subsequent data that is assigned to the part unit that cancels busy state is maintained in described part unit buffer, said write control part is transferred to described storer by described subsequent data from described part unit buffer.This has brought the chance of the cancellation of the busy state that utilizes part unit to transmit the function of data from part unit buffer.
Advantageously, memory controller part also comprises: signal generating unit, it is for generating signal, described signal is used for: be designated as the part unit in busy state when existing by described storer, and when described part unit buffer can not keep being assigned to the data of this part unit, instruction disarmed state; When described part unit buffer is in dummy status, and there is not while being designated as the part unit in busy state by described storer instruction effective status; And in the time that existence is designated as the part unit in busy state by described storer, and when described part unit buffer can keep the data of this part unit, instruction effective status, wherein, in the time of described signal designation effective status, described request generating unit generates the write request of said write unit.This has brought by utilization indicates the existence of effective status and non-existent signal to control the function of the generation of write request.
According to embodiments of the invention, a kind of memory device is provided, it comprises: memory cell array, the unit of writing of described memory cell array is divided into multiple part units with storage data; Part unit buffer, it is for keeping being assigned at least one data of described part unit; Request generating unit, even if it is in the situation that described storer is indicated arbitrary described part unit in busy state, in the time that described part unit buffer can keep being assigned to the data of this part unit, still generate the write request of the said write unit of described memory cell array; And write control part, it is in the case of the generation of said write request, make described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described memory cell array.Even if this has brought in the time there is the part unit being indicated as in busy state and has also generated as much as possible write request to carry out the function of distribute data according to the busy state of part unit.
Advantageously, described memory cell array comprises the memory cell with non-volatile memory device.
According to embodiments of the invention, a kind of information handling system is provided, it comprises: memory cell array, the unit of writing of described memory cell array is divided into multiple part units with storage data; Host computer, it is for sending the instruction that writes of said write unit; Part unit buffer, it is for keeping being assigned at least one data of described part unit; Request generating unit, the in the situation that it sending in said write instruction, even in busy state, still generate the write request of the said write unit of described memory cell array for the arbitrary described part unit of described storer instruction in the time that described part unit buffer can keep being assigned to the data of this part unit; And write control part, it is in the case of the generation of said write request, make described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described memory cell array.Even if having brought, this in the time there is the part unit being indicated as in busy state, also generates as much as possible write request to carry out the function of distribute data according to the busy state of part unit sending while writing instruction.
According to the embodiment of the invention described above, even if can realize the remarkable result that also can continue as much as possible to write processing operation while being placed in busy state in the part unit of writing.
Should be appreciated that aforesaid general explanation and illustrating are below all exemplary, aim to provide the further explanation of desired technology.
Brief description of the drawings
Comprise that accompanying drawing is to provide a further understanding of the present invention, accompanying drawing is merged in and forms the part of this instructions.Accompanying drawing illustrates embodiment, and is used for illustrating principle of the present invention together with instructions.
Fig. 1 shows according to the schematic block diagram of the structure example of the information handling system of the embodiment of the present invention.
Fig. 2 shows according to the schematic block diagram of the functional configuration example of the embodiment of the present invention.
Fig. 3 shows according to the schematic block diagram of the structure example of the storer 300 of first embodiment of the invention.
Fig. 4 shows according to the schematic block diagram of the given example of the page address of the storer 300 of first embodiment of the invention.
Fig. 5 shows according to the sequential chart of the example in the time sequential routine of first embodiment of the invention.
Fig. 6 A and Fig. 6 B all show the schematic diagram of the summary of effect in first embodiment of the invention.
Fig. 7 show receive according to first embodiment of the invention write instruction time the process flow diagram of example for the treatment of step.
Fig. 8 shows the process flow diagram of the example of the treatment step of the first write request of implementing according to the present invention.
Fig. 9 shows and discharges according to the process flow diagram of the example of the treatment step of the subpage impact damper 320 of first embodiment of the invention.
Figure 10 shows according to the schematic block diagram of the structure example of the storer 300 of second embodiment of the invention.
Figure 11 shows according to the schematic block diagram of the given example of the page address of the storer 300 of second embodiment of the invention.
Figure 12 shows according to the sequential chart of the example in the time sequential routine of second embodiment of the invention.
Figure 13 show receive according to second embodiment of the invention write instruction time the process flow diagram of example for the treatment of step.
Figure 14 shows according to the process flow diagram of the example of the treatment step of the write request of second embodiment of the invention.
Figure 15 shows and discharges according to the process flow diagram of the example of the treatment step of the page buffer 321 of second embodiment of the invention.
Figure 16 shows according to the schematic block diagram of the structure example of the storer 300 of third embodiment of the invention.
Figure 17 is according to the truth table of the busy signal generative circuit 351 of third embodiment of the invention.
Figure 18 shows according to the sequential chart of the example in the time sequential routine of third embodiment of the invention.
Figure 19 show receive according to third embodiment of the invention write instruction time the process flow diagram of example for the treatment of step
Figure 20 shows according to the process flow diagram of the example of the treatment step of the write request of third embodiment of the invention.
Figure 21 shows and discharges according to the process flow diagram of the example of the treatment step of the page buffer 321 of third embodiment of the invention.
Figure 22 shows according to the schematic block diagram of the structure example of the controller 200 of the storer 300 of fourth embodiment of the invention and storer.
Figure 23 shows according to the schematic block diagram of the structure example of the storer 300 of fifth embodiment of the invention.
Figure 24 shows according to the schematic block diagram of the structure example of the storer 300 of sixth embodiment of the invention.
Embodiment
Hereinafter, some embodiments of the present invention (hereinafter referred to as " embodiment ") have been described.
The structure of information handling system
Fig. 1 shows the schematic block diagram of the structure example of information handling system according to an embodiment of the invention.This information handling system is made up of host computer 100 and accumulator system 400.Accumulator system 400 is made up of storer 300 and Memory Controller 200.
Host computer 100 sends the instruction for asking accumulator system 400 to be carried out data read/write etc.In this embodiment of the present invention, main concern writes sending of instruction.
Suppose that storer 300 is made up of nonvolatile memory, and particularly by nonvolatile RAM (NVRAM) formation that can carry out with little unit high random access.The example of NVRAM can comprise resistance-type ReRAM, phase-change type PCRAM and magnetic resistance change rate formula MRAM etc.
Memory Controller 200 carrys out control store 300 in response to the request that is derived from host computer 100.Interface (I/F) between Memory Controller 200 and host computer 100 sides refers to host interface 201, and interface between itself and storer 300 sides refers to memory interface 202.
Fig. 2 is the schematic block diagram illustrating according to the functional configuration example of the embodiment of the present invention.Fig. 2 shows memory cell array 31, part unit buffer 32, request generating unit 21 and writes control part 35.Memory cell array 31 is arranged in storer 300.Part unit buffer 32, request generating unit 21 and write control part 35 and be arranged in storer 300 or Memory Controller 200.
Memory cell array 31 is set of the memory cell that is made up of nonvolatile memory, and it can realize the write-once to the single unit of writing.In this example, memory cell array 31 is divided into four partial arrays, that is, partial array 0 is to partial array 3, and the data that are assigned to each part unit (unit of writing after four parts dividing) are write independently of one another.Busy state using the partial array in memory cell array 31 0 to partial array 3 offers request generating unit 21 as Busy0 signal to Busy3 signal respectively.
Part unit buffer 32 is the impact dampers for keeping the data that are assigned to part unit (through the unit of writing dividing).In the time generating the request that memory cell array 31 is write, if a part of part unit in the memory cell array 31 instruction units of writing, in busy state, remains on the data that are assigned to this part part unit in part unit buffer 32 so.On the other hand, by the data transmission that is assigned to following part unit, to memory cell array 31, this part unit is stored device cell array 31 and is designated as in ready state.Offer request generating unit 21 using the data hold mode of part unit buffer 32 as Bufstat signal.
When host computer 100 sends while writing instruction, request generating unit 21 generates based on Bufstat signal and Busy0 to Busy3 signal the request that the unit of writing in memory cell array 31 is write.Even if memory cell array 31 indicates arbitrary portion unit in busy state, if but could keep the situation of the data that are assigned to these part units to set up in part unit buffer 32, request generating unit 21 would still generate the request that the unit of writing is write.In other words,, in the time of the full state of Bufstat signal designation, request generating unit 21 does not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, request generating unit 21 does not equally generate write request yet.On the other hand, in the time being no more than one instruction busy state in Bufstat signal designation dummy status and Busy0 to Busy3 signal, request generating unit 21 generates write request.Note, in the time that request generating unit 21 does not generate write request, it is configured to armed state until Bufstat signal and Busy0 to Busy3 signal meet above-mentioned condition.In addition, in this example, the maintenance capacity of supposing part unit buffer 32 is a part unit.
In the time generating the request that the unit of writing is write, write control part 35 and control the data that are assigned to part unit.More specifically, write control part 35 control section unit buffer 32 and be designated as the data of the part unit in busy state so that its maintenance is assigned to the partial array being stored in device cell array 31.In addition, write control part 35 and will be assigned to data transmission that the partial array being stored in device cell array 31 is designated as the part unit in ready state to memory cell array 31.Subsequently, for the part unit corresponding with the partial array of cancelling busy state, in the time that next data is maintained in part unit buffer 32, writes control part 35 these data are transferred to memory cell array 31 from part unit buffer 32.
Hereinafter, under the prerequisite of above-mentioned information handling system and functional configuration thereof, some embodiments of the present invention are described.With the order providing below, some embodiments of the present invention are described.
1. the first embodiment (access that writes taking page as basis is divided into the example that writes access taking subpage as basis)
2. the second embodiment (for the each example that writes access of dividing across piece)
3. the 3rd embodiment (Busy signal is placed on to the example in storer together)
4. the 4th embodiment (in the example of Memory Controller side management page buffer)
5. the 5th embodiment (each shares the example of multiple page buffers)
6. the 6th embodiment (each group shares the example of page buffer)
1. the first embodiment
[structure of storer]
Fig. 3 shows according to the schematic block diagram of the structure example of the storer 300 of first embodiment of the invention.Storer 300 comprises memory cell array 310, subpage impact damper 320, sub-page address impact damper 330, divider 340 and controller interface circuit 390.
Memory cell array 310 is set of the memory cell that is made up of nonvolatile memory, and it can carry out the write-once of single page.In this example, memory cell array 310 configures as follows, that is, the data that are assigned to each subpage (through the page of four divisions) are write independently of one another.The busy state of each subpage in memory cell array 310 is offered to controller interface circuit 390 as each Busy0 to Busy3 signal.In the first embodiment of the present invention, mainly pay close attention to the variation that writes the rush hour of this subpage (through the page of dividing).
Subpage impact damper 320 is the impact dampers for keeping the data that are assigned to subpage.In the time generating the request that memory cell array 310 is write, if memory cell array 310 indicates a part of subpage in whole page in busy state, the data that are designated to these subpages to be remained in subpage impact damper 320.On the other hand, be stored data transmission that device cell array 310 is designated as the subpage in ready state to memory cell array 310 by being assigned to.The data hold mode of subpage impact damper 320 is offered to controller interface circuit 390 as Bufstat signal.
Sub-page address impact damper 330 is the impact dampers for keeping data that subpage impact damper 320 the keeps address on memory cell array 310.In other words, sub-page address impact damper 330 designation datas are assigned to which subpage of which page.
Divider 340 by the data allocations that is assigned to the data of the subpage comprising in relevant with write request page or is assigned to the subpage keeping in subpage impact damper 320 to the corresponding sub-page address in memory cell array 310.Dividing timing to the data of the subpage comprising in being assigned to the page relevant with write request, with reference to the address relevant with write request.Dividing timing to the data of the subpage keeping in being assigned to subpage impact damper 320, with reference to the address keeping in sub-page address impact damper 330.
Controller interface circuit 390 is mutual circuit of being responsible between Memory Controller 200.Controller interface circuit 390 receives via request/address signal line (Rqt/Adr) and data signal line (Data) write request being generated by Memory Controller 200.In this context, write instruction once host computer 100 sends, Memory Controller 200 generates based on Bufstat signal and Busy0 to Busy3 signal the request that the unit of writing in memory cell array 310 is write.In other words,, in the time of the full state of Bufstat signal designation, Memory Controller 200 does not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, Memory Controller 200 does not equally generate write request yet.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, Memory Controller 200 generates write request.Note, in the time that Memory Controller 200 does not generate write request, it is placed in armed state until Bufstat signal and Busy0 to Busy3 signal meet above-mentioned condition.In addition, Bufstat signal and Busy0 to Busy3 signal are sent to Memory Controller 200 by controller interface circuit 390.
In addition, in the time that Memory Controller 200 is generated to the request that the unit of writing is write, controller interface circuit 390 is controlled the data that are assigned to subpage.More specifically, controller interface circuit 390 is controlled subpage impact damper 320 so that its maintenance is assigned to the data of being indicated the subpage of busy state by memory cell array 310.In addition, controller interface circuit 390 is stored data transmission that device cell array 310 is designated as the subpage in ready state to memory cell array 310 by being assigned to.Subsequently, for the subpage of cancelling busy state, in the time that next data is maintained in subpage impact damper 320, controller interface circuit 390 is transferred to memory cell array 310 by these data from subpage impact damper 320.
Note, memory cell array 31 is realized as the function with the memory cell array 310 in above-mentioned functions structure.Part unit buffer 32 is realized as the function with the subpage impact damper 320 in above-mentioned functions structure.In addition, request generating unit 21 is realized as the function with the Memory Controller 200 in above-mentioned functions structure.In addition, write control part 35 and be realized as the controller interface circuit 390 that has in above-mentioned functions structure and the function of divider 340.
Fig. 4 shows according to the schematic block diagram of the given example of the page address of the storer 300 of first embodiment of the invention.According in the storer 300 of first embodiment of the invention, whole storage space is taking page as basic linear address space.Subpage obtains by page being divided into four parts.
[time sequential routine]
Fig. 5 shows according to the sequential chart of the example in the time sequential routine of first embodiment of the invention.Fig. 5 illustrates the continuous page write operation of following mode,, for example, is written to respectively page 0, page 1 and page 2 via page data Data0, Data1 and the Data2 of data signal line transmission that is.In the time receiving page data, storer 300 starts writing of all subpages simultaneously and processes operation, and the Busy0 to Busy3 of all subpages signal becomes the busy state that is used to indicate write operation well afoot.
In this example, although in the time writing Data0, the rush hour that writes of subpage 2 increases, owing to having the former of subpage impact damper 320 thereby in the moment of the write operation that completes any other subpage, next page data Data1 being transferred to storer 300 from Memory Controller 200.Now, the data of the subpage 2 comprising in Data1 are maintained in subpage impact damper 320, and the address information that writes destination that is used to indicate data is maintained in sub-page address impact damper 330.As a result, Bufstat signal is changed into High state and is placed in full state for instruction subpage impact damper 320.
Completing when Data0 is write to subpage 2, the subpage data that remain on the Data1 of subpage impact damper 320 are transferred to immediately the position of subpage 2 on memory cell array 310 together with address information, process operation thereby start next.Now, the Bufstat signal that is used to indicate the state of empty subpage impact damper 320 is changed into Low state.
Although in the time writing Data2, subpage 1 write the rush hour increase, subpage impact damper 320 is placed in dummy status, and thereby Memory Controller 200 next page data Data3 is transferred to storer 300.The data of the subpage 1 comprising in Data3 are maintained at subpage impact damper 320, and the address information that writes destination that is used to indicate data is maintained in sub-page address impact damper 330.
Fig. 6 A and 6B are the schematic diagram of the summary that shows the effect in first embodiment of the invention.Note, every width accompanying drawing does not comprise the time that transfers data to memory cell array 310 and subpage impact damper 320.
In every width accompanying drawing, suppose simultaneously and continuously each page that is divided into four subpages implemented to four write operations.As shown in Figure 6A, in the conventional method, in each write operation, the rush hour that writes of a subpage has increased, and so whole write performance is just decided by this write time.Here be that the twice of length of the common rush hour, this equals the rush hour of octuple altogether in the hypothesis rush hour.On the other hand, if can receive and be assigned to the data that increased the subpage that writes the rush hour on subpage impact damper 320, next page data be allowed to be written to the subpage that write operation is completed in advance so.As shown in Figure 6B, the memory cell in hypothesis with the longer write time does not concentrate under the prerequisite on single subpage, so, can complete write operation with the rush hour of six times, and this brings the improvement of performance..
[treatment step]
Fig. 7 is the process flow diagram that the example of the treatment step while writing instruction according to the reception of first embodiment of the invention is shown.Treatment step when reception writes instruction is implemented by Memory Controller 200.Here suppose to allow to keep being assigned to the data of a subpage, on subpage impact damper 320.
First, the first page number relevant with writing instruction arranged to variable " p " (step S911).For this variable " p ", set up the value (step S916) that just increases by 1 in the time that the processing of a page has operated.
Whether Memory Controller 200 generates write request (step S912) according to Bufstat signal and Busy0 to Busy3 signal deciding.More specifically, in the time of the full state of Bufstat signal designation, Memory Controller 200 determines to maintain armed state and does not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, Memory Controller 200 equally also determines to maintain armed state and does not generate write request.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, Memory Controller 200 determines to generate write requests.
While not generating write request when determining to maintain armed state (step S912: no), Memory Controller 200 maintains armed state until meet the condition that generates write request.On the other hand, in the time determining to generate write request (step S912: be), Memory Controller 200 generates write request (step S913) taking page as basis.In this case, write request parameter is transmitted in the lump.Subsequently, via memory interface 202, page data is transferred to storer 300 (step S914) from Memory Controller 200.
In the time writing the page of instruction after being applied to equally processed page (step S915: be), variable " p " increases by 1 (step S916), and repeats the processing operation of lower one page.In the time writing instruction and be not applied to lower one page (step S915: no), treatment step completes.
Fig. 8 shows according to the process flow diagram of the example of the treatment step of the write request of first embodiment of the invention.The treatment step of this write request is implemented by controller interface circuit 390 and divider 340.
In the time generating write request, the first sub-page number relevant with write request is set to variable " s " (step S921).Here " 0 " is assumed to first sub-page number.For this variable " s ", set up the value (step S929) that just increases by 1 in the time that the processing of a subpage has operated.
In memory cell array 310, if subpage " s " is not placed in busy state (step S922: no), so, data and address transfer are arrived to memory cell array 310 (step S923), and start the write operation (step S924) of subpage " s ".
On the contrary, in memory cell array 310, in the time that subpage " s " is placed in busy state (step S922: be), determine whether subpage impact damper 320 is placed in full state (step S925).If subpage impact damper 320 has been placed in full state (step S925: be), so, repeat the treatment step after step S922.If subpage impact damper 320 is not placed in full state (step S925: no), so, data is remained in subpage impact damper 320, and sub-page number " s " and address are remained on to (step S926) in sub-page address impact damper 330.Thereafter, the dummy status of subpage impact damper 320 is cancelled and will be placed in full state (step S927).Bufstat signal is placed in full state by this.
In the time that write request is applied to the subpage after processed subpage equally (step S928: be), variable " s " increases by 1 (step S929), and repeats the processing operation of next page.In the time write request not being applied to lower one page (step S928: no), treatment step completes.
Note, although can alternately implement the treatment step of each subpage parallelly, for convenience's sake, the continuous treatment step of each subpage has been described here.
Fig. 9 shows according to the process flow diagram of the example of the treatment step of the release subpage impact damper 320 of first embodiment of the invention.The treatment step that discharges subpage impact damper 320 is implemented by controller interface circuit 390 and divider 340.
In memory cell array 310, process while operate writing of any one subpage, just obtain and completed the sub-page number " e " (step S931) of processing this subpage operating.In addition, in the time being assigned to the data of subpage " e " and being maintained at subpage impact damper 320 (step S932: be), implement following steps.
Transmit data from subpage impact damper 320, and from sub-page address impact damper 330 transport addresses (step S933).Subsequently, the full state of cancelling subpage impact damper 320 is to be placed on dummy status (step S934).Bufstat signal is placed in dummy status by this.Thereafter the writing of subpage " e " starting in memory cell array 310, processed operation (step S935).
On the contrary, in the time being assigned to the data of subpage " e " and not being maintained in subpage impact damper 320 (step S932: no), process and operated.
As mentioned above, according to the first embodiment of the present invention, in memory cell array 310, even if a part of subpage of working as in the page being written into is indicated as in busy state, as long as subpage impact damper 320 can be used, still can continue to write processing operation.
2. the second embodiment
[structure of storer]
Figure 10 shows according to the schematic block diagram of the structure example of the storer 300 of second embodiment of the invention.Storer 300 comprises memory cell array 311, page buffer 321, page address impact damper 331, divider 341 and controller interface circuit 391.
Memory cell array 311 is set of the memory cell that is made up of nonvolatile memory, and can carry out the write-once of multiple pages.In this example, memory cell array 311 is divided into four pieces, and is configured to following mode, that is, write independently of one another each data of single page.The busy state of each piece in memory cell array 311 is offered to controller interface circuit 391 as each Busy0 to Busy3 signal.In second embodiment of the invention, mainly pay close attention to the variation that writes the rush hour in this polylith structure.
Page buffer 321 is the impact dampers for keeping the data that are assigned to page.In the time generating the request that memory cell array 311 is write, if memory cell array 311 indicates a part of piece in busy state, so the data that are assigned to this partial block are remained in page buffer 321.On the other hand, be stored data transmission that device cell array 311 is designated as the piece in ready state to memory cell array 311 by being assigned to.The data hold mode of page buffer 321 is offered to controller interface circuit 391 as Bufstat signal.
Page address impact damper 331 is the impact dampers for keeping data that page buffer 321 the keeps address on memory cell array 311.In other words, which page is page address impact damper 331 designation datas be assigned to.
Divider 341 by the data allocations that is assigned to the data of relevant with write request page or is assigned to the page keeping in page buffer 321 to the relevant block address on memory cell array 311.In the carrying out point timing of the data to the designated page relevant with write request, with reference to the address relevant with write request.In the data of the page keeping in being assigned to page buffer 321 are distributed, the address keeping in referer address buffer 331.
Controller interface circuit 391 is mutual circuit of being responsible between Memory Controller 200.Controller interface circuit 391 receives via request/address signal line (Rqt/Adr) and data signal line (Data) write request being generated by Memory Controller 200.In this context, write instruction once host computer 100 sends, Memory Controller 200 just generates based on Bufstat signal and Busy0 to Busy3 signal the request that the unit of writing in memory cell array 311 is write.In other words,, in the time of the full state of Bufstat signal designation, Memory Controller 200 does not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, Memory Controller 200 does not equally generate write request yet.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, Memory Controller 200 generates write request.Note, in the time that Memory Controller 200 does not generate write request, it is placed in armed state until Bufstat signal and Busy0 to Busy3 signal meet above-mentioned condition.In addition, Bufstat signal and Busy0 to Busy3 signal are sent to Memory Controller 200 by controller interface circuit 391.
In addition, in the time that Memory Controller 200 generates the request that the unit of writing is write, controller interface circuit 391 is controlled the data that are assigned to the page relevant with write request.More specifically, controller interface circuit 391 is controlled page buffer 321, so that its maintenance is assigned to and data that are indicated as the corresponding page of piece in busy state in memory cell array 311.In addition, controller interface circuit 391 will be assigned to the data transmission that is indicated as the corresponding page of piece in ready state in memory cell array 311 to memory cell array 311.Subsequently, for the piece of cancelling busy state, in the time that next data is maintained in page buffer 321, controller interface circuit 391 is transferred to memory cell array 311 by these data from page buffer 321.
Note, memory cell array 31 is realized as the function with the memory cell array 311 in above-mentioned functions structure.Part unit buffer 32 is realized as the function with the subpage impact damper 321 in above-mentioned functions structure.In addition, request generating unit 21 is realized as the function with the Memory Controller 200 in above-mentioned functions structure.In addition, write control part 35 and be realized as the controller interface circuit 391 that has in above-mentioned functions structure and the function of divider 341.
Figure 11 shows according to the schematic block diagram of the given example of the page address of the storer 300 of second embodiment of the invention.According in the storer 300 of second embodiment of the invention, the storage space of each has the address space that uses the common unit of page conduct, and this address space is considered to be from outside on the direction from piece 0 to piece 3 for the multiple address space of every one page column weight.Therefore, in the time of continuous page write operation, realize as follows write-in operation at high speed, that is, the data of four pages are simultaneously written into four pieces.
In addition, be called as a page group in the locational page of common address in each.Such as, page 0 to page 3 belongs to page group 0, and page 4 to page 7 belongs to page group 1, and page 8 to page 11 belongs to page group 2.
[time sequential routine]
Figure 12 shows according to the sequential chart of the example in the time sequential routine of second embodiment of the invention.Implement as follows continuous page write operation, that is, such as, be written to respectively piece 0, piece 1, piece 2, piece 3 and piece 0 via Data0, Data1, Data2, Data3 and the Data4 of data signal line transmission.In the time receiving data writing based on corresponding with all four pages, the writing of page that simultaneously starts four pieces processed operation, and Busy0 to the Busy3 signal of all pages becomes busy state, for instruction write operation well afoot.
In this example, increase although be written to the rush hour that writes of the Data2 of piece 2 in the time writing page data Data0 to Data3, because the moment that has the former of page buffer 321 thereby complete in the write operation of other pieces is transferred to storer 300 by next page data Data4 to Data7 from Memory Controller 200.At this moment, the page data Data6 of piece 2 to be written into is maintained in page buffer 321, and the information of piece 2 as data write destination and page address information is maintained in page address impact damper 331.As a result, Bufstat signal changes over High state, to be placed in full state with instruction page buffer 321.
In the time being written into the writing busy state and finish of piece 2 of page data Data2, next the page data Data6 being maintained in page buffer 321 is transferred to immediately piece 2 together with page address information, writes and processes operation thereby start next.Now, the Bufstat signal that is used to indicate the state of empty page buffer 321 changes over Low state.
Although the rush hour that writes of the Data9 of piece 1 to be written into increases in the time writing page data Data8 to Data11, but, page buffer 321 has been placed in dummy status, and next page data Data12 to Data15 is transferred to storer 300 by Memory Controller 200 thus.Now, the page data Data13 that waits to be written to the piece 1 that carries out write operation is maintained in page buffer 321, and the information of piece 1 as data write destination and page address information is maintained in page address impact damper 331.
[treatment step]
The process flow diagram of the example for the treatment of step when Figure 13 shows according to the reception that writes instruction of second embodiment of the invention.Treatment step when implementing to receive this and write instruction by Memory Controller 200.Here suppose to allow to keep being designated to the data of single page, in page buffer 321.
First, the first page group number relevant with writing instruction arranged to variable " p ", and be set to variable " b " (step S941) as " 0 " of first number of piece to be written into.For variable " b ", set up the value (step S946) that just increases by 1 in the time that the processing of a piece has operated.In addition, for variable " p ", set up the value (step S948) that just increases by 1 in the time that the processing of a page group has operated.
By with reference to Bufstat signal and Busy0 to Busy3 signal, Memory Controller 200 determines whether to generate write request (step S942).More specifically, in the time of the full state of Bufstat signal designation, Memory Controller 200 determines to maintain armed state and does not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, Memory Controller 200 determines too to maintain armed state and does not generate write request.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, Memory Controller 200 determines to generate write requests.
While not generating write request when determining to maintain armed state (step S942: no), Memory Controller 200 maintains armed state until meet the condition that generates write request.On the other hand, in the time determining to generate write request (step S942: be), Memory Controller 200 generates write request (step S943) taking page as basis.In this case, by write request parameter also transmission together.Subsequently, transmission page data (step S944).
In the time that processed page page is afterwards equally within identical page group (step S945: be), variable " b " increases by 1 (step S946), and repeats the processing operation of lower one page.Instantly, when one page is not within identical page group (step S945: no), determine whether to write application of instruction to lower one page group (step S947).
In the time writing application of instruction to lower one page group (step S947: be), variable " p " increases by 1, and will arrange as " 0 " of first number to variable " b " (step S948) to repeat the processing operation of lower one page group.In the time writing application of instruction to lower one page group (step S947: no), treatment step completes.
Note, although can replace the treatment step of implementing each piece parallelly, for convenience's sake, the continuous treatment step of each piece has been described here.
Figure 14 shows according to the process flow diagram of the example of the treatment step of the write request of second embodiment of the invention.The treatment step of this write request is implemented by controller interface circuit 391 and divider 341.
In the time generating write request, be set to variable " b " (step S951) first number relevant with write request.Here, " 0 " is supposed as first number.For variable " b ", set up the value (step S959) that just increases by 1 in the time that the processing of a piece has operated.
In memory cell array 311, if block " b " is not placed in busy state (step S952: no), so, data and address transfer are arrived to memory cell array 311 (step S953), and the write operation (step S954) of begin block " b ".
On the contrary, in memory cell array 311, in the time that piece " b " is placed in busy state (step S952: be), determine whether page buffer 321 is placed in full state (step S955).If page buffer 321 is placed in full state (step S955: be), so, repeat the treatment step after step S952.If page buffer 321 is not placed in full state (step S955: no), so data is remained in page buffer 321, and piece number " b " and address are remained on to (step S956) in page address impact damper 331.Thereafter the dummy status of cancelling page buffer 321, is to be placed on full state (step S957).Bufstat signal is placed in full state by this.
When write request is applied to after processed piece piece time (step S958: be), variable " b " increases by 1 (step S959), and repeats the processing operation of next piece.In the time write request not being applied to next piece (step S958: no), treatment step completes.
Note, although can alternately implement the treatment step of each piece parallelly, for convenience's sake, the continuous treatment step of each piece has been described here.
Figure 15 shows and discharges according to the process flow diagram of the example of the treatment step of the page buffer 321 of second embodiment of the invention.The treatment step that discharges page buffer 321 is implemented by controller interface circuit 391 and divider 341.
In memory cell array 311, process when operation completing writing of any one piece, obtain piece number " e " (the step S961) that has completed this piece of processing operation.In addition, in the time being assigned to the data of piece " e " and being maintained in page buffer 321 (step S962: be), implement step below.
Transmit data from page buffer 321, and from page address impact damper 331 transport addresses (step S963).Subsequently, the full state of cancelling page buffer 321 is to be placed on dummy status (step S964).Bufstat signal is placed in dummy status by this.Thereafter,, in memory cell array 311, operation (step S965) is processed in writing of begin block " e ".
On the contrary, in the time being assigned to the data of piece " e " and not remaining in page buffer 321 (step S962: no), process and operated.
As mentioned above, according to second embodiment of the invention, as long as page buffer 321 is available, in memory cell array 311, even in the time that the pending part page writing is indicated as in busy state, also can continue to write processing operation.
3. the 3rd embodiment
[structure of storer]
Figure 16 shows according to the schematic block diagram of the structure example of the storer 300 of third embodiment of the invention.Storer 300 comprises memory cell array 311, page buffer 321, page address impact damper 331, divider 341, controller interface circuit 392 and busy signal generative circuit 351.Except being equipped with busy signal generative circuit 351, there is almost identical structure according to the storer 300 of third embodiment of the invention and above-mentioned second embodiment of the invention.
Based on Bufstat signal and Busy0 to Busy3 signal, busy signal generative circuit 351 is created on the Busy signal that generates the reference of write request time institute.More specifically, in the time of the full state of Bufstat signal designation, Busy signal is placed in High state (busy state) by busy signal generative circuit 351.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, busy signal generative circuit 351 is placed in Busy signal High state (busy state) too.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, Busy signal is placed in Low state (ready state) by busy signal generative circuit 351.Figure 17 shows the truth table of Busy signal.
Via controller interface circuit 392, the Busy signal being generated by busy signal generative circuit 351 is offered to Memory Controller 200.According to this Busy signal, Memory Controller 200 determines whether to generate the write request of lower one page group.More specifically, if Busy signal is placed in ready state, Memory Controller 200 generates write request so, still, if Busy signal is placed in busy state, does not generate write request.
Third embodiment of the invention comprises busy signal generative circuit 351.Compared to use four signal line in second embodiment of the invention, the 3rd embodiment can only provide Bufstat signal and Busy0 to Busy3 signal via single signal line.In other words, can reduce the signal wire quantity of memory interface 202.
Note, memory cell array 31 is implemented as the function with the memory cell array 311 in above-mentioned functions structure.Part unit buffer 32 is implemented as the function with page buffer 321.In addition, request generating unit 21 is implemented as the function with the Memory Controller 200 in above-mentioned functions structure.In addition, write control part 35 and be implemented as the controller interface circuit 392 that has in above-mentioned functions structure and the function of divider 341.
[time sequential routine]
Figure 18 shows according to the sequential chart of the example in the time sequential routine of third embodiment of the invention.In third embodiment of the invention, busy signal generative circuit 351 generates Busy signal according to Bufstat signal and Busy0 to Busy3 signal.Correspondingly, Memory Controller 200 determines whether generating write request based on Busy signal.
[treatment step]
Figure 19 is the process flow diagram of the example of the treatment step while writing instruction according to the reception of third embodiment of the invention.Treatment step when reception writes instruction is implemented by controller interface circuit 392.
First, the first page number relevant with writing instruction arranged to variable " p " (step S971).For variable " p ", set up the value (step S976) that just increases by 1 in the time that the processing of a page has operated.
By with reference to Bufstat signal and Busy0 to Busy3 signal, busy signal generative circuit 351 generates Busy signal.Subsequently, according to this Busy signal, Memory Controller 200 determines whether to generate write request (step S972).More specifically, in the time of the full state of Bufstat signal designation, because Busy signal rests on busy state, so Memory Controller 200 determines to maintain armed state and do not generate write request.In addition, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, at least both indicate busy state, because Busy signal rests on busy state, so Memory Controller 200 determines too to maintain armed state and do not generate write request.On the other hand, in the time that in Bufstat signal designation dummy status and Busy0 to Busy3 signal, no more than one is indicated busy state, because Busy signal is in ready state, so Memory Controller 200 determines to generate write requests.
While not generating write request when determining to maintain armed state (step S972: no), Memory Controller 200 maintains armed state until meet the condition that generates write request.On the other hand, in the time determining to generate write request (step S972: be), Memory Controller 200 generates write request (step S973) taking page as basis.In this case, by write request parameter also transmission together.Subsequently, transmission page data (step S974).
Similarly, when when writing the page of application of instruction after processed page (step S975: be), variable " p " increases by 1 (step S976) and operates with the processing that repeats lower one page.In the time not writing application of instruction to lower one page (step S975: no), treatment step completes.
Figure 20 shows according to the process flow diagram of the example of the treatment step of the write request of third embodiment of the invention.The treatment step of write request is implemented by controller interface circuit 392 and divider 341.
Generating when write request, by relevant with write request first number arrange to variable " b " (step S981).Here suppose that " 0 " is as first number.For this variable " b ", set up the value (step S989) that just increases by 1 in the time that the processing of a piece has operated.
In memory cell array 311, if block " b " is not placed in busy state (step S982: no), so, data and address transfer are arrived to memory cell array 311 (step S983), and the write operation (step S984) of begin block " b ".
On the contrary, in memory cell array 311, in the time that piece " b " is placed in busy state (step S982: be), determine whether page buffer 321 is placed in full state (step S985).If page buffer 321 is placed in full state (step S985: be), so, repeat the treatment step after step S982.If page buffer 321 is not placed in full state (step S985: no), so, data is remained in page buffer 321, and piece number " b " and address are remained on to (step S986) in page address impact damper 331.Thereafter the dummy status of cancelling page buffer 321, is to be placed on full state (step S987).Bufstat signal is placed in full state by this.
In the time that write request is applied to the piece of following processed piece equally (step S988: be), variable " b " increases by 1 (step S989), and repeats the processing operation of next piece.In the time write request not being applied to next piece (step S988: no), treatment step completes.
Note, although can alternately implement the treatment step of each piece parallelly, for convenience's sake, the continuous treatment step of each piece has been described here.
Figure 21 shows according to the process flow diagram of the example of the treatment step of the release page buffer 321 of third embodiment of the invention.The treatment step of this release page buffer 321 is implemented by controller interface circuit 392 and divider 341.
In memory cell array 311, process when operation completing writing of any one piece, obtain piece number " e " (the step S991) that completes the piece of processing operation.In addition, in the time that the data that are assigned to piece " e " are remained in page buffer 321 (step S992: be), implement following steps.
Transmit data from page buffer 321, and from page address impact damper 331 transport addresses (step S993).Subsequently, the full state of cancelling page buffer 321 is to be placed on dummy status (step S994).Bufstat signal is placed in dummy status by this.Thereafter,, in memory cell array 311, operation (step S995) is processed in writing of begin block " e ".
On the contrary, in the time the data that are assigned to piece " e " not being remained in page buffer 321 (step S992: no), process and operated.
As mentioned above, according to third embodiment of the invention, by be equipped with busy signal generative circuit 351 in polylith structure, can reduce the quantity of the signal wire of memory interface 202.
4. the 4th embodiment
[structure of storer]
Figure 22 shows according to the present invention the schematic block diagram of the structure example of the 4th storer 300 of implementing and Memory Controller 200.In fourth embodiment of the invention, Memory Controller 200 is provided with page buffer 220, page address impact damper 230 and busy signal generative circuit 250.In these parts, the operation of each one is identical with the invention described above the 3rd embodiment.
In sum, according to fourth embodiment of the invention, by the signal wire omitting for Bufstat signal from memory interface 202, can reduce the quantity of the signal wire of memory interface 202.
5. the 5th embodiment
[structure of storer]
Figure 23 shows according to the schematic block diagram of the structure example of the storer 300 of fifth embodiment of the invention.As second embodiment of the invention, storer 300 comprises memory cell array 311, divider 344 and controller interface circuit 394.But, exception, storer 300 also comprises respectively two page buffer A322 and B323 and corresponding page address impact damper A332 and B333.
In fifth embodiment of the invention, be different from second embodiment of the invention, improve the delay of the processing being caused by the busy state of piece in operating by increasing the capacity of page buffer.The quantity of the needed page buffer of maintenance energy depends on the variation characteristic that writes the rush hour of paid close attention to storer.Originally exemplify the structure under following prerequisite, that is, suppose that, in the time that writing of four pieces of enforcement processed operation, the rush hour that writes of no more than two pieces increases.
As mentioned above, according to fifth embodiment of the invention, by increasing the capacity of page buffer, can improve the delay of the processing being caused by the busy state of piece in operating.
6. the 6th embodiment
[structure of storer]
Figure 24 shows according to the schematic block diagram of the structure example of the storer 300 of sixth embodiment of the invention.In storer 300, memory cell array is divided into two memory cell arrays, be memory cell array 312 and memory cell array 313, wherein, each memory cell array comprises page buffer (page buffer A322 or page buffer B323), page address impact damper (page address impact damper A332 or page address impact damper B333) and divider (divider 342 or divider 343).
Although in sixth embodiment of the invention, the capacity that increase page buffer the same as fifth embodiment of the invention,, the quantity that is connected to the memory cell block array of page buffer by restriction makes arranging on chip become easy.
As can be seen from the above, according to above-mentioned exemplary embodiment of the present invention, by part unit buffer 32 (subpage impact damper 320 and page buffer 321 etc.) is set, operate even if also continue as much as possible the in the situation that of being indicated as in busy state in the part unit of writing to write to process.This can improve the deteriorated of the write performance that caused by the random variation of the rush hour.
Note, above-described embodiment has provided for implementing example of the present invention, and element in content and claims in embodiment is about having each other corresponding relation.Similarly, the element in claims and there is content in the exemplary embodiment of identical name about thering is each other corresponding relation with those elements.But the present invention is not limited to above-described embodiment, but can change to implement by the difference that is given in the embodiment in the scope of its essence.
In addition, the treatment step illustrating in the above embodiment of the present invention can be considered to have the method for one group of these step, or can be considered to for make calculate and operation one group of these step program or for storing the recording medium of this program.For example, can use compact disk (Compact Disc, CD), minidisk (MiniDisc, MD), Digital versatile disc (Digital Versatile Disc, DVD), storage card and Blu-ray Disc (registered trademark) etc. are as recording medium.
Moreover any possibility combination of some or all embodiment in the various embodiment that illustrate and comprise has been contained in the present invention here here.
From above-mentioned disclosed exemplary embodiment, can realize at least following structure.
(1) a memory controller part, it comprises:
Part unit buffer, it is for keeping being assigned at least one data of part unit, and the unit of writing of storer is divided into multiple described part units; And
Request generating unit, even if it indicates arbitrary described part unit in busy state for described storer, can keep being assigned to the data of this part unit in described part unit buffer, still generate the write request of the said write unit of described storer.
(2) according to the memory controller part of (1), it also comprises:
Write control part, it for making described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described storer in the case of the generation of said write request.
(3) according to the memory controller part of (2), wherein, in the time that the subsequent data that is assigned to the part unit that cancels busy state is maintained in described part unit buffer, said write control part is transferred to described storer by described subsequent data from described part unit buffer.
(4) according to any one in (1) to (3) memory controller part, it also comprises:
Signal generating unit, it is for generating signal, and described signal is used for:
Be designated as the part unit in busy state when existing by described storer, and described part unit buffer be can not keep being assigned to the data of this part unit time, instruction disarmed state;
When described part unit buffer is in dummy status, and there is not while being designated as the part unit in busy state by described storer instruction effective status; And
Be designated as the part unit in busy state when existing by described storer, and described part unit buffer be can keep the data of this part unit time, instruction effective status,
Wherein, in the time of described signal designation effective status, described request generating unit generates the said write request of said write unit.
(5) according to any one in (1) to (4) memory controller part, wherein, described part unit buffer keeps being assigned to multiple data of described part unit.
(6) memory device, it comprises:
Memory cell array, the unit of writing of described memory cell array is divided into multiple part units with storage data;
Part unit buffer, it is for keeping being assigned at least one data of described part unit;
Request generating unit, even if it indicates arbitrary described part unit in busy state for described storer, can keep being assigned to the data of this part unit in described part unit buffer, still generate the write request of the said write unit of described memory cell array; And
Write control part, it is in the case of the generation of said write request, make described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described memory cell array.
(7) according to the memory device of (6), wherein, described memory cell array comprises the memory cell with non-volatile memory device.
(8) information handling system, it comprises:
Memory cell array, the unit of writing of described memory cell array is divided into multiple part units with storage data;
Host computer, it is for sending the instruction that writes of said write unit;
Part unit buffer, it is for keeping being assigned at least one data of described part unit;
Request generating unit, the in the situation that it sending in said write instruction, even in busy state, still generate the write request of the said write unit of described memory cell array for the arbitrary described part unit of described storer instruction the data that can keep being assigned to this part unit in described part unit buffer; And
Write control part, it is in the case of the generation of said write request, make described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described memory cell array.
(9) storage controlling method, it comprises:
Even if storer instruction is by dividing arbitrary part unit in the part unit forming in busy state to the unit of writing of storer, the data that can keep being assigned to this part unit in part unit buffer, still generate the write request of the said write unit of described storer; And
In the case of the generation of said write request, execution writes control, so that described part unit buffer keeps being assigned to the data that are indicated as the part unit in busy state, and will be assigned to the data transmission that is not indicated as the part unit in described busy state to described storer.
It will be understood by those of skill in the art that within the scope of appended claim and equivalent thereof, can occur that according to designing requirement and other factors different variation, merging, son merge and change.
The application requires the formerly rights and interests of patented claim JP2013-045125 of Japan of submitting on March 7th, 2013, and its full content mode is by reference integrated with herein.

Claims (12)

1. a memory controller part, it comprises:
Part unit buffer, it is for keeping being assigned at least one data of part unit, and the unit of writing of storer is divided into multiple described part units; And
Request generating unit, even if it indicates arbitrary described part unit in busy state for described storer, can keep being assigned to the data of this part unit in described part unit buffer, still generate the write request of the said write unit of described storer.
2. memory controller part according to claim 1, it also comprises:
Write control part, it for making described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described storer in the case of the generation of said write request.
3. memory controller part according to claim 2, wherein, in the time that the subsequent data that is assigned to the part unit that cancels busy state is maintained in described part unit buffer, said write control part is transferred to described storer by described subsequent data from described part unit buffer.
4. according to the described memory controller part described in any one in claim 1-3, it also comprises:
Signal generating unit, it is for generating signal, and described signal is used for:
Be designated as the part unit in busy state when existing by described storer, and described part unit buffer be can not keep being assigned to the data of this part unit time, instruction disarmed state;
When described part unit buffer is in dummy status, and there is not while being designated as the part unit in busy state by described storer instruction effective status; And
Be designated as the part unit in busy state when existing by described storer, and described part unit buffer be can keep the data of this part unit time, instruction effective status,
Wherein, in the time of described signal designation effective status, described request generating unit generates the said write request of said write unit.
5. according to the memory controller part described in any one in claim 1-3, wherein, described part unit buffer keeps being assigned to multiple data of described part unit.
6. a memory device, it comprises:
Memory cell array, the unit of writing of described memory cell array is divided into multiple part units with storage data;
Part unit buffer, it is for keeping being assigned at least one data of described part unit;
Request generating unit, even if it indicates arbitrary described part unit in busy state for described storer, can keep being assigned to the data of this part unit in described part unit buffer, still generate the write request of the said write unit of described memory cell array; And
Write control part, it is in the case of the generation of said write request, make described part unit buffer keep being assigned to the data that are designated as the part unit in busy state by described storer, and will be assigned to the data transmission that is not designated as the part unit in busy state by described storer to described memory cell array.
7. memory device according to claim 6, wherein, in the time that the subsequent data that is assigned to the part unit that cancels busy state is maintained in described part unit buffer, said write control part is transferred to described memory cell array by described subsequent data from described part unit buffer.
8. according to the described memory device described in claim 6 or 7, it also comprises:
Signal generating unit, it is for generating signal, and described signal is used for:
Be designated as the part unit in busy state when existing by described memory cell array, and described part unit buffer be can not keep being assigned to the data of this part unit time, instruction busy state;
When described part unit buffer is in dummy status, and there is not while being designated as the part unit in busy state by described memory cell array instruction ready state; And
When existing while being designated as the part unit in busy state by described memory cell array, and described part unit buffer be can keep the data of this part unit time, instruction ready state,
Wherein, in the time of described signal designation ready state, described request generating unit generates the said write request of said write unit.
9. according to the memory device described in claim 6 or 7, wherein, described part unit buffer keeps being assigned to multiple data of described part unit.
10. according to the memory device described in claim 6 or 7, wherein, described memory cell array comprises the memory cell with non-volatile memory device.
11. 1 kinds of information handling systems, it comprises:
Memory device in claim 6-10 described in any one; With
Host computer, it is for sending the instruction that writes of said write unit to described memory device.
12. 1 kinds of storage controlling methods, it comprises:
Even if storer instruction is by dividing arbitrary part unit in the part unit forming in busy state to the unit of writing of storer, the data that can keep being assigned to this part unit in part unit buffer, still generate the write request of the said write unit of described storer; And
In the case of the generation of said write request, execution writes control, so that described part unit buffer keeps being assigned to the data that are indicated as the part unit in busy state, and will be assigned to the data transmission that is not indicated as the part unit in described busy state to described storer.
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