CN103197898A

CN103197898A - Storage control device, storage device, and control method for controlling storage control device

Info

Publication number: CN103197898A
Application number: CN201310009350XA
Authority: CN
Inventors: 大久保英明; 筒井敬一; 中西健一; 足立直大
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2012-01-10
Filing date: 2013-01-10
Publication date: 2013-07-10
Anticipated expiration: 2033-01-10
Also published as: US20130179646A1; US9043541B2; JP2013142947A; CN103197898B

Abstract

A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read.

Description

The control method of memory control device, memory storage and control store control device

Technical field

The disclosure relates to memory control device.More specifically, the disclosure relates to memory control device, the memory storage that a kind of control has two storage blocks of different access times and is used for the control method of the described memory control device of control.

Background technology

In the past, some memory storage formations that made up two storage blocks with different access times have the high capacity storage device of the access time (delay) that reduces.For example, flash memory is as a storage block that has the shorter access time (the low delay), and hard disk drive (HDD) is as having another storage block of live forever the time of getting (high latency).In another example, the NVRAM(nonvolatile RAM) postpone storage block as low, and flash memory is as the high latency storage block.Have in combination under the situation of storage block of different access times, the low storage block that postpones has the capacity more less than high latency storage block usually, because low to postpone storage block higher than the every cell capability cost of high latency storage block usually.

Waited to write combinations thereof in data under the situation of memory storage of the storage block with different access times, this memory storage need determine which in the storage block institute's focused data wait to write.About determining of the destination of writing data, the high priority data that has proposed to have high frequency of access is write the low method (for example, seeing Japanese Patent Laid publication number 2009-205335) that postpones storage block.The method that proposes intention is in the access time that reduces whole memory storage when wherein fetching the data with high frequency of access.

Summary of the invention

Yet, again under the situation of above-mentioned prior art, be difficult to promote the quantity (, handling capacity) of time per unit sense data when consuming the access time sometimes.For example, if data item has been write all places in the memory storage, then may considerably less data item be written to the low storage block that postpones.In the case, read the time of data to the time of beginning sense data the high latency storage block from finishing Zi the low storage block that postpones, may be through the free time of an elongated segment.So may make handling capacity reduce corresponding amount of described free time.And, if exist a lot of data item to be written to the low storage block that postpones, this means the use that may be wasted of the low capacity that postpones storage block.As under the unsuitable situation of quantity of writing the low data item that postpones storage block as seen, the risk of existence is that the be wasted handling capacity of use or whole memory storage of the low capacity that postpones storage block is not substantially improved.

The disclosure is made in view of above situation, and a kind of technology is provided, and this technology is used for promoting the efficient capacity that uses this memory storage of handling capacity while of whole memory storage.

According to an embodiment of the present disclosure, the control method that a kind of memory control device is provided and is used for it.This memory control device comprises: write-in block, be arranged so that: given a kind of low speed access storage block with access time longer than the access time of zero access storage block, the described access time is time to the time that described data are read from the request of issue read data, the said write piece is established as the zero access data counts, and described zero access data counts is by the quantity of the readable data of described zero access storage block in corresponding to the time period of access time of described low speed access storage block; The said write piece further writes, if a plurality of data wait to write described high speed and described low speed access storage block, then with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data; With read piece, be arranged so that: treat from wherein reading if write described a plurality of data of described low speed and described zero access storage block, then described read piece issue request to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to begin to read described low speed access data after described zero access data have been read out.According to the memory control device of above general introduction and the control method that is used for it, wherein, when a plurality of data are to be written, zero access storage block as described in will writing as the as many zero access data of zero access data counts, and will remain the low speed access data and write described low speed access storage block.Wherein, when a plurality of data were to be read, the issue request was to read described zero access data and low speed access data from these pieces.

Preferably, memory control device of the present disclosure also can comprise the management information storage block that is configured to management information, and described management information is obtained for the zero access address that has been written into the place from described zero access data and treated that the described low speed access data that read first have been written into the low speed access start address at place.If described zero access data are treated to be read from described zero access address, then described read piece can issue the request to described zero access storage block to read described zero access data, the described piece that reads further obtains described low speed access start address based on described management information, described read piece further issue the request to described low speed access storage block to read described low speed access data from described low speed access start address.This preferred structure makes described low speed access start address to obtain from described zero access address.

Preferably, above-mentioned management block information memory can be stored as described management information with the relative position relation between each zero access address and the described low speed access start address.When reading described zero access data from any of described zero access address, the described piece that reads can be from the zero access address of touching upon with from obtaining described low speed access start address corresponding to the described management information of described zero access address.This preferred structure makes described low speed access start address to obtain from the relative position relation between described zero access address and the described low speed access start address and from described zero access address.

Preferably, above-mentioned read the piece request of can issuing simultaneously to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to read described low speed access data.This preferred structure allows that issue request simultaneously is to read described zero access data and issue request to read described low speed access data.

Preferably, if utilize instruction to specify described zero access data counts to write described a plurality of data, then above-mentioned write-in block can write described a plurality of data when setting up specified zero access data counts.This preferred structure makes that specified zero access data counts can be set up.

Preferably, if utilizing described instruction indicates to write: being written into data will be afterwards to read at a high speed, then above-mentioned write-in block can be write described zero access storage block as described zero access data with as many data of zero access data counts as described, simultaneously remaining data is write described low speed access storage block as described low speed access data.According to this preferred structure,, then the zero access data in the described data are write described zero access storage block, and the low speed access data are write described low speed access storage block afterwards to read at a high speed if indication writes data.

According to another one embodiment of the present disclosure, a kind of memory storage is provided, comprising: the zero access storage block; The low speed access storage block is configured to have the access time longer than the access time of described zero access storage block, and the described access time is time to the time that described data are read out from the request of issue read data; And memory control device, comprise: write-in block, be configured to be established as the zero access data counts, described zero access data counts is by the quantity of the readable data of described zero access storage block in corresponding to the time period of access time of described low speed access storage block, the said write piece further writes, if a plurality of data wait to write described high speed and described low speed access storage block, then with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data; With read piece, be arranged so that: treat from wherein reading if write described a plurality of data of described low speed and described zero access storage block, then described read piece issue request to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to begin to read described low speed access data after described zero access data have been read out.According to the memory storage of above general introduction, wherein, when a plurality of data are to be written, zero access storage block as described in will writing as the as many zero access data of zero access data counts, and will remain the low speed access data and write described low speed access storage block.Wherein, when a plurality of data are to be read, will be published to these storage blocks in order to the request of reading described zero access data with in order to the request of reading described low speed access data.

According to the disclosure technology that the above advantageous effects of summarizing is provided, can take full advantage of the handling capacity that the capacity of memory storage is promoted whole memory storage simultaneously.

Description of drawings

Fig. 1 is the block diagram of Typical Disposition that the information handling system of disclosure embodiment is shown;

Fig. 2 is the block diagram that illustrates as the concrete structure of the storage control unit of the part of this embodiment;

Fig. 3 is the block diagram that illustrates as the typical structure of the storage control unit of the part of this embodiment;

Fig. 4 is the block diagram that illustrates as the typical structure of the NVRAM of the part of this embodiment;

Fig. 5 A and Fig. 5 B are the synoptic diagram that illustrates by the set canonical parameter of the order that is used for this embodiment;

Fig. 6 A and Fig. 6 B are the synoptic diagram of typical structure that illustrates for the page or leaf of this embodiment;

Fig. 7 is the tabular drawing that illustrates for the sector address conversion table of this embodiment;

Fig. 8 is the tabular drawing that illustrates for the typical NVRAM page address conversion table of this embodiment;

Fig. 9 is the tabular drawing that illustrates for the typical flash memory physical address admin table of this embodiment;

Figure 10 is the tabular drawing that illustrates for the typical NVRAM physical address admin table of this embodiment;

Figure 11 is the block diagram that illustrates as the typical structure of the data write-in block of the part of this embodiment;

Figure 12 is the block diagram that illustrates as the typical structure of the data read piece of the part of this embodiment;

Figure 13 is the performed sequence chart of reading to handle of this embodiment;

Figure 14 is the sequential chart of the sequential of the performed data transfer of this embodiment of explanation;

Figure 15 illustrates the performed process flow diagram of typically writing processing of this embodiment;

Figure 16 be illustrate this embodiment performed typically read the process flow diagram handled;

Figure 17 illustrates the process flow diagram that the performed typical NVRAM of this embodiment reads to handle;

Figure 18 illustrates the process flow diagram that the performed typical flash memory of this embodiment is read to handle;

Figure 19 is illustrated in the tabular drawing that data are write the typical sector address conversion table that comes into force before the flash memory as the part of this embodiment;

Figure 20 is illustrated in the tabular drawing that data are write the typical sector address conversion table that comes into force after the flash memory as the part of this embodiment;

Figure 21 is illustrated in the tabular drawing that data are write the typical sector address conversion table that comes into force before the NVRAM as the part of this embodiment;

Figure 22 is illustrated in the tabular drawing that data are write the typical sector address conversion table that comes into force after the NVRAM as the part of this embodiment; With

Figure 23 is the synoptic diagram that illustrates for the write order of the variation of this embodiment canonical parameter to be arranged.

Embodiment

Some preferred embodiments (hereinafter referred is embodiment) of disclosure technology are described below.This description is by providing with lower banner:

1. first embodiment (data of predetermined quantity are write NVRAM, and remaining data is write the example of flash memory)

2. variation

＜1. first embodiment 〉

[Typical Disposition of information handling system]

Fig. 1 is the block diagram of Typical Disposition that the information handling system of disclosure embodiment is shown.This information handling system writes and reads data during information processing.This information handling system comprises principal computer 100 and data storage device 200.

In information processing, principal computer 100 is write data storage device 200 with data and is read the data that write from data storage device 200.

When writing data, principal computer 100 is exported write order to data storage device 20 via signal wire 109 together with writing data.The replying this write order that principal computer 100 receives from data storage device 200 via signal wire 109 then.When read data, principal computer 100 arrives data storage device 200 via signal wire 109 output read commands.Principal computer 100 then via signal wire 109 receive to this read command reply and from the read data of data storage device 200.Here, suppose and data are write data storage device 200 or read by carrying out such as the unit of 512 bytes from data storage device 200.For data storage device 200, the data in each access unit (512 byte) will be called " section (sector) " hereinafter.

Data storage device 200 is write data and is read the data that write under the control of principal computer 100.Data storage device 200 comprises: storage control unit 300 and two storage blocks with different read access (read access) time.Here, the described read access time be from request be published to described storage block with time of reading data to touched upon data from time period of time of wherein reading.For example, the storage block with shorter access time can be NVRAM400, and to have the storage block of the time of getting of living forever can be flash memory 500.

The combination of described storage block is not limited to the combination of NVRAM400 and flash memory 500; But use capable of being combined some have other storage block of different access times.For example, data storage device 200 can adopt flash memory as the storage block with short relatively access time, and adopts hard disk drive (HDD) as having the storage block of the time of getting of living forever relatively.Can notice, data storage device 200 is examples of the memory storage described in the claim, NVRAM400 is the example of the zero access storage block described in the claim, and flash memory 500 is examples of the low speed access storage block described in the claim.

Under the control of principal computer 100, storage control unit 300 is write NVRAM400 and flash memory 500 with data or from wherein reading the data that write.When receiving indication to the write order that writes of the data that comprise a plurality of sections, storage control unit 300 is write NVRAM400 via signal wire 308 outputs with (for example, 3) section of the predetermined quantity of described data.Storage control unit 300 is write flash memory 500 via signal wire 309 with the residue section of described data.When receiving read command, storage control unit 300 is issued simultaneously and is read request to NVRAM400 and flash memory 500.Storage control unit 300 receives the read data from NVRAM400 and flash memory 500, and this read data is outputed to principal computer 100.

Here, the quantity of having write the section of NVRAM400 will be called " the continuous section counting of NVRAM " hereinafter.The continuous section of described NVRAM counting is the quantity of the section that can read from NVRAM400 in during corresponding to the time period of access time of flash memory 500.The continuous section of NVRAM counting can be obtained by the handling capacity of access time of access time of NVRAM400, flash memory 500 and NVRAM400.Described handling capacity is illustrated in the quantity of the data (section) that read in the time per unit of access time.The occurrence of described access time and handling capacity will be discussed in company with the method for obtaining the continuous section counting of described NVRAM based on these values later together.It may be noted that the continuous section of described NVRAM counting is the example of the zero access data counts described in the claim.

Data can be write NVRAM400 and flash memory 500 or therefrom read under the control of storage control unit 300.Here supposition except error correcting code (ECC), writes and reads data from NVRAM400 by the unit of 256 bytes.In description subsequently, for NVRAM400, the data in the access unit (256 byte) will be called " NVRAM page or leaf ".On the other hand, suppose except error correcting code, write and read data from flash memory 500 by the unit of eight sections.In description subsequently, will be called " flash memory page or leaf " for the data in 500, one access units of flash memory (512 * 8 byte).

[typical structure of data storage device]

Fig. 2 is the block diagram that illustrates as the concrete structure of the storage control unit 300 of the part of this embodiment.Storage control unit 300 comprises: processor 311, RAM312, error correction process piece 313, ROM(ROM (read-only memory)) 314 and bus 315.Storage control unit 300 also comprises: host interface 316, NVRAM interface 317 and flash memory interface 318.

Processor 311 is control store control module 300 on the whole.The interim storage of processor 311 of RAM312 required data during its processing.Error correction process piece 313 adds error correcting code to data to be written, and is corrected in based on described error correcting code that read can detectable mistake in the data.The program by processor 311 execution is treated in the ROM314 storage.

Bus 315 provides common path, and processor 311, RAM312, error correction process piece 313, ROM314, host interface 316, NVRAM interface 317 and flash memory interface 318 are via this common path swap data betwixt.

Host interface 316 and principal computer 100 swap datas and order.NVRAM interface 317 and NVRAM400 swap data and request.Flash memory interface 318 and flash memory 500 swap datas and request.

Fig. 3 is the block diagram that illustrates as the typical structure of the storage control unit 300 of the part of this embodiment.Storage control unit 300 comprises data write-in block 320 and data read piece 370.Storage control unit 300 also comprises: sector address conversion table 330, NVRAM page address conversion table 340, flash memory physical address admin table 350 and NVRAM physical address admin table 360.For example, data write-in block 320 and data read piece 370 can utilize the processor 311 shown in Fig. 2, RAM312, error correction process piece 313 and ROM314 to implement.Described table can remain on such as among the RAM312 shown in Figure 2.

Sector address conversion table 330 is associated logical address with physical address in the flash memory 500.Each is assigned to a section in the data storage device 200 described logical address.Each is assigned to a section in the flash memory 500 described physical address.The RAM312 that it may be noted that maintenance sector address conversion table 330 is the example of the management information storage block described in the claim.

NVRAM page address conversion table 340 is associated logical address with physical address among the NVRAM400.Each is assigned to one page NVRAM page or leaf (1/2 section) among the NVRAM400 described physical address.

Flash memory physical address admin table 350 holds the state of each physical address in the flash memory 500.NVRAM physical address admin table 360 holds the state of each physical address among the NVRAM400.Described state can be following three types any for example: " in the use ", " free time " and " bad ".Described " in the use " state is the states of data when writing the physical address of touching upon; Described " free time " state is the state when not having data to write described physical address; Described " bad " state is because certain reason data can not be write described physical address or from its state that reads.

Data write-in block 320 is write data NVRAM400 and flash memory 500 under the control of principal computer 100.When receiving from the write order of principal computer 100 and writing data, data write-in block 320 with reference to described table converting physical address to by the logical address of described write order appointment.Data write-in block 320 is proceeded write data to be write described physical address and is upgraded described table.It may be noted that data write-in block 320 is examples of the write-in block described in the claim.Data write-in block 320 is performed writes processing and will discuss in more detail later.

Data read piece 370 reads data from NVRAM400 and flash memory 500 under the control of principal computer 100.When the read command that receives from principal computer 100, data read piece 370 with reference to described table converting physical address to by the logical address of described read command appointment.Data read piece 370 will specify the read request of physical address to be published to each of NVRAM400 and flash memory 500 simultaneously then.After the read data that receives from NVRAM400 and flash memory 500, data read piece 370 outputs to principal computer 100 with this read data.It may be noted that data read piece 370 is the examples that read piece described in the claim.370 performed the reading of data read piece are handled and will be discussed in more detail later.

[typical structure of NVRAM]

Fig. 4 is the block diagram that illustrates as the typical structure of the NVRAM400 of the part of this embodiment.NVRAM400 comprises: interface 410, memory control block 420, address decoder 430, cache register 440, data register 450 and memory array 460.Flash memory 500 has the structure roughly the same with NVRAM400.

Interface 410 and memory control block 300 exchange request and data.

Memory control block 420 is controlled NVRAM400 on the whole.When receiving write request via interface 410, memory control block 420 physical address that this write request is specified outputs to the address decoder 430 for decoding, and receives this decoded results from address decoder 430.In addition, memory control block 420 control cache registers 440 keep from what storage control unit 300 shifted writing data (1/2 section).If data can be transferred to data register 450, then memory control block 420 control cache registers 440 will be transferred to data register 450 from the data of writing that storage control unit 300 receives.In addition, memory control block 420 control data registers 450 keep from what cache register 440 shifted writing data (1/2 section) and the data of writing of touching upon being write memory array 460.

Here, but two processing of memory control block 420 executed in parallel: a processing is will receive from the data of storage control unit 300 in the cache register 440 therein; A processing is therein data to be write data register 450(namely, so-called " staggered (interleave) operation ").Utilize this feature, NVRAM400 can receive data next to be written from storage control unit 300 when writing data.

Simultaneously, when receiving read request via interface 410, memory control block 420 physical address that this read request is specified outputs to the address decoder 430 for decoding, and receives this decoded results from address decoder 430.In addition, memory control block 420 is controlled the read data (1/2 section) that data registers 450 maintenances are read from memory array 460.If data can be transferred to cache register 440, then memory control block 420 control data registers 450 will be transferred to cache register 440 from this read data that memory array 460 reads.In addition, memory control block 420 control cache registers 440 keep from this read data (1/2 section) of data register 450 transfers and via interface 410 this read data being outputed to storage control unit 300.

Here, but also two processing of executed in parallel of memory control block 420: a processing is data to be read in the data register 450 therein; A processing is to export data to storage control unit 300(functional interleaving from cache register 440 therein).Utilize this feature, NVRAM400 can read next step data to be exported from memory array 460 when read data is outputed to storage control unit 300.

Shifting this time period that becomes the possible time from time of read request issue to read data will be called " busy period " hereinafter.Suppose: it is very short to shift the used time of read data between cache register 440 and data register 450, and it is also very short to shift the required time of read request between storage control unit 300 and NVRAM400.Do not consider these times, then the time from the read request issue is read into this time period of the time the data register 450 corresponding to described " busy period " to the NVRAM page or leaf.

The physical address that address decoder 430 decodings receive from memory control block 420, and based on this decoded results, enable the suitable memory cell in the memory array 460.In addition, address decoder 430 outputs to memory control block 420 with this decoded results.

Cache register 440 interim maintenances are treated to output to the data of storage control unit 300 or the data that receive from storage control unit 300 via interface 410.Data register 450 interim maintenances wait to write the data of memory array 460 or the data that read from memory array 460.Cache register 440 and data register 450 utilize the many signal line interconnection corresponding to the size of NVRAM page or leaf.For example, if the size of NVRAM page or leaf is 265 bytes, the parallel transfer signal line that then uses quantity as 265 * 8 is with register as described in connecting.This connection allows that the high-speed data between cache register 440 and the data register 450 shifts.

Memory array 460 is made of a plurality of memory cells with the arrangement of two-dimensional grid pattern.Each memory cell keeps the data of pre-sizing.

Fig. 5 A and Fig. 5 B are the synoptic diagram that illustrates for the set canonical parameter of the order of this embodiment.Fig. 5 A illustrates the set canonical parameter of write order.This parameter to be arranged can comprise: first logical address, size of data and high speed specified sign HF.Described first logical address is first of the target logical address that is used to write data.Described size of data can represent for example to write the quantity of the section of data.

Described high speed specified sign HF specifies whether to write the sign that data make that these data can read with high speed afterwards.For example, if data are to be written to read at a high speed, then high speed specified sign HF to be arranged to T(true); Otherwise this high speed specified sign HF is arranged to the F(vacation).Be arranged under the situation of T at high speed specified sign HF, storage control unit 300 will be write NVRAM400 as the as many section of writing data of the continuous section counting of NVRAM, and this residue section of writing data is write flash memory 500.Be arranged under the situation of F at high speed specified sign HF, storage control unit 300 will all be write data and write flash memory 500.

Make that described data can be afterwards to read at a high speed though whether this embodiment is configured to use high speed specified sign HF to specify writes data, the disclosure is not limited thereto.Alternately, the available special-purpose write order (hereinafter referred to as " specifying write order at a high speed ") that is different from common write order carries out described appointment.In the case, storage control unit 300 only need verify whether this write order is for specifying write order at a high speed, to determine whether that data are write NVRAM400.

Fig. 5 B illustrates for the set canonical parameter of the read command of this embodiment.This parameter to be arranged can comprise: first logical address and size of data.Described first logical address is first of the target logical address that reads that is used for data.Described size of data can be indicated for example quantity of the section of read data.

Fig. 6 A and Fig. 6 B are the synoptic diagram of typical structure that illustrates for the page or leaf of this embodiment.Fig. 6 A illustrates the typical structure of NVRAM page or leaf.For example, the NVRAM page or leaf can be 265 byte datas that the error correcting code (ECC) of 256 byte datas and 9 bytes constitutes.Fig. 6 B illustrates the typical structure of flash memory page or leaf.For example, the flash memory page or leaf can be 4,320 byte datas that are made of eight 540 byte data items.Each 540 byte data item is made of 512 byte datas (section) and 28 byte error correcting codes.

Fig. 7 is the tabular drawing that illustrates for the typical segment address translation table 330 of this embodiment.This sector address conversion table 330 holds the section management information about each logical address.This section management information comprises: the continuous section counting of flash memory physical address, physical address skew, enabler flags, NVRAM sign, NVRAM section number and NVRAM.

Described flash memory physical address is the physical address that is assigned to the logical address in the flash memory 500.Described each physical address of physical address skew indication is with reference to the relative position of the given physical address in the flash memory page or leaf.For example, if the flash memory page or leaf is made of eight sections, the value 0 to 7 that then provides with the sexadecimal mark is offset as described physical address.

Described enabler flags is to specify physical address assignments in NVRAM400 whether or the flash memory 500 to the sign of logical address.For example, if physical address assignments to logical address, then this enabler flags to be arranged to T(true); If do not have physical address assignments to logical address, then enabler flags is arranged to the F(vacation).

Described NVRAM sign is to specify physical address assignments among the NVRAM400 whether to the sign of logical address.For example, if the physical address assignments among the NVRAM400 to logical address, then NVRAM sign to be arranged to T(true); If do not have physical address assignments among the NVRAM400 to logical address, then the NVRAM sign is arranged to the F(vacation).

Described NVRAM section number indicates each logical address with reference to the relative position of first logical address among the NVRAM400.For example, if the continuous section of NVRAM counting is 3, then provide value 0 to 2 with the sexadecimal mark as NVRAM section number.The continuous section count table of described NVRAM shows the quantity of the section for the treatment of to write continuously NVRAM400.

By reference NVRAM section number and the continuous section counting of NVRAM, data read piece 370 can obtain to read first from flash memory 500 logical address (described address is called " beginning logical address " hereinafter) at data place easily.Particularly, data read piece 370 can utilize following formula 1 to calculate described beginning logical address:

(beginning logical address)=(first logical address)+(the continuous section counting of NVRAM)-(NVRAM section number) ... (expression formula 1)

Without recourse to above expression formula 1, thereby also can obtain described beginning logical address by the NVRAM sign with reference to each logical address.Yet if the continuous section counting of NVRAM is big quantity, the described calculating of execution may need to take time.Count to get under the situation of expression at NVRAM section number and the continuous section of NVRAM, described beginning logical address can be calculated by these numbers.This feasible expense that can reduce software.

Though storage control unit 300 is configured to obtain the beginning logical address from NVRAM section number and the continuous section counting of NVRAM, other method also can be used for obtaining the beginning logical address.For example, when writing data, it is true that storage control unit 300 can be masked as T(with described beginning logical address self and NVRAM) logical address represent explicitly; When reading described data, storage control unit 300 can read this and begins logical address.

Fig. 8 is the tabular drawing that illustrates for the typical NVRAM page address conversion table 340 of this embodiment.NVRAM page address conversion table 340 holds logical address skew and about the NVRAM page management information of each logical address.Described NVRAM page management information comprises: NVRAM physical address, Physical Page number and continuous physical page or leaf counting.

Described each logical address of logical address skew indication is with reference to the relative position of the given logical address in the section.For example, if a section is divided into two NVRAM pages or leaves, the

value

0 or 1 that then provides with the sexadecimal mark is offset as logical address.

Described NVRAM physical address is the physical address that is assigned to the address of being determined by logical address and logical address skew.The counting expression of NVRAM continuous physical page or leaf treats to write continuously the quantity of the NVRAM page or leaf of NVRAM400.NVRAM continuous physical page or leaf counting utilizes following formula 2 and determines:

(NVRAM continuous physical page or leaf counting)=(the continuous section counting of NVRAM) * (sector sizes)/(NVRAM page or leaf size) ... (expression formula 2)

In expression formula 2, each is the size of data that does not comprise error correcting code for sector sizes and NVRAM page or leaf size.For example, if the continuous section of NVRAM counting is 3, sector sizes is 512 bytes, and NVRAM page or leaf size is 256 bytes, and then NVRAM continuous physical page or leaf counting is defined as 6 based on above expression formula 2.Described Physical Page number indicates each NVRAM page or leaf with reference to the relative position of given NVRAM page or leaf.For example, if NVRAM continuous physical page or leaf counting is 6, then provide value 0 to 5 with the sexadecimal mark as the Physical Page number.

Fig. 9 is the tabular drawing that illustrates for the typical flash memory physical address admin table 350 of this embodiment.Flash memory physical address admin table 350 holds the state of each flash memory physical address.Described flash memory physical address is the physical address in the flash memory 500.Described state can be following three types any for example: " in the use ", " free time " and " bad ".

Figure 10 is the tabular drawing that illustrates for the typical NVRAM physical address admin table 360 of this embodiment.NVRAM physical address admin table 360 holds the state of each NVRAM physical address.Described NVRAM physical address is the physical address among the NVRAM400.Described state can be following three types any for example: " in the use ", " free time " and " bad ".

[typical structure of data write-in block]

Figure 11 is the block diagram that illustrates as the typical structure of the data write-in block 320 of the part of this embodiment.Data write-in block 320 comprises: order analysis part 321, write destination determining section 322, data write request part 323 and Biao Geng new portion 324.

Order analysis part 321 is analyzed described write order.Based on the result of this analysis, first physical address and size of data that order analysis part 321 is specified with this write order output to data write request part 323.In addition, order analysis part 321 size of data that this write order is specified and high speed specified sign output to and write destination determining section 322.

Write destination determining section 322 and determine that in NVRAM400 and the flash memory 500 which is the destination of writing data.Write destination determining section 322 and receive size of data and high speed specified sign from order analysis part 321, and reply from 323 receptions of data write request part.

If the high speed specified sign is arranged to F, then writes destination determining section 322 and determine flash memories 500 for writing the destination, and the result of this destination is outputed to data write request part 323.

On the other hand, if the high speed specified sign is arranged to T, then write destination determining section 322 determine NVRAM400 be described size of data indicated count the destination that as many section is written into as the continuous section of NVRAM, and the result of this destination is outputed to data write request part 323.Write the destination that destination determining section 322 determines that flash memory 500 is written into for the residue section then, and the result of this destination is outputed to data write request part 323.Section to be written obtains from replying of data write request part 323 outputs by writing 322 calculating of destination determining section with respect to the initial position of first section.

Data write request part 323 is write NVRAM400 or flash memory 500 with data.Data write request part 323 receives first logical address and size of data from order analysis part 321, and writes data from principal computer 100 receptions.In addition, data write request part 323 is write the result that the destination is determined from writing 322 receptions of destination determining section.Data write request part 323 will be connected in the as many logical address of size of data as described of first logical address and take it is the address that writes that target is used for data as.According to from the definite result who writes destination determining section 322, data write request part 323 determines to be used for corresponding to target the physical addresss of the logical address that writes of data.

If NVRAM400 is for writing the destination, then data write request part 323 is divided into each section the unit of 256 bytes to produce the NVRAM page or leaf that respectively is supplemented with error correcting code.In addition, data write request part 323 is assigned to target for the physical address of the logical address that write with reference to NVRAM page address conversion table 340 to determine whether to exist via signal wire 348.If there is not this physical address to be assigned with, then data write request part 323 via signal wire 368 with reference to NVRAM physical address admin table 360, so that some of free physical address are assigned to described logical address.Data write request part 323 proceeds the NVRAM page or leaf to be write the physical address of assigned described logical address.

If flash memory 500 is for writing the destination, then data write request part 323 is replenished error correcting code with each section.In addition, data write request part 323 is assigned to target for the physical address of the logical address that writes via signal wire 338 reference section address translation table 330 to determine whether to exist.If there is not this physical address to be assigned with, then data write request part 323 via signal wire 358 with reference to flash memory physical address admin table 350 in order to some of free physical address are assigned to described logical address.Data write request part 323 proceeds data to be write the physical address of assigned described logical address by the unit of eight sections.Because flash memory page or leaf size is greater than described sector sizes, so data write request part 323 typically can be before being write data the data of a flash memory page or leaf are remained in the buffer zone as required.

When writing the data of a section, data write request part 323 will declare that the data of a section have been written into replys to output to and writes destination determining section 322, and outputs to logical address with corresponding to the physical address of this logical address and to show more new portion 324.After all section has been written into, data write request part 323 will declare that the replying of termination of this write order outputs to principal computer 100.

Show more new portion 324 and receive described logic and physical addresss from data write request part 323, and correspondingly upgrade described table.

[typical structure of data read piece]

Figure 12 is the block diagram that shows as the typical structure of the data read piece 370 of the part of this embodiment.Data read piece 370 comprises: order analysis part 371, beginning logical address calculating section 372, NVRAM reading section 373, flash memory reading section 374 and read data send part 375.

Order analysis part 371 is analyzed this read command.Based on the result of this analysis, first logical address that order analysis part 371 is specified with this read command and size of data output to beginning logical address calculating section 372 and NVRAM reading section 373.

Beginning logical address calculating section 372 calculates the logical address (described address is called the beginning logical address) for the treatment of to be written into from the data that flash memory 500 reads first the place.Beginning logical address calculating section 372 is from order analysis part 371 reception first logical address and size of data.Beginning logical address calculating section 372 reads corresponding to NVRAM section number and the continuous section of NVRAM of first logical address from sector address conversion table 330 via signal wire 339 and counts.Based on the continuous section of NVRAM counting and NVRAM section number, beginning logical address calculating section 372 can utilize the expression formula 1 shown in above to calculate to begin logical address.

If be the specified logical address of this read command by the beginning logical address of using above expression formula 1 to obtain, then begin logical address calculating section 372 and will begin logical address and output to flash memory reading section 374.In addition, thereby beginning logical address calculating section 372 obtains to read the section counting by deduct the continuous section counting of NVRAM from described size of data with difference between the NVRAM section number, and will obtain thus this read section and count and output to flash memory reading section 374.

NVRAM reading section 373 reads data from NVRAM400.NVRAM reading section 373 receives first logical address and size of data from order analysis part 371.NVRAM reading section 373 indicates from the NVRAM that sector address conversion table 330 reads corresponding to first logical address via signal wire 339.If it is true that the NVRAM sign is arranged to T(), then NVRAM reading section 373 reads corresponding to NVRAM section number and the continuous section of NVRAM of first logical address from sector address conversion table 330 and counts.By the continuous section counting of NVRAM, NVRAM section number and size of data, NVRAM reading section 373 determines whether that following formula 3 keeps:

(size of data) 〉=(the continuous section counting of NVRAM)-(NVRAM section number) ... (expression formula 3)

If above expression formula 3 keeps, the as many logic block of the right side quantity as expression formula 3 (that is difference) that then will start from first logical address sets the goal to being used for reading of data.IF expression 3 does not keep, and then NVRAM reading section 373 will start from the as many logical address of size of data as described of first logical address as the address of reading of target for data.For example, if the right side quantity of above expression formula 3 be 3 and size of data be 4, then three logical addresses being set the goal be to be used for reading of data.If the right side quantity of above expression formula 3 be 3 and described size of data be 2, then two logical addresses being set the goal be to be used for reading of data.

NVRAM reading section 373 via signal wire 349 with reference to NVRAM page address conversion table 340, to read the physical address that is used for the logical address that reads of data corresponding to target.With reference to NVRAM physical address admin table 360, the physical address of being touched upon to determine whether is bad via signal wire 369 for NVRAM reading section 373.If physical address is not bad, then the read request of the physical address of touching upon has wherein been specified in 373 issues of NVRAM reading section, and this read request is outputed to NVRAM400, receive from the read data of NVRAM400 output, and these data are remained in the buffer zone as required.NVRAM reading section 373 is proofreaied and correct based on the error correcting code execution error that is attached to this read data and is handled, and after this data deletion error correcting code this read data is being outputed to read data transmission part 375.

Flash memory reading section 374 reads data from flash memory 500.Flash memory reading section 374 receives the beginning logical address and reads the section counting from beginning logical address calculating section 372.Flash memory reading section 374 will be left the beginning logical address and read section as described and count the logical address of as many section and take that target is used for the logical address that reads of data as.Flash memory reading section 374 is via signal wire 339 reference section address translation table 330, to read the physical address that is used for the logical address that reads of data corresponding to target.With reference to flash memory physical address admin table 350, the physical address of being touched upon to determine whether is bad via signal wire 359 for flash memory reading section 374.If this physical address is not bad, then the read request of the physical address of touching upon has wherein been specified in 374 issues of flash memory reading section, and this read request is outputed to flash memory 500.This read request is issued simultaneously with the read request of being issued by NVRAM reading section 373.Flash memory reading section 374 receives from the read data of flash memory 500 outputs and with these data and remains on the buffer zone as required.Flash memory reading section 374 proofread and correct to be handled based on the error correcting code execution error that is attached to this read data, and after deleting described error correcting code from these data this read data is outputed to read data and send part 375.

Read data send part 375 will from NVRAM reading section 373 or from the read data of flash memory reading section 374 with replying of described read command outputed to principal computer 100.

Figure 13 illustrates the sequence chart that the performed typical read of this embodiment is handled.Here supposition: in data D1 to D16, data D1 to D3 is written among the NVRAM400, and remaining data D4 to D6 is written in the flash memory 500.Hypothesis principal computer 100 outputs to storage control unit 300 with read command now, has specified data D1 to D16 to be written into the address at place in this read command.

As discussed above, because NVRAM400 comprises data register 450 and cache register 440 as the transferring buffered district of data, so NVRAM400 can carry out the processing of reading data and the processing of shifting read data simultaneously.Thus, NVRAM400 can receive next read request when carrying out given read request.Yet, because the capacity of each buffer zone is only big as a NVRAM page or leaf, can not accept three or more read requests simultaneously.Similarly, suppose: flash memory 500 can be accepted nearly two read requests simultaneously.

Storage control unit 300 issues read request to NVRAM400 before read data D1 data D1 is divided into data D1-1 and D1-2.In addition, in the request to data D1-1 and D1-2, storage control unit 300 issue read requests are to read data D4 to D11 and issue read request to read data D12 to D16.

D1-1 is read out along with read data, and storage control unit 300 issue read requests are to read data D1-2.D1-2 is read out along with data, and storage control unit 300 outputs to principal computer 100 with the data that data D1-1 and D1-2 constitute as data D1.Access time (delay) from time that this read command begins to be performed to this time period composition data memory storage 200 of the time that data D is read out.Because the first data D1 reads from the NVRAM400 with short relatively access time, so the access time of whole data storage device 200 has shortened.

For example, consider a kind of structure, wherein, the busy period of NVRAM400 is 0.1 microsecond (μ s), and the data that shift 1/2 section from NVRAM400 to the 300 required times of storage control unit are 5.3 microseconds (μ s).In the case, the access time of NVRAM400 is defined as: the time period of the time that the data from time that read command is carried out to 1/2 section of dividing are output, i.e. 5.7 microseconds (μ s), the used time period of transfer of its data by being augmented 1/2 section the described busy period obtains.Therefore the access time of whole data storage device 200 amounts to by the used time of transfer with the data of 1 section and adds to 10.7 microseconds (μ s) that the described busy period obtains.

After NVRAM400 reads, remaining data D4 to D16 reads from flash memory 500 at data D1 to D3.After total data is read out, the termination of storage control unit 300 notice principal computers 100 these read commands.

Figure 14 is the sequential chart of the sequential of the performed data transfer of this embodiment of explanation.In Figure 14, horizontal axis is assumed to the time axis.In addition, in Figure 14, the busy period of the length of each dash area supposition expression on the horizontal axis.Particularly, suppose: the busy period of NVRAM400 is 0.1 microsecond (μ s), and the busy period of flash memory 500 is 30 microseconds (μ s).Also supposition: being used for the frequency that data shift between NVRAM400 and flash memory 500 is 50 megahertzes (MHz), and eight data parallel shifts.Supposition in addition: be used for enough lacking in the time of shifting read command between principal computer 100 and the storage control unit 300 and time of being used for transfer read request between NVRAM400 and flash memory 500.

Given above supposition, then calculate to storage control unit 300 required time utilization following formulas 4 from the data of NVRAM400 transferase 12 65 bytes (NVRAM page or leaf):

265 ÷ 50 * 10 ⁶[Hz]=5.3 * 10 ^-6[s]=5.3[μ s] ... (expression formula 4)

Utilize above expression formula 4, the Time Calculation that is used for the data (1 section) of two NVRAM pages or leaves of transfer is 10.6 microseconds (μ s).The handling capacity of NVRAM400 is by given divided by 10.6 microseconds (μ s) with sector sizes (512 byte).

On the other hand, be used for calculating to the time utilization following formula 5 of storage control unit 300 from the data of being furnished with error correcting code of flash memory 500 sections of transfer (540 byte):

540 ÷ 50 * 10 ⁶[Hz]=10.8 * 10 ^-6[s]=10.8[μ s] ... (expression formula 5)

When time of the data that be used for to shift a section obtained and be added to busy period of flash memory 500 by expression formula 5, the access time of 40.8 microseconds of flash memory 500 (μ s) obtained thus.

The quantity of the section that during access time of flash memory 500, can read from NVRAM400, based on the busy period of NVRAM400 and based on the transfer time that obtains from above expression formula 4 and by utilizing following formula 6 to calculate:

(40.8[μ s] – 0.1[μ s])/10.6[μ s] ≈ 3.8...(expression formula 6)

Indicated as above expression formula 6, during access time of flash memory 500, can read the nearly data of three sections from NVRAM400.Thus, this example this, the continuous section of NVRAM counting is arranged to three.

Data up to three sections read from NVRAM400, and the busy period of flash memory 500 just passes by, and making data shift becomes possibility.For this reason, can when reading from NVRAM400, data begin to read data from flash memory 500.Because from the NVRAM400 sense data finish subsequently up to from flash memory 500 read datas begin do not have free time, so this has promoted handling capacity.

Even make the continuous section counting of NVRAM greater than three, handling capacity is not greatly improved yet.This be because the access time in the past after, indifference almost on the time that is used for the every section of transfer between NVRAM400 and the flash memory 500.Thus, if make the continuous section counting of NVRAM greater than three, then wasted the capacity of the NVRAM400 corresponding with excessive counting.As above-mentioned, when the continuous section counting of NVRAM was arranged to its minimum number, the capacity of NVRAM400 can be fully utilized to improve handling capacity.

Though this embodiment is arranged so that storage control unit 300 is issued simultaneously and reads request to NVRAM400 and flash memory 500 that the sequential of request issue is not limited thereto.As long as busy period of flash memory 500 as NVRAM continuous section count as many section read before termination, other sequential also can be used.Particularly, by will adding to the busy period of NVRAM400 as the time that being used for of obtaining from expression formula 4 shifted the data of three sections, thereby provide the time of 31.9 microseconds (μ s), at this moment between in three sections be read.This difference that reads between busy period of time and flash memory 500 is 1.9 microseconds (μ s).Thus, described read request can be distributed to flash memory 500 in the time that is published to NVRAM400 from this read request during this time period of the time in 1.9 microseconds (μ s) past.

[typical operation of data write-in block]

Figure 15 illustrates the performed process flow diagram of typically writing processing of this embodiment.This writes processing can be when receiving write order and writing data from principal computer 100 such as storage control unit 300.

Data write-in block 320 in the storage control unit 300 is handled writing of write data based on specified first logical address of this write order and size of data and is divided into section (step S921).Data write-in block 320 is determined: will be used for the logical address (step S922) that writes as target with respect to any of the logical address of the as many still data to be written of size of data counting of first logical address (logical address that for example has the lowest address value).

By reference section address translation table 330, data write-in block 320 reads corresponding to the section management information (step S923) of target for the logical address that writes.

It is true that data write-in block 320 determines whether to be arranged to T(from the high speed specified sign that principal computer 100 receives) (step S924).If the high speed specified sign is arranged to "Yes" among the T(step S924), then data write-in block 320 determines that targets are used for the logical address that writes whether within respect to the as many section of the continuous section counting as NVRAM of first logical address (for example 3) (step S925).

If the logical address that target is used for writing is being counted (step S925 "Yes") within the as many section with respect to the continuous section as NVRAM of first logical address, the physical address that reads corresponding to this logical address from NVRAM page address conversion table 340 of data write-in block 320 then.If in conversion table 340, do not find physical address corresponding, then data write-in block 320 with reference to NVRAM physical address admin table 360 free physical address is assigned to this logical address.Data write-in block 320 is write the physical address corresponding to this logical address (step S926) among the NVRAM400 with data.Data write-in block 320 based on write and update area sector address conversion table 330(step S927).Particularly, data write-in block 320 will to be updated to T(corresponding to the NVRAM of this logical address sign and enabler flags true).In addition, data write-in block 320 is write field (field) corresponding to the continuous section of the NVRAM of this logical address counting with " 3 ", and will be worth 0 to 2 field of writing NVRAM section number.

Data write-in block 320 based on write and upgrade NVRAM page address conversion table 340(step S928).If the logical address that data are written into is unregistered in NVRAM page address conversion table 340, then data write-in block 320 registers to conversion table 340 with logical address and the NVRAM page management information of touching upon.

If the high speed specified sign is arranged to the F(vacation) ("No" among the step S924), if or the logical address that target is used for writing do not counting (step S925 "No") within the as many section with respect to the continuous section as NVRAM of first logical address, then data write-in block 320 is considered as writing the destination with flash memory 500.Data write-in block 320 obtains corresponding to the physical address of target for the logical address that writes from physical address section management information.If this physical address corresponding does not find in section management information, then data write-in block 320 with reference to flash memory physical address admin table 350 free physical address is assigned to this logical address.Data write-in block 320 is write the physical address corresponding to this logical address (step S929) in the flash memory 500 with data.Data write-in block 320 is based on the update area sector address conversion table 330(step S930 that writes).Particularly, it is true that data write-in block 320 will be updated to T(corresponding to the enabler flags of this logical address), and NVRAM sign is updated to the F(vacation).In addition, data write-in block 320 is write physical address and the physical address skew corresponding to this logical address.

After described table upgrades (step S928 or S930), data write-in block 320 determines whether to exist any data (section) (step S931) of write data still to be written.If there are any data ("Yes" among the step S931) still to be written, then data write-in block 320 turns back to step S922.If there is no still data ("No" among the step S931) to be written, the then termination (step S932) of data write-in block 320 notice principal computers 100 these write orders.In step S932 end, data write-in block 320 stops this and writes processing.

[typical operation of data read piece]

Figure 16 illustrates the process flow diagram that the performed typical read of this embodiment is handled.This reads to handle can be such as when storage control unit 300 during from principal computer 100 reception read commands.

Data read piece 370 in the storage control unit 300 is read this read data to handle based on the specified beginning logical address of this read command and size of data and is divided into section (step S951).Data read piece 370 is determined: will be used for the logical address (step S952) that reads as target with respect to any of the as many logical address that still continues of size of data counting of first logical address (logical address that for example has the lowest address value).

By reference section address translation table 330, data read piece 370 reads corresponding to the section management information (step S953) of target for the logical address that reads.It is true that data read piece 370 determines whether that the NVRAM sign in this section management information is arranged to T() (step S954).

If this NVRAM sign is arranged to "Yes" among the T(step S954), then data read piece 370 utilizes the beginning logical address (step S955) that expression formula 1 discussed above is calculated in the flash memory 500.And data read piece 370 need to determine whether issue to read request to flash memory 500.Particularly, if should the beginning logical address be the specified logical address of this read command, determine that then this read request needs issue.Otherwise, do not need to determine issue to read request to flash memory 500(step S956).

If NVRAM is arranged to the F(vacation) ("No" among the step S954), if determine that perhaps this read request needs issue ("Yes" among the step S956), then data read piece 370 is issued this and is read request to flash memory 500.Be published in case it should be noted that read request, then this read request need not to be published again.In this read request, specified the logical address (step S957) that is connected in the beginning logical address.

Read request to flash memory ("No" among the step S956) if need not to issue this, or in step S957 end, then data read piece 370 is carried out NVRAM and is read to handle (step S960).And data read piece 370 is carried out flash memory and is read to handle (step S970).

Data read piece 370 determines whether to exist still any data (section) (step S958) to be read.If there are any data ("Yes" among the step S958) still to be read, then data read piece 370 turns back to step S952.If there are not data still ("No" among the step S958) to be read, the then termination (step S959) of data read piece 370 notice principal computers 100 these read commands.In the end of step S959, data read piece 370 stops this and reads to handle.

Figure 17 illustrates the process flow diagram that the performed typical NVRAM of this embodiment reads to handle.Data read piece 370 determines whether that the logical address that target is used to read is the address (step S961) that is connected in the beginning logical address.

If the logical address that target is used for reading is not the address (step S961 "No") that is connected in the beginning logical address, then data read piece 370 reads corresponding to the section management information of target for the logical address that reads from sector address conversion table 330.Whether keep according to above expression formula 3, data read piece 370 will as the as many logical address of right side quantity of expression formula 3 or as described the as many logical address of size of data take that target is used for the logical address (step S962) that reads from NVRAM400 as.And data read piece 370 reads to handle the unit (step S963) that is divided into 256 bytes (1/2 section) at NVRAM400 with this.

Data read piece 370 reads corresponding to the physical address of target for the logical address that reads from NVRAM page address conversion table 340, and these addresses are defined as target for the physical address that reads.Be assigned at two physical addresss under the situation of each logical address of representing a section, described physical address begins to read continuously (step S964) from the physical address that the logical address corresponding to smaller value is offset.Data read piece 370 reads NVRAM page or leaf (1/2 section) (step S965) from the physical address of determining thus.

Data read piece 370 determines whether data to be transferred to principal computer 100.For example, in the end of error correction process, described data shift and are confirmed as possibility (step S966).

If described data shift possibility ("Yes" among the step S966), then data read piece 370 is transferred to principal computer 100(step S967 with described read data by the unit of section).

Can not ("No" among the step S966) if described data shift, or in the end of step S967, then data read piece 370 determines whether to exist and treats any NVRAM page or leaf (step S968) of reading from NVRAM400.Treat the data ("Yes" the step S968) that read from NVRAM400 if exist, then data read piece 370 turns back to step S964.If the logical address that target is used for reading is the address (step S961 "Yes") that is routed to the beginning logical address, if or do not treat the data ("No" the step S968) that read from NVRAM400, then data read piece 370 stops these NVRAM and reads to handle.

Figure 18 illustrates the process flow diagram that the performed typical flash memory of this embodiment is read to handle.Data read piece 370 determines whether read request is published to flash memory 500(step S971).

If this read request is distributed to "Yes" among the flash memory 500(step S971), then determine whether can be from flash memory 500 read data (step S972) when its busy period disappears for data read piece 370.If can not be from flash memory 500 read datas ("No" the step S972), then data read piece 370 turns back to step S972.

If can be from flash memory 500 read datas ("Yes" the step S972), then data read piece 370 reads data (step S973) from flash memory 500.Data read piece 370 determines whether to shift described data to principal computer 100.For example, in the end of error correction process, determine that it is possible (step S974) that described data shift.

If determine that it is possible ("Yes" among the step S974) that described data shift, then data read piece 370 is transferred to principal computer 100(step S975 with described read data by the unit of section).Can not ("No" among the step S974) if described data shift, or in the end of step S975, then data read piece 370 stops these flash memories and reads to handle.

Figure 19 is illustrated in the tabular drawing that data are write the typical sector address conversion table 330 that comes into force before the flash memory 500 as the part of this embodiment.Logical address for example " j+3 ", " j+5 " and " j+7 " has respectively been distributed physical address, and it is true to be arranged to T(corresponding to the enabler flags of these each logical addresses).Other logical address is " j ", " j+1 " and " j+2 " unallocated physical address for example, and is arranged to the F(vacation corresponding to the enabler flags of these each logical addresses).

Figure 20 is illustrated in the tabular drawing that data are write the typical sector address conversion table 330 that comes into force after the flash memory 500 as the part of this embodiment.Dash area among Figure 20 is the field of the renewal in sector address conversion table 330 shown in Figure 19.Consider an example, wherein, first logical address is " j ", and flash memory page or leaf (8 sections) has been write flash memory 500.In this case, for each field corresponding to the flash memory physical address of logical address " j " to " j+7 ", corresponding to the physical address " fA of logical address " j " _j" be written into.In addition, for the field that the physical address corresponding to logical address " j " to " j+7 " is offset, indicate described physical address with respect to physical address " fA _j" the value " 0 " to " 7 " of relative position be written into.In addition, it is true to be configured to T(corresponding to the enabler flags of each logical address " j " to " j+7 ").In this way, each logical address is offset the reference physical address that has distributed in the flash memory page or leaf with physical address corresponding.

Figure 21 is illustrated in the tabular drawing that data are write the typical sector address conversion table 330 that comes into force before the NVRAM400 as the part of this embodiment.Logical address is " i ", " i+1 " and " i+2 " unallocated any physical address for example, and is configured to the F(vacation corresponding to NVRAM sign and the enabler flags of these each logical addresses).

Figure 22 is illustrated in data to write the tabular drawing of the typical sector address conversion table 330 that comes into force after the NVRAM400 as the part of this embodiment is tabular drawings.Dash area among Figure 22 is the field of upgrading in the sector address conversion table 330 shown in Figure 21.Consider an example, wherein, first logical address is " i ", and the data of three sections have been written to NVRAM400.In this case, it is true to be arranged to T(corresponding to the NVRAM sign of each logical address " i " to " i+2 ").In addition, for the field corresponding to the NVRAM section number of logical address " i " to " i+2 ", represent that described logical address is written into respect to the value 0 to 2 of the relative position of first logical address.For each field of counting to the continuous section of the NVRAM of " i+2 " corresponding to logical address " i ", value " 3 " is written into.In this way, when data were written to NVRAM400, related logical address was associated with corresponding logical address counting (being the continuous section counting of NVRAM) and is associated with the relative position (NVRAM section number) of these logical addresses.

Above-described embodiment according to disclosure technology, when writing a plurality of data, storage control unit 300 will be write NVRAM400 as quantity data can reading from NVRAM400 in the time period corresponding to access time of flash memory 500, and remaining data is write flash memory 500.When reading a plurality of data, storage control unit 300 is issued in the following manner and is read request to NVRAM400 and flash memory 500, makes that namely reading data from flash memory 500 is reading from NVRAM400 when finishing.This sets and makes storage control unit 300 read data from NVRAM400 to finish and begin subsequently from flash memory 500 read datas.This means finishing to read the time of data from NVRAM400 and begin to read from flash memory 500 between time of data do not have free time, promote handling capacity thus.In addition, be written to NVRAM400 because be used for the data of the minimum number of raising handling capacity, so the capacity of NVRAM400 can be utilized efficiently.

In addition, because storage control unit 300 can be so that the mode that data can be read at a high speed and write data can improve so read the convenience of the equipment of this data.For example, this feature can strengthen smart mobile phone, dull and stereotyped PC(personal computer) and other need aspect the convenience of equipment of high-speed starting effective especially usually.Particularly, the mode that pending software code can be read at a high speed with this code when the startup of this kind equipment and writing.This provides the high-speed starting of described equipment.

＜2. variation 〉

The variation of above-described embodiment is described below with reference to Figure 23.Figure 23 schematically illustrates for the write order of the variation of this embodiment canonical parameter to be arranged.As one of described parameter, the continuous section counting of NVRAM is arranged to replace high speed specified sign HF.When writing the data that are made of a plurality of sections, principal computer 100 is determined the continuous section counting of NVRAM and is sent instructions to its data storage device 2000.Principal computer 100 can change the continuous section counting of NVRAM based on the type of using with based on the time that is used for the data transfer between principal computer 100 and the data storage device 200.In the instruction of principal computer 100, data storage device 200 arranges the continuous section counting of NVRAM.

According to the variation of above general introduction, principal computer 100 can change the continuous section counting of NVRAM as required.

Above-described embodiment and variation thereof only are the examples that can be implemented of the disclosure therein.The disclosed theme that embodiment in the description of the preferred embodiment of this instructions and the spy of variation thereof claim (particulars) to correspond essentially to state in the claims.Similarly, the disclosed theme of naming in the claims corresponds essentially to the spy who has same names in the description of preferred embodiment and claims.Yet, the disclosure is not limited to this class embodiment of the present disclosure, variation and other example, and it will be understood by those skilled in the art that in the scope of claim and equivalent thereof, according to designing requirement and other factors, can carry out various modification, combination, sub-portfolio and change.

As step and the processing of the described series discussed above of the part of described embodiment, also can take as for the method for implementing this class step and processing, take as be used to making computing machine carry out the program of these class methods or taking the recording medium of storing this class method as.Described recording medium can be for example CD (Compact Discs, CD), any in miniature video disc (MiniDisc, MD), DVD(Digital Versatile Disks), storer card or the Blu-ray disc (registered trademark).

Disclosure technology is also configurable as follows:

(1) a kind of memory control device comprises:

Write-in block, be arranged so that: given low speed access storage block with access time longer than the access time of zero access storage block, the described access time is time to the time of reading described data from the request of issue read data, the said write piece be built up in corresponding in the time period of the access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts, if a plurality of data wait to write described high speed and described low speed access storage block, then the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data, with read piece, be arranged so that: if treat described a plurality of data of writing described low speed and described zero access storage block from wherein reading, then described read piece issue request to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to begin to read described low speed access data after reading described zero access data.

(2) as the described memory control device of above paragraph (1), also comprise the management information storage block that is configured to management information, described management information is used for obtaining from the zero access address that writes described zero access data and writes the low speed access start address for the treatment of the described low speed access data that at first read; Wherein, read described zero access data if treat from described zero access address, then described read piece issue request to described zero access storage block to read described zero access data, the described piece that reads further obtains described low speed access start address based on described management information, described read piece further issue the request to described low speed access storage block to read described low speed access data from described low speed access start address.

(3) as the described memory control device of above paragraph (2), wherein, described management information storage block is stored as described management information with the relative position relation between each zero access address and the described low speed access start address, wherein, when reading described zero access data from any of described zero access address, the described piece that reads is from the zero access address of touching upon with from obtaining described low speed access start address corresponding to the described management information of described zero access address.

(4) as any described memory control device of above paragraph (1) to (3), wherein, described read the piece request of issuing simultaneously to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to read described low speed access data.

(5) as any described memory control device of above paragraph (1) to (4), wherein, if utilize instruction to specify described zero access data counts to write described a plurality of data, then the said write piece writes described a plurality of data when setting up specified zero access data counts.

(6) as the described memory control device of above paragraph (5), wherein, indicate to write the data that write to read at a high speed afterwards if utilize described instruction, then the said write piece will be as described the as many data of zero access data counts write described zero access storage block as described zero access data, simultaneously remaining data is write described low speed access storage block as described low speed access data.

(7) a kind of have write-in block and the control method that reads the memory control device of piece for control, described control method comprises: given low speed access storage block with access time longer than the access time of zero access storage block, the described access time is time to the time of reading described data from the request of issue read data, make the said write piece be built up in corresponding in the time period of access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts; If a plurality of data wait to write described high speed and described low speed access storage block, then make the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data, if and treat described a plurality of data of writing described low speed and described zero access storage block from wherein reading, then make described read piece issue request to described zero access storage block reading described zero access data, and issue is asked to described low speed access storage block to begin to read described low speed access data after described zero access data have been read out.

(8) a kind of memory storage comprises:

The zero access storage block;

The low speed access storage block is configured to have the access time longer than the access time of described zero access storage block, and the described access time is time to the time of reading described data from the request of issue read data; And memory control device, comprise: write-in block, be configured to be built up in corresponding in the time period of access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts, if a plurality of data wait to write described high speed and described low speed access storage block, then the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data, with read piece, be arranged so that: if treat described a plurality of data of writing described low speed and described zero access storage block from wherein reading, then described read piece issue request to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to begin to read described low speed access data after reading described zero access data.

The disclosure comprises the related topics of disclosed content among the Japanese priority patent application JP2012-001781 that submitted to Jap.P. office on January 10th, 2012, and its full content is incorporated herein by reference.

It will be understood by those skilled in the art that in the scope of claim or its equivalent of enclosing, according to designing requirement and other factors, can carry out various modification, combination, sub-portfolio and change.

Claims

1. memory control device comprises:

Write-in block, be arranged so that: given low speed access storage block with access time longer than the access time of zero access storage block, the described access time is time to the time of reading described data from the request of issue read data, the said write piece be built up in corresponding in the time period of the access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts, if a plurality of data wait to write described high speed and described low speed access storage block, then the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data and

Read piece, be arranged so that: if treat described a plurality of data of writing described low speed and described zero access storage block from wherein reading, then described read piece issue request to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to begin to read described low speed access data after reading described zero access data.

2. memory control device as claimed in claim 1, also comprise the management information storage block that is configured to management information, described management information is used for obtaining from the zero access address that writes described zero access data and writes the low speed access start address for the treatment of the described low speed access data that at first read;

Wherein, read described zero access data if treat from described zero access address, then described read piece issue request to described zero access storage block to read described zero access data, the described piece that reads further obtains described low speed access start address based on described management information, described read piece further issue the request to described low speed access storage block to read described low speed access data from described low speed access start address.

3. memory control device as claimed in claim 2, wherein, described management information storage block with the relative position relation between each zero access address and the described low speed access start address be stored as described management information and

Wherein, when reading described zero access data from any of described zero access address, the described piece that reads is from the zero access address of touching upon with from obtaining described low speed access start address corresponding to the described management information of described zero access address.

4. memory control device as claimed in claim 1, wherein, described read the piece request of issuing simultaneously to described zero access storage block to read described zero access data and issue is asked to described low speed access storage block to read described low speed access data.

5. memory control device as claimed in claim 1 wherein, specifies described zero access data counts to write described a plurality of data if utilize to instruct, and then the said write piece writes described a plurality of data when setting up specified zero access data counts.

6. memory control device as claimed in claim 5, wherein, indicate to write the data that write to read at a high speed afterwards if utilize described instruction, then the said write piece will be as described the as many data of zero access data counts write described zero access storage block as described zero access data, simultaneously remaining data is write described low speed access storage block as described low speed access data.

7. one kind is used for the control method that control has write-in block and reads the memory control device of piece, and described control method comprises:

Given low speed access storage block with access time longer than the access time of zero access storage block, the described access time is time to the time of reading described data from the request of issue read data, make the said write piece be built up in corresponding in the time period of access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts;

If a plurality of data wait to write described high speed and described low speed access storage block, then make the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data, and

If treat described a plurality of data of writing described low speed and described zero access storage block from wherein reading, then make described read piece issue request to described zero access storage block reading described zero access data, and issue is asked to described low speed access storage block to begin to read described low speed access data after described zero access data have been read out.

8. a memory storage comprises:

The zero access storage block;

The low speed access storage block is configured to have the access time longer than the access time of described zero access storage block, and the described access time is time to the time of reading described data from the request of issue read data; With

Memory control device comprises:

Write-in block, be configured to be built up in corresponding in the time period of access time of described low speed access storage block by the quantity of the readable data of described zero access storage block, as the zero access data counts, if a plurality of data wait to write described high speed and described low speed access storage block, then the said write piece further with in described a plurality of data as described the as many data of zero access data counts write described zero access storage block as the zero access data, simultaneously remaining data is write described low speed access storage block as the low speed access data and