CN104035852A - Automatic frame repetition based 1553B bus hardware timed communication test device and method - Google Patents
Automatic frame repetition based 1553B bus hardware timed communication test device and method Download PDFInfo
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Abstract
The invention relates to an automatic frame repetition based 1553B bus hardware timed communication test device and method, relates to the field of communication, tests and measurements, and aims at solving the problems of data response delay, data interrupt and data deficiency that are easily caused in the conventional hardware timing based 1553B communication when a new command datum is inserted into multiple command data. By adopting an arbitration module and cache modules of different priorities and utilizing an automatic frame repetition module, the device achieves the hardware timing function with variable message intervals in a 1553B communication test, achieves an interval variable 1553B frame form communication method, and guarantees the adjustable interval between messages in each frame. Under the condition that no data updating is available, the method automatically repeats the data content of the last frame at a receiving or transmitting state, detects the existence of the inserted data in real time, prioritizes the transmission of the inserted data and then the transmission of routine data if the inserted data exist, and guarantees the instantaneity and the reliability of the communication. The automatic frame repetition based 1553B bus hardware timed communication test device and the automatic frame repetition based 1553B bus hardware timed communication test method are suitable for the occasions of communication tests.
Description
Technical field
The present invention relates to communication and thermometrically field.
Background technology
1553B bus is the serial communication bus of MILSTD, and its full name is " interior of aircraft time-devision system, command/response, multiplex bus ".This bus is as the medium of information between subset and exchanges data, not only in Physical layer, the electrical specification of signal has been done to strict regulation, for the form of 1553B instruction response and the detection method of Frame mistake, in data link layer and network layer, also done strict definition simultaneously.
Adopting 1553B bus to realize regularly communication, is current conventional technological means, is conventionally referred to as 1553B and regularly communicates by letter.In non real-time system, for guaranteeing the requirement of real-time Communication for Power, based on hardware communication means regularly, be introduced into application.When regularly having multiple order data and inserting newer command data in communication process, due to the switching of order data, can cause the time delay of 1553B communication response, send data and interrupt and send the problems such as data are imperfect.
Summary of the invention
The present invention is in order to solve while inserting newer command data under multiple order data, and existing based on hardware, 1553B communication regularly easily occurs that data response time delay, data interrupt and the incomplete problem of data.The 1553B bus hardware timing communication test device and method repeating based on automatic frame has now been proposed.
The 1553B bus hardware repeating based on automatic frame is communication test device regularly, and it comprises host computer and interface bus; It also comprises testing apparatus, and testing apparatus comprises automatic frame replicated blocks and FPGA module;
FPGA module comprises decoding logic module, writes buffer memory decoding module, reads buffer memory decoding module, arbitration modules, steering logic module, insert order and send cache module, insert order and receive cache module, conventional cache module and the conventional cache module that receives of sending;
Automatically frame replicated blocks are for realizing mutual with the data bus signal of the decoding logic module of FPGA module, also for realizing mutual with the address bus signal of the decoding logic module of FPGA module, also for realizing mutual with the steering logic signal of the steering logic module of FPGA module;
Decoding logic module is used for carrying out decoding from the data of arbitration modules and automatic frame replicated blocks, and the data interaction between realization and arbitration modules;
Arbitration modules is for realizing and inserting order transmission cache module and the conventional data interaction that sends cache module, also for being deposited in, insertion order inserts order reception cache module, also for standing order being deposited in to the conventional cache module that receives, also for realizing the data interaction with steering logic module; Also for realizing, the data of all input arbitration modules are arbitrated, concrete arbitrated procedure is: whether judgement finishes from the frame of the stack pointer of automatic frame replicated blocks, thereby determines whether to continue to read this frame data; Also for judging the type of the frame of stack pointer, and according to the type of frame, the content of this frame is write and inserts order reception cache module or the conventional cache module that receives; Steering logic module is for realizing mutual with the control signal of interface bus, also for automatic frame replicated blocks are resetted; Insert order send cache module for and write the mutual of data inserting between buffer memory decoding module, also for storing and send from the data inserting of writing buffer memory decoding module; Conventional send cache module for and write the mutual of routine data between buffer memory decoding module, also for storing and send from the data of writing buffer memory decoding module;
Insert order receive cache module for and read the mutual of data inserting between buffer memory decoding module, also for storing and send the data inserting from arbitration modules; Conventional receive cache module for and read the mutual of routine data between buffer memory decoding module, also for storing and send the routine data from arbitration modules;
Write buffer memory decoding module for realize and interface bus between data interaction, also for receiving from the data of interface bus and by these data, deposit in and insert order and send cache module or the conventional cache module that sends;
Read buffer memory decoding module for realize and interface bus between data interaction, also for reading, insert order and receive cache module and the conventional data that receive buffer memory.
The 1553B bus hardware repeating based on automatic frame is communication test device regularly, and it also comprises 1553B Bussing connector, an isolating transformer and No. two isolating transformers;
1553B Bussing connector for realize and measurand between communication data signal mutual, also for and an isolating transformer and No. two isolating transformers between voltage signal mutual;
Isolating transformer and No. two isolating transformers all for realize and automatic frame replicated blocks between voltage signal mutual; An isolating transformer and No. two isolating transformers are also for the protection to the voltage signal of 1553B Bussing connector and automatic frame replicated blocks.
The 1553B bus hardware repeating based on automatic frame is communication test method regularly, and this method of testing comprises the steps:
Step 1, host computer send order by interface bus to the buffer memory decoding module of writing in FPGA module, automatically frame replicated blocks trigger interrupt procedure simultaneously, now the arbitration modules in FPGA module reads the stack pointer of automatic frame replicated blocks by decoding logic module, obtains message number;
Step 2, arbitration modules read the command word content in stack pointer, and judge the state of this command word place frame;
If the state of command word place frame is transmission state, arbitration modules judges whether these frame data finish, execution step three; If the state of command word place frame is accepting state, arbitration modules judges the type of this frame and performs step four;
If the data of the frame at the command frame place described in step 3 step 2 do not finish, repeating step two continues to read these frame data; Whether, if the data of the frame at the command frame place described in step 2 finish, arbitration modules stops reading the content of this frame, and be empty according to priority judgement insertion order transmission cache module and conventional transmission cache module, performs step 31;
If step 3 one is inserted order transmission, cache module is empty, and whether continue the conventional transmission of judgement cache module is empty, and perform step three or two;
If the conventional cache module that sends of step 3 two is empty, arbitration modules resets automatic frame replicated blocks by steering logic module; If it is not empty conventional, sending cache module, and arbitration modules reads the content of conventional transmission cache module and writes automatic frame replicated blocks by decoding logic module;
If insert, ordering and sending cache module is not sky, and arbitration modules reads the content of insertion order transmission cache module and will order the content that read transmission cache module to write automatic frame replicated blocks from inserting;
Step 3 three, automatically frame replicated blocks send to measurand by the content depositing in by isolating transformer, No. two isolating transformers and 1553B Bussing connector; Then measurand is back to automatic frame replicated blocks by the content depositing in through 1553B Bussing connector, two isolating transformers, waits for and triggers interrupt procedure next time, and return to step 1;
If it is to insert frame that the judgement of step 4 arbitration modules draws this frame, arbitration modules reads the content of this insertion frame and this insertion content frame is write and inserted in order reception cache module, then performs step five;
If arbitration modules judgement show that this frame is conventional frame, arbitration modules reads the content of conventional frame and the content of this routine frame is write to conventional reception in cache module, execution step five;
If the data of the frame at the insertion frame described in step 5 step 4 or conventional frame place do not finish, arbitration modules continues to read the data of inserting frame or conventional frame; If the data of the frame at the insertion frame described in step 4 or conventional frame place finish, arbitration modules stops reading the content of this frame, read buffer memory decoding module and read the data of inserting in order reception cache module or conventional reception cache module, these data are back to host computer through interface bus, whether arbitration modules is empty according to priority judgement insertion order transmission cache module and conventional transmission cache module simultaneously, performs step 31.Automatically frame replicated blocks adopt the 1553B interface chip of ACE/MiniACE series to realize.
The present invention is applicable to communication test occasion.
The present invention is by adopting the cache module of arbitration modules and different priorities, and utilize automatic frame replicated blocks to realize the variable hardware timing function of message interval in 1553B communication test, solved logical resource waste anxiety, data response time delay, the data that while existing multiple order data to send, order data switching brings and interrupted and the incomplete problem of data in 1553B communication.
The present invention, not increasing under the condition of hardware circuit, has enriched the function of the communication test set based on 1553B to a great extent, enables to adapt to the test occasion of various communication protocol complexity.
Accompanying drawing explanation
Fig. 1 is the regularly structural drawing of communication test device of the 1553B bus hardware repeating based on automatic frame of the present invention;
Fig. 2 is the workflow schematic diagram of interrupt procedure of the present invention.
Embodiment
Embodiment one, with reference to Fig. 1, illustrate present embodiment, the 1553B bus hardware repeating based on automatic frame described in present embodiment is communication test device regularly, and it comprises host computer and interface bus; It also comprises testing apparatus 1, and testing apparatus 1 comprises automatic frame replicated blocks 6 and FPGA module 7;
FPGA module 7 comprises decoding logic module 71, writes buffer memory decoding module 72, reads buffer memory decoding module 73, arbitration modules 74, steering logic module 75, insert order and send cache module 76, insert order and receive cache module 77, conventional cache module 78 and the conventional cache module 79 that receives of sending;
Automatically frame replicated blocks 6 are for realizing mutual with the data bus signal of the decoding logic module 71 of FPGA module 7, also for realizing mutual with the address bus signal of the decoding logic module 71 of FPGA module 7, also for realizing mutual with the steering logic signal of the steering logic module 75 of FPGA module 7;
Decoding logic module 71 for to from arbitration modules 74 and automatically the data of frame replicated blocks 6 carry out decoding, and the data interaction between realization and arbitration modules 74;
Arbitration modules 74 is for realizing and inserting order transmission cache module 76 and the conventional data interaction that sends cache module 78, also for being deposited in, insertion order inserts order reception cache module 77, also for standing order being deposited in to the conventional cache module 79 that receives, also for realizing the data interaction with steering logic module 75;
Also for realizing, the data of all input arbitration modules 74 are arbitrated, concrete arbitrated procedure is: whether judgement finishes from the frame of the stack pointer of automatic frame replicated blocks 6, thereby determines whether to continue to read this frame data; Also for judging the type of the frame of stack pointer, and according to the type of frame, the content of this frame is write and inserts order reception cache module 77 or the conventional cache module 79 that receives;
Steering logic module 75 is for realizing mutual with the control signal of interface bus, also for automatic frame replicated blocks 6 are resetted;
Insert order send cache module 76 for and write the mutual of data inserting between buffer memory decoding module 72, also for storing and send from the data inserting of writing buffer memory decoding module 72;
Conventional send cache module 78 for and write the mutual of routine data between buffer memory decoding module 72, also for storing and send from the data of writing buffer memory decoding module 72;
Insert order receive cache module 77 for and read the mutual of data inserting between buffer memory decoding module 73, also for storing and send the data inserting from arbitration modules 74;
Conventional receive cache module 79 for and read the mutual of routine data between buffer memory decoding module 73, also for storing and send the routine data from arbitration modules 74;
Write buffer memory decoding module 72 for realize and interface bus between data interaction, also for receiving from the data of interface bus and by these data, deposit in and insert order and send cache module 76 or the conventional cache module 78 that sends;
Read buffer memory decoding module 73 for realize and interface bus between data interaction, also for reading, insert order and receive cache module 77 and the conventional data that receive buffer memory 79.
Embodiment two, present embodiment are further illustrating the 1553B bus hardware repeating based on the automatic frame timing communication test device described in embodiment one, in present embodiment, it also comprises 1553B Bussing connector 3, isolating transformer 4 and No. two isolating transformers 5;
1553B Bussing connector 3 for realize and measurand 2 between communication data signal mutual, also for and an isolating transformer 4 and No. two isolating transformers 5 between voltage signal mutual;
Isolating transformer 4 and No. two isolating transformers 5 all for realize and automatic frame replicated blocks 6 between voltage signal mutual; An isolating transformer 4 and No. two isolating transformers 5 are also for the protection to the voltage signal of 1553B Bussing connector 3 and automatic frame replicated blocks 6.
Embodiment three, with reference to Fig. 1 and Fig. 2, illustrate present embodiment, according to the timing communication test method of communication test device regularly of the 1553B bus hardware repeating based on automatic frame described in embodiment two, this method of testing comprises the steps:
Step 1, host computer send order by interface bus to the buffer memory decoding module 72 of writing in FPGA module 7, automatically frame replicated blocks 6 trigger interrupt procedure simultaneously, now the arbitration modules 74 in FPGA module 7 reads the stack pointer of automatic frame replicated blocks 6 by decoding logic module 71, obtains message number;
Step 2, arbitration modules 74 read the command word content in stack pointer, and judge the state of this command word place frame;
If the state of command word place frame is transmission state, arbitration modules 74 judges whether these frame data finish, execution step three; If the state of command word place frame is accepting state, arbitration modules 74 judges the type of these frames and performs step four;
If the data of the frame at the command frame place described in step 3 step 2 do not finish, repeating step two continues to read these frame data; Whether, if the data of the frame at the command frame place described in step 2 finish, arbitration modules 74 stops reading the content of this frame, and be empty according to priority judgement insertion order transmission cache module 76 and conventional transmission cache module 78, performs step 31;
If step 3 one is inserted order transmission, cache module 76 is empty, and whether continue the conventional transmission of judgement cache module 78 is empty, and perform step three or two;
If the conventional cache module 78 that sends of step 3 two is empty, arbitration modules resets automatic frame replicated blocks 6 by steering logic module 75; If it is not empty conventional, sending cache module 78, and arbitration modules 74 reads the content of conventional transmission cache module 78 and writes automatic frame replicated blocks 6 by decoding logic module;
If insert, ordering and sending cache module 76 is not sky, and arbitration modules 74 reads the content of insertion order transmission cache module 76 and will order the content that read transmission cache module 76 to write automatic frame replicated blocks 6 from inserting;
Step 3 three, automatically frame replicated blocks 6 send to measurand 2 by the content depositing in by isolating transformer 4, No. two isolating transformers 5 and 1553B Bussing connector 3; Then measurand is back to automatic frame replicated blocks by the content depositing in through 1553B Bussing connector, two isolating transformers, waits for and triggers interrupt procedure next time, and return to step 1;
If it is to insert frame that 74 judgements of step 4 arbitration modules draw this frame, arbitration modules 74 reads the content of this insertion frame and this insertion content frame is write and inserted in order reception cache module 77, then performs step five;
If arbitration modules 74 judgements show that this frame is conventional frame, arbitration modules 74 reads the content of conventional frame and the content of this routine frame is write to conventional reception in cache module 79, execution step five;
If the data of the frame at the insertion frame described in step 5 step 4 or conventional frame place do not finish, arbitration modules continues to read the data of inserting frame or conventional frame; If the data of the frame at the insertion frame described in step 4 or conventional frame place finish, arbitration modules 74 stops reading the content of this frame, read buffer memory decoding module 73 and read the data of inserting in order reception cache module 77 or conventional reception cache module 79, these data are back to host computer through interface bus, whether arbitration modules 74 is empty according to priority judgement insertion order transmission cache module 76 and conventional transmission cache module 78 simultaneously, performs step 31.In present embodiment, transmission state refers to BC-RT state, refers to data that host computer sends to FPGA module in transmission state, and accepting state refers to RT-BC state, refers to data that host computer sends to FPGA module in accepting state.Whether the data that judge the frame at certain frame place finish according to being to judge whether the value of this frame is 0Xffff, are that 0Xffff represents to finish.
FPGA module is the key component of whole communication module, host computer sends data by interface bus to FPGA module, these data exist in the mode of conventional frame, these data are sent to measurand through FPGA module, automatic frame replicated blocks, an isolating transformer, No. two isolating transformers, 1553B Bussing connectors, when host computer sends the order data inserting, the order data of this insertion exists to insert the form of frame.
Embodiment four, present embodiment are further illustrating the 1553B bus hardware repeating based on the automatic frame timing communication test device described in embodiment one, in present embodiment, frame replicated blocks 6 adopt the 1553B interface chip of ACE/MiniACE series to realize automatically.
The 1553B interface chip of ACE/MiniACE series is in realizing MIL-STD-1553B national military standard prescribed terminal function, also there is stronger message management ability, repeating transmission and the automatic frame that can realize message repeat to send, and message interval is able to programme, wherein, the message interval time of BU61580 chip is 1 μ s～65.535ms, meets the needs of system real-time communication.
The mode that the present invention adopts FPGA control, the 1553B communication technology, automatic frame repeat techniques to combine, has realized the 1553B bus hardware timing communication means with automatic frame repeat function.Solve the imperfect problem of time delay, data causing while inserting newer command data under multiple order data, and enriched the function of the communication test set based on 1553B, enabled to adapt to the test occasion of various communication protocol complexity.
Claims (4)
1. the 1553B bus hardware repeating based on automatic frame is communication test device regularly, and it comprises host computer and interface bus;
It is characterized in that, it also comprises testing apparatus (1), and testing apparatus (1) comprises automatic frame replicated blocks (6) and FPGA module (7);
FPGA module (7) comprises decoding logic module (71), writes buffer memory decoding module (72), reads buffer memory decoding module (73), arbitration modules (74), steering logic module (75), insert order and send cache module (76), insert order and receive cache module (77), conventional cache module (78) and the conventional reception cache module (79) of sending;
Automatically frame replicated blocks (6) are for realizing mutual with the data bus signal of the decoding logic module (71) of FPGA module (7), also for realizing mutual with the address bus signal of the decoding logic module (71) of FPGA module (7), also for realizing mutual with the steering logic signal of the steering logic module (75) of FPGA module (7);
Decoding logic module (71) for to from arbitration modules (74) and automatically the data of frame replicated blocks (6) carry out decoding, and the data interaction between realization and arbitration modules (74);
Arbitration modules (74) is for realizing and inserting order transmission cache module (76) and the conventional data interaction that sends cache module (78), also for being deposited in, insertion order inserts order reception cache module (77), also for standing order being deposited in to the conventional cache module (79) that receives, the also data interaction with steering logic module (75) for realization;
Also for realizing, the data of all input arbitration modules (74) are arbitrated, concrete arbitrated procedure is: whether judgement finishes from the frame of the stack pointer of automatic frame replicated blocks (6), thereby determines whether to continue to read this frame data; Also for judging the type of the frame of stack pointer, and according to the type of frame, the content of this frame is write and inserts order reception cache module (77) or the conventional cache module (79) that receives;
Steering logic module (75) is for realizing mutual with the control signal of interface bus, also for automatic frame replicated blocks (6) are resetted;
Insert order send cache module (76) for and write the mutual of data inserting between buffer memory decoding module (72), also for store and sends the data inserting of certainly writing buffer memory decoding module (72);
Conventional send cache module (78) for and write the mutual of routine data between buffer memory decoding module (72), also for store and send oneself, write the data of buffer memory decoding module (72);
Insert order receive cache module (77) for and read the mutual of data inserting between buffer memory decoding module (73), also for storing and send the data inserting from arbitration modules (74);
Conventional receive cache module (79) for and read the mutual of routine data between buffer memory decoding module (73), also for storing and send the routine data from arbitration modules (74);
Write buffer memory decoding module (72) for realize and interface bus between data interaction, also for receiving from the data of interface bus and by these data, deposit in and insert order and send cache module (76) or the conventional cache module (78) that sends;
Read buffer memory decoding module (73) for realize and interface bus between data interaction, also for reading, insert the data that order receives cache module (77) and conventional reception buffer memory (79).
2. the 1553B bus hardware timing communication test device repeating based on automatic frame according to claim 1, is characterized in that, it also comprises 1553B Bussing connector (3), an isolating transformer (4) and No. two isolating transformers (5);
1553B Bussing connector (3) for realize and measurand (2) between communication data signal mutual, also for and an isolating transformer (4) and No. two isolating transformers (5) between voltage signal mutual;
An isolating transformer (4) and No. two isolating transformers (5) all for realize with the voltage signal between frame replicated blocks (6) automatically alternately; An isolating transformer (4) and No. two isolating transformers (5) are also for the protection to the voltage signal of 1553B Bussing connector (3) and automatic frame replicated blocks (6).
3. the timing communication test method of the 1553B bus hardware timing communication test device repeating based on automatic frame according to claim 2, is characterized in that, this method of testing comprises the steps:
Step 1, host computer send order by interface bus to the buffer memory decoding module (72) of writing in FPGA module (7), automatically frame replicated blocks (6) trigger interrupt procedure simultaneously, now the arbitration modules (74) in FPGA module (7) reads the stack pointer of automatic frame replicated blocks (6) by decoding logic module (71), obtains message number;
Step 2, arbitration modules (74) read the command word content in stack pointer, and judge the state of this command word place frame;
If the state of command word place frame is transmission state, arbitration modules (74) judges whether these frame data finish, execution step three; If the state of command word place frame is accepting state, arbitration modules (74) judges the type of this frame and performs step four;
If the data of the frame at the command frame place described in step 3 step 2 do not finish, repeating step two continues to read these frame data; If the data of the frame at the command frame place described in step 2 finish, arbitration modules (74) stops reading the content of this frame, and whether be sky according to priority judgement insertion order transmission cache module (76) and the conventional cache module (78) that sends, execution step 31;
Whether if it is empty that step 3 one is inserted order transmission cache module (76), continuing judgement conventional transmission cache module (78) is empty, and perform step three or two;
If the conventional cache module (78) that sends of step 3 two is empty, arbitration modules resets automatic frame replicated blocks (6) by steering logic module (75); If it is not empty conventional, sending cache module (78), and arbitration modules (74) reads the content of conventional transmission cache module (78) and writes automatic frame replicated blocks (6) by decoding logic module;
If insert, ordering and sending cache module (76) is not sky, and arbitration modules (74) reads and inserts the content of order transmission cache module (76) and write automatic frame replicated blocks (6) by sending from insertion order the content reading cache module (76);
Step 3 three, automatic frame replicated blocks (6) send to measurand (2) by the content depositing in by an isolating transformer (4), No. two isolating transformers (5) and 1553B Bussing connector (3); Then measurand is back to automatic frame replicated blocks by the content depositing in through 1553B Bussing connector, two isolating transformers, waits for and triggers interrupt procedure next time, and return to step 1;
If it is to insert frame that step 4 arbitration modules (74) judgement draws this frame, arbitration modules (74) reads the content of this insertion frame and this insertion content frame is write and inserted in order reception cache module (77), then performs step five;
If arbitration modules (74) judgement show that this frame is conventional frame, arbitration modules (74) reads the content of conventional frame and the content of this routine frame is write to conventional reception in cache module (79), execution step five;
If the data of the frame at the insertion frame described in step 5 step 4 or conventional frame place do not finish, arbitration modules continues to read the data of inserting frame or conventional frame; If the data of the frame at the insertion frame described in step 4 or conventional frame place finish, arbitration modules (74) stops reading the content of this frame, read buffer memory decoding module (73) and read the data of inserting in order reception cache module (77) or conventional reception cache module (79), these data are back to host computer through interface bus, whether arbitration modules (74) is sky according to priority judgement insertion order transmission cache module (76) and the conventional cache module (78) that sends simultaneously, execution step 31.
4. the 1553B bus hardware timing communication test device repeating based on automatic frame according to claim 1, is characterized in that, frame replicated blocks (6) adopt the 1553B interface chip of ACE/MiniACE series to realize automatically.
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