CN104022657A - Control circuit and control method - Google Patents

Abstract

A control circuit and a control method. The control method is used for controlling the active clamped flyback power converter. The control method comprises the following steps: generating a switching signal according to the feedback signal to switch the low-side transistor and regulate the output of the active-clamping flyback power converter; generating an active clamp signal after the switching signal is disabled; generating a hysteresis bias to adjust the feedback signal; and periodically generating a pulse signal to enable the switching signal. The low side transistor switches the transformer. The switching signal drives the low side transistor. The active clamp signal is used to drive the high side transistor. The pulse width of the active clamping signal is determined by the first resistor. The high side transistor is connected in series with the capacitor to form an active clamping circuit. In the heavy load state, the minimum frequency of the switching signal is determined by the second resistor.

Description

Control circuit and control method

technical field

The invention relates to an active clamping flyback power converter, in particular to a control circuit for the active clamping flyback power converter.

Background technique

Existing active clamping circuits can only achieve ZVS under certain load conditions. Furthermore, high circulating currents during light loads lead to higher power loss issues. Related techniques can be found in U.S. Patent No. 5,570,278 entitled "Clamped Continuous Flyback Power Converter", U.S. Patent No. 6,069,803 entitled "Offset Resonance Zero Voltage Switching Flyback Converter" and U.S. Patent No. 6,069,803 entitled "Active-clamp Circuit for Quasi -resonant Flyback Power Converter Power Converter" and No. 20110305048 US patent application.

Contents of the invention

Therefore, the present invention proposes a control circuit for actively clamping a flyback power converter. It achieves zero voltage switching at heavy loads and high efficiency at light loads. The purpose of the present invention is to provide a method and a device, which can ensure that the active-clamp flyback power converter realizes zero-voltage switching under heavy load conditions and achieves high efficiency under light load conditions.

The present invention provides a control circuit for actively clamping a flyback power converter. The control circuit includes a low-side transistor, a high-side transistor, a high-side drive circuit, a controller and a charging pump circuit. Low-side transistors are used to switch the transformer. A high-side transistor is connected in series with a capacitor to form an active clamp circuit. This active clamping circuit is connected in parallel with the transformer. The high-side driving circuit is used to drive the high-side transistor. A controller generates a switching signal as well as an active clamping signal. The switching signal is used to drive the low-side transistor. A switching signal is generated based on the feedback signal to regulate the output of the actively clamped flyback power converter. The active clamping signal is coupled to the high-side driving circuit to control the high-side transistor. The pulse width of the active clamp signal is determined by the first resistor. The active clamp signal is enabled after the toggle signal is disabled. The toggle signal can be enabled after the active clamp signal is disabled. Under heavy load conditions, the minimum frequency of the switching signal is determined by the second resistor. The control circuit includes a hysteretic bias generator and a capacitor. The hysteretic bias generator generates a hysteretic bias voltage to adjust the feedback signal. The comparator has a light load threshold to control the hysteretic bias. The comparator controls the hysteretic bias according to the value of the feedback signal and the light load threshold. The switching signal will be activated according to the pulse signal. The pulse signal is periodically generated by an oscillator circuit of the controller. The charge-pump circuit includes a diode and a charge-pump capacitor. The diode is coupled to the supply voltage. The charge-pump capacitor and the diode are connected in series with each other. The charge pump capacitor is coupled to the high voltage side drive circuit.

The present invention also provides a control method for controlling the active-clamp flyback power converter. The control method includes the following steps: generating a switching signal according to the feedback signal to switch the low-side transistor and adjust the output of the active-clamp flyback power converter; and generating the active-clamping signal after the switching signal is disabled. The low-side transistor switches the transformer. The switching signal drives the low-side transistor. The active clamping signal is used to drive the high-side transistor. The pulse width of the active clamp signal is determined by the first resistor. A high-side transistor is connected in series with a capacitor to form an active clamp circuit. This active clamping circuit is connected in parallel with the transformer. The active clamp signal is enabled after the toggle signal is disabled. The toggle signal is enabled after the active clamp signal is disabled. Under heavy load conditions, the minimum frequency of the switching signal is determined by the second resistor. The control method also includes the step of generating a hysteretic bias to adjust the feedback signal. The hysteretic bias is generated based on the value of the feedback signal and the light load threshold. The control method also includes the step of periodically generating a pulse signal to enable the switching signal. This pulse signal determines the maximum on-time of the switching signal.

Description of drawings

FIG. 1 shows a flyback power converter according to an embodiment of the present invention.

2A-2D respectively show four states of the current of the power converter according to an embodiment of the present invention.

Figure 3 shows the waveforms of the switching signal, the active clamping signal, and the circulating current.

Figure 4 shows intermittent waveforms of the switching signal and the active clamping signal.

FIG. 5 shows a controller in a power converter according to an embodiment of the invention.

FIG. 6 shows an oscillation circuit in a controller according to an embodiment of the present invention.

FIG. 7 shows a signal generating circuit in a controller according to an embodiment of the present invention.

FIG. 8A shows the waveforms of the ramp signal and the pulse signal.

FIG. 8B shows the waveforms of ramp signal, pulse signal, switching signal and active clamping signal.

FIG. 9A shows a circuit architecture of a pulse generator in an oscillation circuit according to an embodiment of the invention.

FIG. 9B shows the waveforms of the input signal and the output signal of the pulse generator in FIG. 9A.

FIG. 10A shows a circuit architecture of a delay circuit in a signal generating circuit according to an embodiment of the present invention.

FIG. 10B shows the waveforms of the input signal and the output signal of the delay circuit in FIG. 10A.

【Symbol Description】

figure 1:

10～transformer; 11～leakage inductance;

15～capacitor; 20～transistor (low voltage side transistor);

25～body diode; 30～transistor (high voltage side transistor);

35～body diode; 40～capacitor;

43～rectifier; 45～capacitor;

50～high voltage side drive circuit; 65～capacitor;

60～rectifier; 70～diode;

75～capacitor; 81, 82～resistor;

90～optical coupler; 93～resistor;

95～voltage regulator; 100～controller;

N _A ～auxiliary coil; N _P ～primary side coil;

N _S ～secondary side coil; S ₁ ～switching signal;

S ₂ ～active clamping signal; V _CC ～supply voltage;

V _FB ～feedback signal; V _IN ～input voltage;

V _O ~ output voltage;

Figure 2A-Figure 2D:

10～transformer; 11～leakage inductance;

15～capacitor; 20～transistor (low voltage side transistor);

25～body diode; 28～parasitic capacitor;

30～transistor (high voltage side transistor);

35～body diode; 38～parasitic capacitor;

40～capacitor; 43～rectifier;

45～capacitor; I _CR ～circulating current;

I _DS , I _P , I _S ~current; N _P ~primary side coil;

N _S ～secondary side coil; S ₁ ～switching signal;

S ₂ ～active clamping signal; T ₁ …T ₄ ～state;

V _IN ～input voltage; V _O ～output voltage;

image 3:

I _CR ～circulating current; S ₁ ～switching signal;

S ₂ ~ active clamping signal; T _CH ~ period of state T ₂ ;

T _DS ~ the maximum period of state T ₃ ; T _S1 ~ the pulse width of switching signal S ₁ ;

T _S2 ~ the pulse width of the active clamping signal S ₂ ;

Figure 4:

S ₁ ~ switching signal; S ₂ ~ active clamping signal;

T _BT ~ Intermittent period;

Figure 5:

100～controller; 110～comparator;

111～trigger; 112～AND gate;

113～inverter; 115～AND gate;

117～current source; 118～switch;

119～comparator; 120～level shift transistor;

125, 126～resistor; 130～oscillating circuit;

200～signal generation circuit; CLR～clear signal;

PLS～pulse signal; RMP～ramp signal;

S ₁ ~ switching signal; S ₂ ~ active clamping signal;

V _B ～signal; V _CC ～supply voltage;

V _FB ～feedback signal; V _TL ～light load threshold;

Figure 6:

127～capacitor; 128～switch;

130～oscillating circuit; 131～current source;

132～switch; 135～current source;

136 ~ switch; 141, 142, 145 ~ comparator;

146, 151, 152～NAND gate; 156～inverter;

157～inverter; 165～or gate;

300～pulse generator; CKA, CKB～frequency signal;

CLR～clear signal; PLS～pulse signal;

RMP ~ ramp signal; S ₂ ~ active clamping signal;

S _IN1 ~ signal; S _OUT1 ~ output pulse signal;

V _H , V _L ～trip point voltage; V _M ～threshold voltage;

Figure 7:

200～signal generating circuit; 270～comparator;

271～inverter; 280～current source;

281～switch; 285～capacitor;

290～trigger; 350～delay circuit;

S ₁ ~ switching signal; S ₂ ~ active clamping signal;

S _IN2 ~ signal; S _OUT2 ~ output pulse signal;

V _W ~threshold;

Figure 8A-8B

PLS～pulse signal; RMP～ramp signal;

S ₁ ~ switching signal; S ₂ ~ active clamping signal;

V _H , V _L ～trip point voltage; V _M ～threshold voltage;

Figure 9A-9B:

300～pulse generator; 310～current source;

321～inverter; 322～transistor;

325～capacitor; 327～inverter;

329～AND gate; S _IN1 ～signal;

S _OUT1 ~ output pulse signal;

T _P ~ the pulse width of the output pulse signal S _OUT1 ;

Figure 10A-Figure 10B:

350～delay circuit; 361～inverter;

362～transistor; 360～current source;

365～capacitor; 369～AND gate;

S _IN2 ~ signal; S _OUT2 ~ output pulse signal;

T _B ˜the delay time generated by the delay circuit 350 .

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

FIG. 1 shows a flyback power converter according to an embodiment of the present invention. The transformer 10 receives the input voltage V _IN of the power converter. A transistor (also referred to as “low-side transistor”) 20 is coupled to switch the primary-side winding N _P of the transformer 10 . The controller 100 generates a switching signal S ₁ at its terminal S1, and the switching signal S ₁ is used to drive the transistor 20 to adjust the output voltage V _O of the power converter. The switching signal S ₁ is generated according to the feedback signal V _FB at the terminal FB of the controller 100 . The feedback signal V _FB is related to the output voltage V _O of the power converter. The secondary winding N _S of the transformer 10 will generate an output voltage V _O through a rectifier 43 and a capacitor 45 . The resistor 93, the voltage regulator 95 (Zene (gene) nanodiode) and the optocoupler 90 form a feedback circuit to generate a feedback signal V _FB according to the output voltage V _O. Transformer 20 includes an auxiliary winding N _A which, via a rectifier 60 , generates a supply voltage V _CC across a capacitor 65 . The supply voltage V _CC is used to power the controller 100 . Transistor (also referred to as "high-side transistor") 30 in series with capacitor 15 has formed an active clamping circuit. This active clamp circuit and the primary side winding _NP of the transformer 10 are connected in parallel with each other. When the transistor 20 is turned off, the energy of the leakage inductance 11 of the transformer 10 will be stored in the capacitor 15 through the transistor 30 and its body diode 35 . The high voltage side driving circuit 50 is used to drive the transistor 30 . The charge-pump circuit composed of the diode 70 and the capacitor 75 receives the supply voltage V _CC and supplies power to the high-side driving circuit 50 . The capacitor 75 and the diode 70 are connected in series with each other. In the embodiment of FIG. 1 , the transistor 20 , the controller 100 , the high voltage side driver circuit 50 , the active clamping circuit and the charge-pump circuit form a control circuit.

The controller 100 generates an active clamping signal S ₂ on its terminal S2 to control the high-side driving circuit 50 . The pulse width of the active clamping signal S ₂ is determined by the resistance value of the resistor 81 . The resistor 81 is coupled to the terminal RT of the controller 100 . Active clamping signal _S2 is only enabled when switching signal _S1 is disabled. During heavy load conditions, the switching signal S ₁ will be enabled after the active clamping signal S ₂ is disabled. The resistor 82 is coupled to the terminal RM of the controller 100 to determine the minimum frequency (maximum on-time) of the switching signal _S1 under heavy load conditions.

2A-2D respectively show four states of the current of the power converter according to the embodiment of the present invention. Referring to FIG. 2A , in the state _T1 , the switching signal _S1 turns on (ON) the transistor 20 . The current _IP flows through the transformer 10 and stores energy in the transformer 10 . This energy will also be stored in the leakage inductance 11 of the transformer 10 .

Referring to FIG. 2B , in the state T ₂ , the switching signal S ₁ turns off (OFF) the transistor 20 . The energy stored in the transformer 10 will be transferred to the output of the power converter via the current _IS to generate the output voltage V _O . In addition, the energy stored in the transformer 10 and the leakage inductance 11 will be transferred to the capacitor 15 through the body diode 35 of the transistor 30 . The circulating current I _CR represents the energy flowing into the capacitor 15 . after this. Active clamp signal _S2 will turn on transistor 30 .

Referring to FIG. 2C , in the state T ₃ , the energy stored in the capacitor 15 will be reused by the transformer 10 and the leakage inductance 11 through the transistor 30 . Capacitor 15 is discharged by circulating current I _CR through leakage inductance 11 . The leakage inductance 11 and the capacitor 15 form a resonant tank and determine its resonant frequency.

Referring to FIG. 2D , in state T ₄ , active clamp signal S ₂ turns off transistor 30 . The energy stored in the leakage inductance 11 will be transferred to the input voltage V _IN through the current I _DS . At the same time, the parasitic capacitor 28 of transistor 20 will discharge and the body diode 25 of transistor 20 can be turned on to achieve zero voltage switching operation of transistor 20 (state T ₁ ) in the next switching cycle.

FIG. 3 shows waveforms of switching signal S ₁ , active clamping signal S ₂ and circulating current I _CR . The period T _CH is a period representing the state _T2 . The period T _DS is the maximum period representing the state _T3 . T _S1 represents the pulse width of the switching signal _S1 . T _S2 is the pulse width representing the active clamp signal _S2 . In order to initiate state T ₃ (period T _DS ), active clamping signal S ₂ must be enabled before period T _CH ends. In order to complete zero-voltage switching, the active clamping signal _S2 must be disabled before the end of the period T _DS . Both the period T _CH and the period T _DS are determined by the resonant frequency of the resonant tank.

FIG. 4 shows burst waveforms of the switching signal _S1 and the active clamping signal _S2 . The period T _BT is a burst period.

FIG. 5 shows a controller 100 in a power converter according to an embodiment of the present invention. The controller 100 includes an oscillation circuit 130 that generates a pulse signal PLS, a ramp signal RMP, and a clear signal CLR. The pulse signal PLS enables the switching signal S ₁ through the inverter 113 , the flip-flop 111 and the AND gate 115 . The active clamping signal S ₂ and the resistor 82 (shown in FIG. 1 ) are coupled to the oscillation circuit 130 for generating the switching signal S ₁ . Therefore, once the active clamping signal _S2 is disabled, the switching signal _S1 is enabled. The resistor 82 determines the minimum switching frequency of the switching signal _S1 (lowest switching frequency). The resistor 81 (shown in FIG. 1 ) and the switching signal S ₁ are coupled to the signal generating circuit 200 to generate the active clamping signal S ₂ . Once the switching signal S ₁ is disabled, the active clamping signal S ₂ is enabled. The level shift transistor 120 and the resistors 125 and 126 generate a signal V _B according to the feedback signal V _FB . The ramp signal RMP is compared with the signal V _B in the comparator 110 to generate a signal for disabling the switching signal S ₁ through the AND gate 112 , thereby realizing the PWM operation. The clear signal CLR generated by the oscillation circuit 130 is used to reset the flip-flop 111 to disable the switching signal S ₁ and limit the maximum on-time of the switching signal S ₁ .

The comparator 119 is used to compare the signal V _B with the light load threshold V _TL . When the signal V _B is lower than the light load threshold V _TL , the hysteresis bias will start to decrease from the current level of the signal V _B . The hysteresis bias voltage generator including the resistors 125 and 126 and the current source 117 generates the hysteresis voltage, which is determined by the magnitude of the current source 117 and the equivalent resistance of the resistors 125 and 126 . A switch 118 controlled by a comparator 119 turns on/off the current source 117 . When the signal V _B is higher than the light load threshold V _TL , a hysteresis bias will be added to the signal V _B . When the signal V _B is lower than the light load threshold V _TL , the hysteresis bias starts to decrease from the current level of the signal V _B . Therefore, through this feedback loop, the hysteresis bias will cause intermittent switching to reduce the switching frequency of the switching signal S ₁ and improve the light load performance under light load conditions (signal V _B is lower than the light load threshold V _TL ).

FIG. 6 shows the oscillation circuit 130 in the controller 100 according to an embodiment of the present invention. The current sources 131 and 135 charge and discharge the capacitor 127 through the switches 132 and 136 respectively. Ramp signal RMP is generated across capacitor 127 . The ramp signal RMP is also coupled to the comparators 141 , 142 , and 145 . The comparator 141 has a trip-point voltage V _H . Comparator 142 has a trip point voltage V _L . Comparator 145 has a threshold voltage V _M . The level of the trip point voltage V _H is greater than the level of the threshold voltage V _M . The level of the threshold voltage V _M is greater than the level of the trip point voltage V _L . The NAND gates 151 and 152 form a latch circuit which receives the output signals of the comparators 141 and 142 . The latch circuit and the inverter 156 generate clock signals CKA and CKB. The frequency signal CKA is used to control the switch 136 to discharge the capacitor 127 . The frequency signal CKB is used to control the switch 132 to charge the capacitor 127 . The output of the comparator 145 and the frequency signal CKA pass through the NAND gate 146 to generate the clear signal CLR. The falling edge of the active clamping signal S ₂ generates a click signal at an input terminal of the OR gate 165 through the inverter 157 and the pulse generator 300 . The other input terminal of the OR gate 165 receives the frequency signal CKA. Both the click signal and the frequency signal CKA pass through the OR gate 165 to generate the pulse signal PLS. Therefore, whenever the active clamping signal _S2 is disabled, the pulse signal PLS will be generated. In addition, when the maximum oscillation period of the ramp signal RMP is reached, the pulse signal PLS will be generated according to the clock signal CKA. Since the clear signal CLR is generated according to the frequency signal CKA (the frequency signal CKA is associated with the pulse signal PLS), the pulse signal PLS will thus limit the maximum on-time of the switching signal _S1 . The magnitude of the current source 131 is controlled by the resistance of the resistor 82 (shown in FIG. 1 ) connected to the terminal RM. Therefore, the resistor 82 is used to determine the maximum oscillation period of the ramp signal RMP.

FIG. 7 shows a signal generating circuit 200 in the controller 100 according to an embodiment of the present invention. The switching signal S ₁ passes through the inverter 271 , the delay circuit 350 and the flip-flop 290 to generate the active clamping signal S ₂ . Therefore, when the switching signal _S1 is disabled, the active clamping signal _S2 will be enabled after a delay time determined by the delay circuit 350 . Once the switching signal _S1 is disabled, the switch 281 will be turned off. Current source 280 will begin charging capacitor 285 . When the voltage across the capacitor 285 is higher than the threshold V _W , the comparator 270 disables the active clamping signal S ₂ via the flip-flop 290 . The magnitude of the current source 280 is controlled by the resistance of the resistor 81 (shown in FIG. 1 ) coupled to the terminal RT. Therefore, the resistor 81, the capacitor 285 and the threshold V _W determine the pulse width of the active clamp signal _S2 . The resistor 81 is implemented to determine the pulse width T _S2 of the active clamping signal S ₂ to achieve zero voltage switching. The pulse width T _S2 must satisfy the following conditions: T _S2 >T _CH and T _S2 <"T _CH +T _DS " (shown in FIG. 3 ).

FIG. 8A shows the waveforms of the ramp signal RMP and the pulse signal PLS. The pulse signal PLS in FIG. 8A is generated according to the frequency signal CKA, as shown in FIG. 6 .

FIG. 8B shows the waveforms of the ramp signal RMP, the pulse signal PLS, the switching signal _S1 and the active clamping signal _S2 . Active clamping signal _S2 will be generated after switching signal _S1 is disabled. Switching signal _S1 will be generated after active clamping signal _S2 is disabled. That is, the switching signal S ₁ and the active clamping signal S ₂ are generated in an interleaved manner and are not activated at the same time. The pulse signal PLS is generated periodically to enable the switching signal S _{1 when the switching signal S 1 is} not enabled during the intermittent switching mode. The pulse signal PLS in FIG. 8B is generated according to the click signal generated on the output of the pulse generator 300 . In addition, the maximum on-time of the switching signal _S1 is limited by the maximum period of the ramp signal RMP.

FIG. 9A shows the pulse generator 300 within the oscillation circuit 130 according to an embodiment of the present invention. Referring to FIG. 9A , a current source 310 is coupled to charge a capacitor 325 . The transistor 322 is used to discharge the capacitor 325 . The signal S _IN1 at the terminal IN1 of the pulse generator 300 controls the transistor 322 via the inverter 321 . Signal S _IN1 is also coupled to the input of AND gate 329 . The other input end of the AND gate 329 is coupled to the capacitor 325 through the inverter 327 . The pulse width of the output pulse signal S _OUT1 at the terminal OUT1 of the pulse generator 300 is determined by the current of the current source 310 and the capacitance of the capacitor 325 . In this embodiment, the signal S _IN1 received by the pulse generator 300 of FIG. 9A is provided by the output terminal of the inverter 157 (shown in FIG. 6 ), and the output pulse signal S _OUT1 is provided to the OR gate 165 (shown in FIG. In Figure 6) the input terminal is used as a click signal.

FIG. 9B shows the waveforms of the input signal S _IN1 and the output pulse signal S _OUT1 of the pulse generator 300 . T _P represents the pulse width of the output pulse signal S _OUT1 .

FIG. 10A is a circuit configuration diagram showing the delay circuit 350 in the signal generation circuit 200 . Referring to FIG. 10A , a current source 360 is coupled to charge a capacitor 365 . The transistor 362 is coupled to discharge the capacitor 365 . The signal S _IN2 at the terminal IN2 of the delay circuit 350 controls the transistor 362 through the inverter 361 . Signal S _IN2 is also coupled to the input of AND gate 369 . The other input terminal of the AND gate 369 is coupled to the capacitor 365 . The pulse width of the output pulse signal S _OUT2 at the terminal OUT2 of the delay circuit 350 is determined by the current of the current source 360 and the capacitance of the capacitor 365 . In this embodiment, the signal S _IN2 received by the delay circuit 350 of FIG. 10A is provided by the output terminal of the inverter 271 (shown in FIG. 7 ), and the output pulse signal S _OUT2 is provided to the flip-flop 290 (shown in FIG. 7 ). FIG. 7 ) to generate the active clamping signal S ₂ .

FIG. 10B shows the waveforms of the input signal S _IN2 and the output pulse signal S _OUT2 of the delay circuit 350 . T _B represents the delay time generated by the delay circuit 350 .

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope defined by the appended claims.

Claims (12)

1. A control circuit for actively clamping a flyback power converter comprising: Low-side transistors for switching transformers; a high-voltage side transistor connected in series with a capacitor to form an active clamp circuit, wherein the active clamp circuit is connected in parallel with the transformer; a high-side driving circuit for driving the high-side transistor; and a controller that generates a switching signal and an active clamping signal; Wherein, the switching signal is used to drive the low-side transistor, and the switching signal is generated according to a feedback signal to adjust the output of the actively clamped flyback power converter; and Wherein, the active clamping signal is coupled to the high-voltage side drive circuit to control the high-voltage side transistor, and the pulse width of the active clamping signal is determined by a first resistor. 2. The control circuit of claim 1, wherein the active clamping signal is enabled after the switching signal is disabled, and the switching signal is enableable after the active clamping signal is disabled. 3. The control circuit of claim 1, wherein the minimum frequency of the switching signal is determined by the second resistor under heavy load conditions. 4. The control circuit of claim 1, wherein the controller comprises: a hysteretic bias generator that generates a hysteretic bias to adjust the feedback signal; and a comparator with a light load threshold to control the hysteretic bias; Wherein, the comparator controls the hysteresis bias voltage according to the value of the feedback signal and the light load threshold. 5. The control circuit of claim 1, wherein the switching signal is to be enabled according to a pulse signal, and the pulse signal is periodically generated by an oscillation circuit of the controller. 6. The control circuit according to claim 1, further comprising a charge-pump circuit, wherein the charge-pump circuit comprises: a diode coupled to the supply voltage; and a charge-pump capacitor connected in series with the diode; Wherein, the charge-pump capacitor is coupled to the high-voltage side drive circuit. 7. A control method for controlling an actively clamped flyback power converter, comprising: generating a switching signal based on a feedback signal to switch a low side transistor and regulate the output of the actively clamped flyback power converter; and generating an active clamping signal after said switching signal is disabled; Wherein, the low-voltage side transistor switches the transformer, and the switching signal drives the low-voltage side transistor; Wherein, the active clamping signal is used to drive the high-voltage side transistor, and the pulse width of the active clamping signal is determined by the first resistor; and Wherein, the high-voltage side transistor is connected in series with a capacitor to form an active clamping circuit, and the active clamping circuit is connected in parallel with the transformer. 8. The control method of claim 7, wherein the active clamping signal is enabled after the switching signal is disabled, and the switching signal is enabled after the active clamping signal is disabled. 9. The control method according to claim 7, wherein the minimum frequency of the switching signal is determined by the second resistor under heavy load conditions. 10. The control method according to claim 7, further comprising: generating a hysteretic bias to adjust the feedback signal; Wherein, the hysteresis bias voltage is generated according to the value of the feedback signal and the light load threshold. 11. The control method according to claim 7, further comprising: A pulse signal is periodically generated to enable the switching signal. 12. The control method according to claim 11, wherein the pulse signal determines a maximum on-time of the switching signal.