CN104022657A - Control circuit and control method - Google Patents
Control circuit and control method Download PDFInfo
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- CN104022657A CN104022657A CN201410299469.XA CN201410299469A CN104022657A CN 104022657 A CN104022657 A CN 104022657A CN 201410299469 A CN201410299469 A CN 201410299469A CN 104022657 A CN104022657 A CN 104022657A
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Abstract
The invention provides a control circuit and a control method. The control method is used for controlling an active-clamp flyback power converter. The control method comprises the steps of generating a switching signal according to a feedback signal to switch a low voltage side transistor and regulate the output of the active-clamp flyback power converter; generating an active-clamp signal after the switching signal is forbidden; generating lag bias voltage to regulate the feedback signal; periodically generating a pulse signal to start the switching signal, wherein the low voltage side transistor is used for switching a transformer; the switching signal is used for driving the low voltage side transistor; the active-clamp signal is used for driving a high voltage side transistor; the pulse width of the active-clamp signal is determined by a first resistor; the high voltage side transistor is connected with a capacitor in series to form an active-clamp circuit; in the state of heavy load, the minimum frequency of the switching signal is determined by a second resistor.
Description
Technical field
The present invention relates to a kind of initiatively strangulation flyback power converter, particularly a kind of control circuit for active strangulation flyback power converter.
Background technology
Existing active clamped circuit is realized zero voltage switching only under specific load condition.In addition, the high circulating current during underload causes higher power loss problem.Relevant technology can be called in name " Clamped Continuous Flyback Power Converter " and be numbered 5,570,278 United States Patent (USP), name are called " Offset Resonance Zero Voltage Switching Flyback Converter " and are numbered 6,069,803 United States Patent (USP) and name are called " Active-clamp Circuit for Quasi-resonant Flyback Power Converter Power Converter " and are numbered in 20110305048 U.S. patent application case and obtain.
Summary of the invention
Therefore, the present invention proposes a kind of control circuit, and it is for active strangulation flyback power converter.It can realize zero voltage switching and can be issued to high efficiency in light load condition in heavy duty situation.The object of the invention is to propose a kind of method and device, it can guarantee that initiatively strangulation flyback power converter is realized zero voltage switching and is issued to high efficiency in light load condition in heavy duty situation.
The invention provides a kind of control circuit, for active strangulation flyback power converter.This control circuit comprises low-pressure side transistor, high-pressure side transistor, high-pressure side driving circuit, controller and fills pump circuit.Low-pressure side transistor is used for switching transformer.High-pressure side transistor AND gate capacitor's series is to form initiatively clamped circuit.This is clamped circuit and transformers connected in parallel initiatively.High-pressure side driving circuit is used for driving high-pressure side transistor.Controller generates switching signal and active strangulation signal.Switching signal is used for driving low-pressure side transistor.Switching signal generates according to feedback signal, to regulate the initiatively output of strangulation flyback power converter.Initiatively strangulation signal couples high-pressure side driving circuit to control high-pressure side transistor.Initiatively the pulse duration of strangulation signal is determined by the first resistor.Initiatively strangulation signal is enabled after switch signal forbidden.Switching signal can be enabled after active strangulation signal disables.Under heavy duty state, the minimum frequency of switching signal is determined by the second resistor.Control circuit comprises sluggish bias voltage maker and capacitor.Sluggish bias voltage maker generates sluggish bias voltage to adjust feedback signal.Comparator has underload threshold value to control sluggish bias voltage.Comparator is controlled sluggish bias voltage according to value and the underload threshold value of feedback signal.Switching signal will be enabled according to pulse signal.This pulse signal is periodically generated by an oscillating circuit of controller.Filling pump circuit comprises diode and fills pump capacitor.Diode couples supply voltage.Filling pump capacitor and diode is one another in series.Fill pump capacitor and couple high-pressure side driving circuit.
The present invention also provides a kind of control method, in order to control initiatively strangulation flyback power converter.This control method comprises the following steps: generate switching signal according to feedback signal, to switch low-pressure side transistor and to regulate the initiatively output of strangulation flyback power converter; And after switch signal forbidden, generate initiatively strangulation signal.Low-pressure side transistor switching transformer.Switching signal drives low-pressure side transistor.Initiatively strangulation signal is used for driving high-pressure side transistor.Initiatively the pulse duration of strangulation signal is determined by the first resistor.High-pressure side transistor AND gate capacitor's series is to form initiatively clamped circuit.This is clamped circuit and transformers connected in parallel initiatively.Initiatively strangulation signal is enabled after switch signal forbidden.Switching signal is enabled after active strangulation signal disables.Under heavy duty state, the minimum frequency of switching signal is determined by the second resistor.This control method also comprises step: generate sluggish bias voltage to adjust feedback signal.Sluggish bias voltage generates according to the value of feedback signal and underload threshold value.This control method also comprises step: periodically production burst signal, and to enable switching signal.This pulse signal has determined the maximum turn-on time of switching signal.
Brief description of the drawings
Fig. 1 represents flyback power converter according to an embodiment of the invention.
Fig. 2 A-Fig. 2 D represents respectively according to one embodiment of the invention, four kinds of states of the electric current of power converter.
Fig. 3 represents the waveform of switching signal, initiatively strangulation signal and circulating current.
Fig. 4 represents the waveform at intermittence of switching signal and active strangulation signal.
Fig. 5 represents the controller in power converter according to one embodiment of the invention.
Fig. 6 represents the oscillating circuit in controller according to one embodiment of the invention.
Fig. 7 represents the signal generating circuit in controller according to one embodiment of the invention.
Fig. 8 A represents the waveform of ramp signal and pulse signal.
Fig. 8 B represents the waveform of ramp signal, pulse signal, switching signal and active strangulation signal.
Fig. 9 A represents the circuit framework of the impulse generator in oscillating circuit according to one embodiment of the invention.
Fig. 9 B is illustrated in the input signal of impulse generator and the waveform of output signal in Fig. 9 A.
Figure 10 A represents the circuit framework of the delay circuit in signal generating circuit according to one embodiment of the invention.
Figure 10 B is illustrated in the input signal of delay circuit and the waveform of output signal in Figure 10 A.
[symbol description]
Fig. 1:
10～transformer; 11～leakage inductance;
15～capacitor; 20～transistor (low-pressure side transistor);
25～body diode; 30～transistor (high-pressure side transistor);
35～body diode; 40～capacitor;
43～rectifier; 45～capacitor;
50～high-pressure side driving circuit; 65～capacitor;
60～rectifier; 70～diode;
75～capacitor; 81,82～resistor;
90～optical coupler; 93～resistor;
95～voltage adjuster; 100～controller;
N
a～ancillary coil; N
p～primary side coil;
N
s～secondary side coil; S
1～switching signal;
S
2～initiatively strangulation signal; V
cC～supply voltage;
V
fB～feedback signal; V
iN～input voltage;
V
o～output voltage;
Fig. 2 A-Fig. 2 D:
10～transformer; 11～leakage inductance;
15～capacitor; 20～transistor (low-pressure side transistor);
25～body diode; 28～capacitor parasitics;
30～transistor (high-pressure side transistor);
35～body diode; 38～capacitor parasitics;
40～capacitor; 43～rectifier;
45～capacitor; I
cR～circulating current;
I
dS, I
p, I
s～electric current; N
p～primary side coil;
N
s～secondary side coil; S
1～switching signal;
S
2～initiatively strangulation signal; T
1t
4～state;
V
iN～input voltage; V
o～output voltage;
Fig. 3:
I
cR～circulating current; S
1～switching signal;
S
2～initiatively strangulation signal; T
cH～state T
2during;
T
dS～state T
3maximum during; T
s1～switching signal S
1pulse duration;
T
s2～initiatively strangulation signal S
2pulse duration;
Fig. 4:
S
1～switching signal; S
2～initiatively strangulation signal;
T
bT～tempus intercalare;
Fig. 5:
100～controller; 110～comparator;
111～trigger; 112～with door;
113～inverter; 115～with door;
117～current source; 118～switch;
119～comparator; 120～level shift transistor;
125,126～resistor; 130～oscillating circuit;
200～signal generating circuit; CLR～clear signal;
PLS～pulse signal; RMP～ramp signal;
S
1～switching signal; S
2～initiatively strangulation signal;
V
b～signal; V
cC～supply voltage;
V
fB～feedback signal; V
tL～underload threshold value;
Fig. 6:
127～capacitor; 128～switch;
130～oscillating circuit; 131～current source;
132～switch; 135～current source;
136～switch; 141,142,145～comparator;
146,151,152～NAND gate; 156～inverter;
157～inverter; 165～or door;
300～impulse generator; CKA, CKB～frequency signal;
CLR～clear signal; PLS～pulse signal;
RMP～ramp signal; S
2～initiatively strangulation signal;
S
iN1～signal; S
oUT1～output pulse signal;
V
h, V
l～trip point voltage; V
m～threshold voltage;
Fig. 7:
200～signal generating circuit; 270～comparator;
271～inverter; 280～current source;
281～switch; 285～capacitor;
290～trigger; 350～delay circuit;
S
1～switching signal; S
2～initiatively strangulation signal;
S
iN2～signal; S
oUT2～output pulse signal;
V
w～threshold value;
Fig. 8 A-Fig. 8 B
PLS～pulse signal; RMP～ramp signal;
S
1～switching signal; S
2～initiatively strangulation signal;
V
h, V
l～trip point voltage; V
m～threshold voltage;
Fig. 9 A-Fig. 9 B:
300～impulse generator; 310～current source;
321～inverter; 322～transistor;
325～capacitor; 327～inverter;
329～with door; S
iN1～signal;
S
oUT1～output pulse signal;
T
p～output pulse signal S
oUT1pulse duration;
Figure 10 A-Figure 10 B:
350～delay circuit; 361～inverter;
362～transistor; 360～current source;
365～capacitor; 369～with door;
S
iN2～signal; S
oUT2～output pulse signal;
T
bthe time of delay that～delay circuit 350 generates.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Fig. 1 represents flyback power converter according to an embodiment of the invention.The input voltage V of transformer 10 received power transducers
iN.Transistor (also referred to as " low-pressure side transistor ") 20 couples the primary side coil N of switching transformer 10
p.Controller 100 generates switching signal S at its end points S1
1, and switching signal S
1be used for the output voltage V of driving transistors 20 with Modulating Power transducer
o.Switching signal S
1the feedback signal V according to the end points FB at controller 100
fBand generate.Feedback signal V
fBoutput voltage V with power converter
obe associated.The secondary side coil N of transformer 10
sto generate output voltage V by rectifier 43 and capacitor 45
o.Resistor 93, voltage adjuster 95 (neat (base) receive diode) and optical coupler 90 form a feedback circuit, with according to output voltage V
ogenerate feedback signal V
fB.Transformer 20 comprises ancillary coil N
a, it generates the supply voltage V that crosses over capacitor 65 by rectifier 60
cC.Supply voltage V
cCbe used for power supply to controller 100.Transistor (also referred to as " high-pressure side transistor ") 30 is connected with capacitor 15 and is formed an active clamped circuit.The primary side coil N of this active clamped circuit and transformer 10
pbe connected in parallel to each other.In the time that transistor 20 disconnects, the energy of the leakage inductance 11 of transformer 10 will by transistor 30 with and body diode 35 deposit in to capacitor 15.High-pressure side driving circuit 50 is used for driving transistors 30.The pump circuit that fills being made up of diode 70 and capacitor 75 receives supply voltage V
cC, and power for high-pressure side driving circuit 50.Capacitor 75 is one another in series with diode 70.In the embodiment in figure 1, transistor 20, controller 100, high-pressure side driving circuit 50, clamped circuit and fill pump circuit and form a control circuit initiatively.
Controller 100 generates initiatively strangulation signal S on its end points S2
2, to control high-pressure side driving circuit 50.Initiatively strangulation signal S
2pulse duration determined by the resistance value of resistor 81.Resistor 81 couples the end points RT of controller 100.Initiatively strangulation signal S
2only at switching signal S
1when forbidding, enable.During heavy duty state, switching signal S
1will be at active strangulation signal S
2after forbidding, enable.Resistor 82 couples the end points RM of controller 100, with the switching signal S that makes decision at heavy duty state
1minimum frequency (maximum turn-on time).
Fig. 2 A-Fig. 2 D represents respectively according to the embodiment of the present invention, four kinds of states of the electric current of power converter.Consult Fig. 2 A, at state T
1under, switching signal S
1connect (ON) transistor 20.Electric current I
pflow through transformer 10 and storage power to transformer 10.This energy also will be stored to the leakage inductance 11 of transformer 10.
Consult Fig. 2 B, at state T
2under, switching signal S
1disconnect (OFF) transistor 20.The energy that is stored in transformer 10 will be by electric current I
sbe sent to the output of power converter, to generate output voltage V
o.In addition the body diode by transistor 30 35 is sent to capacitor 15 by the energy that, is stored in transformer 10 and leakage inductance 11.Circulating current I
cRrepresent to flow into the energy of capacitor 15.After this.Initiatively strangulation signal S
2to connect transistor 30.
Consult Fig. 2 C, at state T
3under, the energy being stored in capacitor 15 will be recycled by transformer 10 and leakage inductance 11 by transistor 30.Capacitor 15 is by circulating current I
cRand discharge by leakage inductance 11.15, leakage inductance 11 and capacitor have formed resonant slots and have determined its resonance frequency.
Consult 2D figure, at state T
4under, initiatively strangulation signal S
2disconnect transistor 30.The energy being stored in leakage inductance 11 will be by electric current I
dSbe sent to input voltage V
iN.At the same time, the capacitor parasitics 28 of transistor 20 will discharge, and the body diode 25 of transistor 20 can be switched on zero voltage switching operation (the state T to realize transistor 20 at next switching cycle
1).
Fig. 3 represents switching signal S
1, strangulation signal S initiatively
2and circulating current I
cRwaveform.T during this time
cHto represent state T
2during.T during this time
dSto represent state T
3maximum during.T
s1to represent switching signal S
1pulse duration.T
s2to represent initiatively strangulation signal S
2pulse duration.For initial state T
3(T during this time
dS), initiatively strangulation signal S
2must during T
cHbefore finishing, enable.In order to complete zero voltage switching, initiatively strangulation signal S
2must during T
dSforbidding before finishing.T during this time
cHand during T
dSall determined by the resonance frequency of resonant slots.
Fig. 4 represents switching signal S
1and active strangulation signal S
2waveform at intermittence (burst waveform).T during this time
bTfor tempus intercalare (burst period).
Fig. 5 represents according to one embodiment of the invention, the controller 100 in power converter.Controller 100 comprises oscillating circuit 130, its production burst signal PLS, ramp signal RMP and clear signal CLR.Pulse signal PLS is by inverter 113, trigger 111 and enable switching signal S with door 115
1.Initiatively strangulation signal S
2and resistor 82 (being shown in Fig. 1) is coupled to oscillating circuit 130 to be used for generating switching signal S
1.Therefore, once active strangulation signal S
2forbidding, switching signal S
1enable.Resistor 82 has determined switching signal S
1minimum switching frequency (minimum switching frequency).Resistor 81 (being shown in Fig. 1) and switching signal S
1be coupled to signal generating circuit 200 to generate initiatively strangulation signal S
2.Once switching signal S
1forbidding, initiatively strangulation signal S
2enable.Level shift transistor 120 and resistor 125 and 126 are according to feedback signal V
fBand generation signal V
b.Ramp signal RMP and signal V
bin comparator 110, compare with by generating to forbid switching signal S with door 112
1a signal, realize by this pulse-width modulation operation.The clear signal CLR that oscillating circuit 130 the generates trigger 111 that is used for resetting, to forbid switching signal S
1and limit switching signal S
1maximum turn-on time.
Comparator 119 is used for comparison signal V
bwith underload threshold value V
tL.As signal V
blower than underload threshold value V
tLtime, magnetic hysteresis bias voltage will be by signal V
bcurrent level start reduce.Comprise resistor 125 and 126 and the magnetic hysteresis bias voltage maker of current source 117 generate above-mentioned hysteresis voltage, the equivalent resistance of its size by current source 117 and resistor 125 and 126 is determined.The switch 118 on/off current sources 117 of being controlled by comparator 119.As signal V
bhigher than underload threshold value V
tL, magnetic hysteresis bias voltage will be added to signal V
b.As signal V
blower than underload threshold value V
tL, magnetic hysteresis bias voltage is by signal V
bcurrent level start reduce.Therefore,, by this feedback loop, magnetic hysteresis bias voltage will cause intermittently switching, to reduce switching signal S
1switching frequency and improve light-load state (signal V
blower than underload threshold value V
tL) under underload usefulness.
Fig. 6 represents according to one embodiment of the invention, the oscillating circuit 130 in controller 100.Current source 131 and 135 is charged and discharges capacitor 127 by switch 132 and 136 respectively.Ramp signal RMP generates across capacitor 127.Ramp signal RMP is also coupled to comparator 141,142, with 145.Comparator 141 has trip point voltage (trip-point voltage) V
h.Comparator 142 has trip point voltage V
l.Comparator 145 has threshold voltage V
m.Trip point voltage V
hlevel be greater than threshold voltage V
mlevel.Threshold voltage V
mlevel be greater than trip point voltage V
llevel.NAND gate 151 and 152 forms latch cicuit, and it receives the output signal of comparator 141 and 142.This latch cicuit and inverter 156 have generated frequency signal CKA and CKB.Frequency signal CKA be used for control switch 136 so that capacitor 127 discharge.Frequency signal CKB be used for control switch 132 so that capacitor 127 charge.The output of comparator 145 and frequency signal CKA generate clear signal CLR by NAND gate 146.Initiatively strangulation signal S
2trailing edge by inverter 157 and impulse generator 300 and or an input of door 165 generate and click signal.Or another input receiving frequency signals CKA of door 165.Click signal and frequency signal CKA both by or door 165 generate pulse signal PLS.Therefore, whenever active strangulation signal S
2when forbidding, pulse signal PLS will be generated.In addition,, in the time reaching the full swing cycle of ramp signal RMP, pulse signal PLS will generate according to frequency signal CKA.Because clear signal CLR generates according to frequency signal CKA (frequency signal CKA is associated with pulse signal PLS), therefore pulse signal PLS will limit switching signal S
1maximum turn-on time.The size of the resistance value control current source 131 of the resistor 82 (being shown in Fig. 1) of connection end point RM.Therefore, resistor 82 use decide the full swing cycle of ramp signal RMP.
Fig. 7 represents according to one embodiment of the invention, the signal generating circuit 200 in controller 100.Switching signal S
1generate initiatively strangulation signal S by inverter 271, delay circuit 350 and trigger 290
2.Therefore, as switching signal S
1when forbidding, initiatively strangulation signal S
2to after the time of delay determining at delay circuit 350, enable.Once switching signal S
1forbidding, switch 281 will be disconnected.Current source 280 will start capacitor 285 to charge.When the voltage of crossing over capacitor 285 is higher than threshold value V
wtime, 270 of comparators are forbidden initiatively strangulation signal S by trigger 290
2.Be coupled to the resistor 81 (being shown in Fig. 1) of end points RT resistance value control the size of current source 280.Therefore, resistor 81, capacitor 285 and threshold value V
wdetermine initiatively strangulation signal S
2pulse duration.Resistor 81 is to implement to decide initiatively strangulation signal S
2pulse width T
s2, to realize zero voltage switching.Pulse width T
s2must meet following condition: T
s2>T
cHand T
s2< " T
cH+ T
dS" (being shown in Fig. 3).
Fig. 8 A is the waveform that represents ramp signal RMP and pulse signal PLS.Pulse signal PLS in Fig. 8 A generates according to frequency signal CKA, as shown in Figure 6.
Fig. 8 B represents ramp signal RMP, pulse signal PLS, switching signal S
1and active strangulation signal S
2waveform.Initiatively strangulation signal S
2will be at switching signal S
1after forbidding, generate.Switching signal S
1will be at active strangulation signal S
2after forbidding, generate., switching signal S
1and active strangulation signal S
2generate and can not enable simultaneously in the mode of interlocking.Pulse signal PLS periodically generates, with switching signal S during intermittence switch mode
1situation about not being activated gets off to enable switching signal S
1.Pulse signal PLS in Fig. 8 B generates according to the signal of clicking being created in the output of impulse generator 300.In addition switching signal S,
1maximum turn-on time limited by the maximum cycle of ramp signal RMP.
Fig. 9 A represents according to one embodiment of the invention, the impulse generator 300 in oscillating circuit 130.Consult Fig. 9 A, current source 310 couples capacitor 325 is charged.322, transistor is for capacitor 325 is discharged.Signal S on the end points IN1 of impulse generator 300
iN1control transistor 322 by inverter 321.Signal S
iN1also be coupled to the input with door 329.Pass through inverter 327 coupling capacitance devices 325 with another input of door 329.Output pulse signal S on the end points OUT1 of impulse generator 300
oUT1pulse duration determined by the electric current of current source 310 and the capacitance of capacitor 325.In this embodiment, the signal S that the impulse generator 300 of Fig. 9 A receives
iN1output by inverter 157 (being shown in Fig. 6) is provided, and output pulse signal S
oUT1provide to or the input of door 165 (being shown in Fig. 6) using as clicking signal.
Fig. 9 B is the input signal S of indicating impulse maker 300
iN1and output pulse signal S
oUT1waveform.T
prepresent output pulse signal S
oUT1pulse duration.
Figure 10 A is the circuit framework figure that is illustrated in delay circuit 350 in signal generating circuit 200.Consult Figure 10 A, current source 360 couples capacitor 365 is charged.362, transistor is to couple capacitor 365 to discharge.Signal S on the end points IN2 of delay circuit 350
iN2control transistor 362 by inverter 361.Signal S
iN2also be coupled to the input with door 369.Coupling capacitance device 365 of another input with door 369.Output pulse signal S on the end points OUT2 of delay circuit 350
oUT2pulse duration determined by the electric current of current source 360 and the capacitance of capacitor 365.In this embodiment, the signal S that the delay circuit 350 of Figure 10 A receives
iN2output by inverter 271 (being shown in Fig. 7) is provided, and output pulse signal S
oUT2provide to trigger 290 (being shown in Fig. 7) to generate initiatively strangulation signal S
2.
Figure 10 B is the input signal S that represents delay circuit 350
iN2and output pulse signal S
oUT2waveform.T
brepresent the time of delay that delay circuit 350 generates.
Though the present invention with preferred embodiment openly as above; so it is not in order to limit scope of the present invention; without departing from the spirit and scope of the present invention, when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum for those skilled in the art.
Claims (12)
1. a control circuit, for active strangulation flyback power converter, comprising:
Low-pressure side transistor, is used for switching transformer;
High-pressure side transistor, with capacitor's series to form initiatively clamped circuit, wherein, described active clamped circuit and described transformers connected in parallel;
High-pressure side driving circuit, is used for driving described high-pressure side transistor; And
Controller, generates switching signal and active strangulation signal;
Wherein, described switching signal is used for driving described low-pressure side transistor, and described switching signal generates to regulate the output of described active strangulation flyback power converter according to feedback signal; And
Wherein, described active strangulation signal couples described high-pressure side driving circuit to control described high-pressure side transistor, and the pulse duration of described active strangulation signal is determined by the first resistor.
2. control circuit as claimed in claim 1, wherein, described active strangulation signal is enabled after described switch signal forbidden, and described switching signal can be enabled after described active strangulation signal disables.
3. the control circuit as described in claim the 1, wherein, under heavy duty state, the minimum frequency of described switching signal is determined by the second resistor.
4. control circuit as claimed in claim 1, wherein, described controller comprises:
Sluggish bias voltage maker, generates sluggish bias voltage to adjust described feedback signal; And
Comparator, has underload threshold value to control described sluggish bias voltage;
Wherein, described comparator is controlled described sluggish bias voltage according to value and the described underload threshold value of described feedback signal.
5. control circuit as claimed in claim 1, wherein, described switching signal will be enabled according to pulse signal, and described pulse signal is periodically generated by the oscillating circuit of described controller.
6. control circuit as claimed in claim 1, also comprises and fills pump circuit, wherein, described in fill pump circuit and comprise:
Diode, couples supply voltage; And
Fill pump capacitor, be one another in series with described diode;
Wherein, described in, fill pump capacitor and couple described high-pressure side driving circuit.
7. a control method, in order to control initiatively strangulation flyback power converter, comprising:
Generate switching signal according to feedback signal, to switch low-pressure side transistor and to regulate the output of described active strangulation flyback power converter; And
After described switch signal forbidden, generate initiatively strangulation signal;
Wherein, described low-pressure side transistor switching transformer, and described switching signal drives described low-pressure side transistor;
Wherein, described active strangulation signal is used for driving high-pressure side transistor, and the pulse duration of described active strangulation signal is determined by the first resistor; And
Wherein, described high-pressure side transistor AND gate capacitor's series is to form initiatively clamped circuit, and described active clamped circuit and described transformers connected in parallel.
8. control method as claimed in claim 7, wherein, described active strangulation signal is enabled after described switch signal forbidden, and described switching signal is enabled after described active strangulation signal disables.
9. the control method as described in claim the 7, wherein, under heavy duty state, the minimum frequency of described switching signal is determined by the second resistor.
10. control method as claimed in claim 7, also comprises:
Generate sluggish bias voltage to adjust described feedback signal;
Wherein, described sluggish bias voltage generates according to the value of described feedback signal and underload threshold value.
11. control methods as claimed in claim 7, also comprise:
Periodically production burst signal, to enable described switching signal.
12. control methods as claimed in claim 11, wherein, described pulse signal determines the maximum turn-on time of described switching signal.
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| CN201410299469.XA CN104022657B (en) | 2014-06-27 | 2014-06-27 | control circuit and control method |
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|---|---|---|---|
| CN201410299469.XA CN104022657B (en) | 2014-06-27 | 2014-06-27 | control circuit and control method |
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| CN104022657B CN104022657B (en) | 2016-09-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712472A (en) * | 2017-02-28 | 2017-05-24 | 华为技术有限公司 | Control method for ACF (Active Clamp Flyback) circuit and ACF circuit |
| CN109905031A (en) * | 2017-12-07 | 2019-06-18 | 硅谷实验室公司 | Isolated power transmitting device with integrated transformer and voltage controller |
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| CN103887986A (en) * | 2013-04-15 | 2014-06-25 | 崇贸科技股份有限公司 | Control Circuit Of Flyback Type Power Converter Time Predictive Control |
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| CN103825468A (en) * | 2013-02-18 | 2014-05-28 | 崇贸科技股份有限公司 | Control circuit of flyback power converter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106712472A (en) * | 2017-02-28 | 2017-05-24 | 华为技术有限公司 | Control method for ACF (Active Clamp Flyback) circuit and ACF circuit |
| CN109905031A (en) * | 2017-12-07 | 2019-06-18 | 硅谷实验室公司 | Isolated power transmitting device with integrated transformer and voltage controller |
| CN109905031B (en) * | 2017-12-07 | 2021-12-03 | 天工方案公司 | Isolated power transmission device with integrated transformer and voltage controller |
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| Publication number | Publication date |
|---|---|
| CN104022657B (en) | 2016-09-07 |
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