TWI523394B - Control circuits and control methods - Google Patents

Description

Control circuit and control method

The present invention relates to an active clamped flyback power converter, and more particularly to a control circuit for actively clamping a flyback power converter.

Existing active clamping circuits can only achieve zero voltage switching under specific load conditions. In addition, high circulating currents during light loads result in higher power loss issues. A related art can be found in U.S. Patent No. 5,570,278, entitled "Offset Resonance Zero Voltage Switching Flyback Converter", and U.S. Patent No. 6,069,803, and entitled "Active-clamp Circuit for Quasi", entitled "Clamped Continuous Flyback Power Converter". -resonant Flyback Power Converter Power Converter" is available in U.S. Patent Application Serial No. 20110305048.

Accordingly, the present invention provides a control circuit for actively clamping a flyback power converter. It achieves zero voltage switching under heavy load conditions and achieves high efficiency under light load conditions. It is an object of the present invention to provide a method and apparatus that ensures that an active clamped flyback power converter achieves zero voltage switching under heavy load conditions and achieves high efficiency under light load conditions.

The present invention provides a control circuit for actively clamping a flyback power converter. The control circuit includes a low-voltage side transistor, a high-voltage side transistor, and a high voltage Side drive circuit, controller and charge pump circuit. The low side transistor is used to switch the transformer. The high side transistor is connected in series with the capacitor to form an active clamp circuit. This active clamping circuit is connected in parallel with the transformer. The high side drive circuit is used to drive the high side transistor. The controller generates a switching signal as well as an active clamping signal. The switching signal is used to drive the low side transistor. The switching signal is generated based on the feedback signal to adjust the output of the active clamped flyback power converter. The active clamp signal is coupled to the high side drive circuit to control the high side transistor. The pulse width of the active clamp signal is determined by the first resistor. The active clamp signal is enabled after the switching signal is disabled. The switching signal can be enabled after the active clamp signal is disabled. In the heavy load state, the minimum frequency of the switching signal is determined by the second resistor. The control circuit includes a hysteresis bias generator and a capacitor. The hysteresis bias generator generates a hysteresis bias to adjust the feedback signal. The comparator has a light load threshold to control the hysteresis bias. The comparator controls the hysteresis bias based on the value of the feedback signal and the light load threshold. The switching signal will be enabled based on the pulse signal. This pulse signal is periodically generated by an oscillating circuit of the controller. The charge pump circuit includes a diode and a charge pump capacitor. The diode is coupled to the supply voltage. The charge pump capacitor and the diode are connected in series with each other. The charge pump capacitor is coupled to the high side drive circuit.

The present invention also provides a control method for controlling an active clamped flyback power converter. The control method includes the steps of: generating a switching signal according to the feedback signal to switch the low-voltage side transistor and adjusting an output of the active clamp-down power converter; and generating an active clamping signal after the switching signal is disabled. Low-voltage side transistor switching transformer. The switching signal drives the low side transistor. The active clamp signal is used to drive the high side transistor. The pulse width of the active clamp signal is determined by the first resistor. The high side transistor is connected in series with the capacitor to form an active clamp circuit. This active clamping circuit is connected in parallel with the transformer. Active clamping signal after the switching signal is disabled Enable. The switching signal is enabled after the active clamp signal is disabled. In the heavy load state, the minimum frequency of the switching signal is determined by the second resistor. The control method further includes the step of generating a hysteresis bias to adjust the feedback signal. The hysteresis bias is generated based on the value of the feedback signal and the light load threshold. The control method further includes the step of periodically generating a pulse wave signal to enable switching of the signal. This pulse signal determines the maximum on-time of the switching signal.

Figure 1:

10‧‧‧Transformers

11‧‧‧Leakage inductance

15‧‧‧ capacitor

20‧‧‧Optoelectronics (low voltage side transistor)

25‧‧‧ Body diode

30‧‧‧Optotrans (high-voltage side transistor)

35‧‧‧ Body diode

40‧‧‧ capacitor

43‧‧‧Rectifier

45‧‧‧ capacitor

50‧‧‧High-voltage side drive circuit

65‧‧‧ capacitor

60‧‧‧Rectifier

70‧‧‧ diode

75‧‧‧ capacitor

81‧‧‧First resistor

82‧‧‧second resistor

90‧‧‧Optocoupler

93‧‧‧Resistors

95‧‧‧Voltage regulator

100‧‧‧ Controller

N _A ‧‧‧Auxiliary coil

N _P ‧‧‧ primary side coil

N _S ‧‧‧ secondary coil

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

V _CC ‧‧‧ supply voltage

V _FB ‧‧‧Response signal

V _IN ‧‧‧ input voltage

V _O ‧‧‧Output voltage

Figure 2A-2D:

10‧‧‧Transformers

11‧‧‧Leakage inductance

15‧‧‧ capacitor

20‧‧‧Optoelectronics (low voltage side transistor)

25‧‧‧ Body diode

28‧‧‧Parasitic capacitors

30‧‧‧Optotrans (high-voltage side transistor)

35‧‧‧ Body diode

38‧‧‧Parasitic capacitors

40‧‧‧ capacitor

43‧‧‧Rectifier

45‧‧‧ capacitor

I _CR ‧‧‧Circulating current

I _DS , I _P , I _S ‧‧‧ current

N _P ‧‧‧ primary side coil

N _S ‧‧‧ secondary coil

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

T ₁ ... T ₄ ‧‧‧ state

V _IN ‧‧‧ input voltage

V _O ‧‧‧Output voltage

Figure 3:

I _CR ‧‧‧Circulating current

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

Period of T _CH ‧‧‧State T ₂

Maximum period of T _DS ‧‧‧state T ₃

Pulse width of T _S1 ‧‧‧ switching signal S ₁

Pulse width of T _S2 ‧‧‧ active clamp signal S ₂

Figure 4:

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

T _BT ‧‧‧ Intermittent period

Figure 5:

100‧‧‧ Controller

110‧‧‧ comparator

111‧‧‧Factor

112‧‧‧ and gate

113‧‧‧Inverter

115‧‧‧ and gate

117‧‧‧current source

118‧‧‧ switch

119‧‧‧ comparator

120‧‧‧bit shifting transistor

125, 126‧‧‧ resistors

130‧‧‧Oscillation circuit

200‧‧‧Signal generation circuit

CLR‧‧‧clear signal

PLS‧‧‧ pulse signal

RMP‧‧‧ ramp signal

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

V _B ‧‧‧ signal

V _CC ‧‧‧ supply voltage

V _FB ‧‧‧Response signal

V _TL ‧‧‧ light load threshold

Figure 6:

127‧‧‧ capacitor

128‧‧‧ switch

130‧‧‧Oscillation circuit

131‧‧‧current source

132‧‧‧ switch

135‧‧‧current source

136‧‧‧ switch

141, 142, 145‧‧‧ comparator

146, 151, 152‧‧‧ anti-gate

156‧‧‧Inverter

157‧‧‧Inverter

165‧‧‧ or gate

300‧‧‧ Pulse Generator

CKA, CKB‧‧‧ frequency signals

CLR‧‧‧clear signal

PLS‧‧‧ pulse signal

RMP‧‧‧ ramp signal

S ₂ ‧‧‧Active clamp signal

S _IN1 ‧‧‧ signal

S _OUT1 ‧‧‧ output pulse signal

V _H , V _L ‧‧‧ jumping point voltage

V _M ‧‧‧threshold voltage

Figure 7:

200‧‧‧Signal generation circuit

270‧‧‧ Comparator

271‧‧‧Inverter

280‧‧‧current source

281‧‧‧ switch

285‧‧‧ capacitor

290‧‧‧Factor

350‧‧‧ Delay Circuit

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

S _IN2 ‧‧‧ signal

S _OUT2 ‧‧‧ Output pulse signal

V _W ‧‧‧ threshold

Figure 8A-8B

PLS‧‧‧ pulse signal

RMP‧‧‧ ramp signal

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

V _H , V _L ‧‧‧ jumping point voltage

V _M ‧‧‧threshold voltage

Figure 9A-9B:

300‧‧‧ Pulse Generator

310‧‧‧current source

321‧‧‧Inverter

322‧‧‧Optoelectronics

325‧‧‧ capacitor

327‧‧‧Inverter

329‧‧‧ and gate

S _IN1 ‧‧‧ signal

S _OUT1 ‧‧‧ output pulse signal

Pulse width of T _P ‧‧‧ output pulse signal S _OUT1

Figure 10A-10B:

350‧‧‧ Delay Circuit

361‧‧‧Inverter

362‧‧‧Optoelectronics

360‧‧‧current source

365‧‧‧ capacitor

369‧‧‧ and gate

S _IN2 ‧‧‧ signal

S _OUT2 ‧‧‧ Output pulse signal

T _B ‧‧‧ delay time of the delay circuit 350 generates a

Figure 1 shows a flyback power converter in accordance with an embodiment of the present invention.

2A-2D are diagrams showing four states of current of a power converter, respectively, in accordance with an embodiment of the present invention.

Figure 3 shows the waveforms of the switching signal, the active clamp signal, and the circulating current.

Figure 4 shows the intermittent waveform of the switching signal and the active clamping signal.

Figure 5 shows a controller in a power converter in accordance with an embodiment of the present invention.

Figure 6 shows an oscillating circuit in a controller in accordance with an embodiment of the present invention.

Figure 7 shows a signal generating circuit in a controller in accordance with an embodiment of the present invention.

Fig. 8A shows the waveforms of the ramp signal and the pulse wave signal.

Fig. 8B shows the waveforms of the ramp signal, the pulse wave signal, the switching signal, and the active clamp signal.

Fig. 9A is a diagram showing the circuit configuration of a pulse wave generator in an oscillation circuit according to an embodiment of the present invention.

Figure 9B shows the input signal and output signal of the pulse generator in Figure 9A. The waveform of the number.

Fig. 10A is a diagram showing the circuit configuration of a delay circuit in a signal generating circuit according to an embodiment of the present invention.

Fig. 10B is a diagram showing the waveforms of the input signal and the output signal of the delay circuit in Fig. 10A.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 1 is a diagram showing a flyback power converter in accordance with an embodiment of the present invention. Transformer 10 receives the input voltage V _{IN of the} power converter. A transistor (also referred to as a "low voltage side transistor") 20 is coupled to switch the primary side coil N _{P of the} transformer 10. The controller 100 generates a switching signal S ₁ at its end point S1, and the switching signal S ₁ is used to drive the transistor 20 to adjust the output voltage V _{O of the} power converter. The switching signal S ₁ is generated in accordance with the feedback signal V _FB at the terminal FB of the controller 100. The feedback signal V _{FB is} associated with the output voltage V _{O of the} power converter. The secondary side coil N _{S of the} transformer 10 will pass through the rectifier 43 and the capacitor 45 to generate an output voltage V _O . Resistor 93, voltage regulator 95 (kina diode) and optocoupler 90 form a feedback circuit for generating feedback signal V _FB in accordance with output voltage V _O . Transformer 20 includes an auxiliary winding N _A that passes through rectifier 60 to produce a supply voltage V _CC across capacitor 65. The supply voltage V _CC is used to supply power to the controller 100. A transistor (also referred to as "high voltage side transistor") 30 in series with capacitor 15 has formed an active clamping circuit. This active clamp circuit and the primary side coil N _{P of the} transformer 10 are connected in parallel with each other. When the transistor 20 is turned off, the energy of the leakage inductance 11 of the transformer 10 is stored in the capacitor 15 through the transistor 30 and its body diode 35. The high side drive circuit 50 is used to drive the transistor 30. The charge pump circuit composed of the diode 70 and the capacitor 75 receives the supply voltage V _CC and supplies power to the high side drive circuit 50. The capacitor 75 and the diode 70 are connected in series to each other. In the embodiment of Fig. 1, the transistor 20, the controller 100, the high side drive circuit 50, the active clamp circuit, and the charge pump circuit form a control circuit.

The controller 100 generates an active clamp signal S ₂ at its end point S2 to control the high side drive circuit 50. The pulse width of the active clamp signal S ₂ is determined by the resistance value of the first resistor 81. The first resistor 81 is coupled to the terminal RT of the controller 100. The active clamp signal S _{2 is} only enabled when the switching signal S _{1 is} disabled. During the heavy load condition, the switching signal S ₁ will be enabled after the active clamp signal S _{2 is} disabled. The second resistor 82 is coupled to the terminal RM of the controller 100 to determine the minimum frequency (maximum on-time) of the switching signal S ₁ under heavy load conditions.

2A-2D are diagrams showing four states of current of a power converter, respectively, in accordance with an embodiment of the present invention. Refer to FIG. 2A, in the state T _1, switching signals S ₁ is turned on (ON) transistor 20. Current I _P flows through transformer 10 and stores energy to transformer 10. This energy will also be stored to the leakage inductance 11 of the transformer 10.

See Figure 2B, in the state T _2, the switching signals S ₁ is turned off (OFF) transistor 20. The energy stored in the output transformer 10 by current I _S will be transmitted to the power converter to generate an output voltage V _O. In addition, the energy stored in the transformer 10 and the leakage inductance 11 is transmitted to the capacitor 15 through the body diode 35 of the transistor 30. The circulating current I _CR represents the energy flowing into the capacitor 15. after this. The active clamping signal S ₂ will conduct the crystal 30.

Refer first to FIG 2C, in the state T _3, the energy stored in the capacitor 15 through transistor 30 will be 10 and the leakage inductance of the transformer 11 for reuse. The capacitor 15 is discharged by circulating the current I _CR and passing through the leakage inductance 11. The leakage inductance 11 and the capacitor 15 form a resonant tank and determine its resonant frequency.

See FIG. 2D, at state T _4, the clamping signal S ₂ active transistor 30 is turned off. The energy stored in the leakage inductance 11 will be transferred to the input voltage V _IN by the current I _DS . In the meantime, the parasitic capacitor 28 of the transistor 20 will be discharged and the transistor 20 of the body diode 25 may be turned on to the next switching cycle to achieve zero-voltage transistor 20 of the switching operation (state T _1).

Fig. 3 shows waveforms of the switching signal S ₁ , the active clamp signal S _{2 ,} and the circulating current I _CR . The period T _CH indicates the period of the state T ₂ . The period T _DS indicates the maximum period of the state T ₃ . T _S1 represents the pulse width of the switching signal S ₁ . T _S2 represents the pulse width of the active clamp signal S ₂ . For the initial state T ₃ (period T _DS ), the active clamp signal S ₂ must be enabled before the end of the period T _CH . In order to complete the zero voltage switching, the active clamp signal S ₂ must be disabled before the end of the period T _DS . The period T _CH and the period T _DS are both determined by the resonant frequency of the resonant tank.

Fig. 4 shows a burst waveform of the switching signal S ₁ and the active clamp signal S ₂ . The period T _BT is a burst period.

Figure 5 is a diagram showing a controller 100 in a power converter in accordance with an embodiment of the present invention. The controller 100 includes an oscillating circuit 130 that generates a pulse signal PLS, a ramp signal RMP, and a clear signal CLR. The pulse signal PLS passes through the inverter 113, the flip-flop 111, and the AND gate 115 to enable the switching signal S ₁ . The active clamp signal S ₂ and the second resistor 82 (shown in Figure 1) are coupled to the oscillating circuit 130 for generating the switching signal S ₁ . Therefore, once the active clamp signal S _{2 is} disabled, the switching signal S ₁ is enabled. The second resistor 82 determines the minimum switching frequency of the switching signal S ₁ (lowest switching frequency). A first resistor 81 (shown in FIG. 1) and a switching signal S _{1 are} coupled to the signal generating circuit 200 to generate an active clamp signal S ₂ . Once the switching signal S _{1 is} disabled, the active clamping signal S ₂ is enabled. The level shifting transistor 120 and the resistors 125 and 126 generate a signal V _{B in} response to the feedback signal V _FB . The ramp signal RMP is compared with the signal V _B in the comparator 110 to pass through the AND gate 112 to generate a signal for disabling the switching signal S ₁ , thereby implementing a pulse width modulation operation. The clear signal CLR generated by the oscillating circuit 130 is used to reset the flip flop 111 to disable the switching signal S ₁ and limit the maximum on time of the switching signal S ₁ .

Comparator 119 is used to compare signal V _B with light load threshold V _TL . When the signal V _{B is} below the light load threshold V _TL , the hysteresis bias will begin to decrease from the current level of the signal V _B . The hysteresis bias generator including resistors 125 and 126 and current source 117 produces the hysteresis voltage described above, which is determined by the magnitude of current source 117 and the equivalent resistance of resistors 125 and 126. The switch 118 controlled by the comparator 119 turns on/off the current source 117. When the signal V _{B is} above the light load threshold V _TL , the hysteresis bias will be added to the signal V _B . When the signal V _{B is} below the light load threshold V _TL , the hysteresis bias begins to decrease from the current level of the signal V _B . Therefore, through this feedback loop, the hysteresis bias will cause intermittent switching to reduce the switching frequency of the switching signal S ₁ and improve the light load performance under light load conditions (signal V _{B is} lower than the light load threshold V _TL ).

Figure 6 shows an oscillating circuit 130 in the controller 100 in accordance with an embodiment of the present invention. Current sources 131 and 135 pass through switches 132 and 136, respectively, to charge and discharge capacitor 127. The ramp signal RMP is generated across the capacitor 127. The ramp signal RMP is further coupled to comparators 141, 142, and 145. The comparator 141 has a trip-point voltage V _H . The comparator 142 has a trip point voltage V _L . The comparator 145 has a threshold voltage V _M . The level of the trip point voltage V _H is greater than the level of the threshold voltage V _M . The bit criterion of the threshold voltage V _M is greater than the level of the trip point voltage V _L . The anti-gates 151 and 152 form a latch circuit that receives the output signals of the comparators 141 and 142. This latch circuit and inverter 156 generate frequency signals CKA and CKB. The frequency signal CKA is used to control the switch 136 to discharge the capacitor 127. The frequency signal CKB is used to control the switch 132 to charge the capacitor 127. The output of comparator 145 and frequency signal CKA are passed through inverse gate 146 to produce a clear signal CLR. Active clamping signal S ₂ of the falling edge 300 generates a click signal input terminal of OR gate 165 through inverter 157 and pulse generator. The other input of the OR gate 165 receives the frequency signal CKA. Both the click signal and the frequency signal CKA pass through the OR gate 165 to generate the pulse signal PLS. Therefore, the pulse signal PLS will be generated each time the active clamp signal S _{2 is} disabled. Furthermore, when the maximum oscillation period of the ramp signal RMP is reached, the pulse signal PLS will be generated in accordance with the frequency signal CKA. Since the clear signal CLR signal CKA accordance with the frequency (CKA and the clock signal associated with the pulse wave signal PLS) generated, the pulse signal PLS thus limiting the switching signal S ₁ of the maximum on time. The resistance value of the second resistor 82 (shown in FIG. 1) connected to the terminal RM controls the magnitude of the current source 131. Therefore, the second resistor 82 is used to determine the maximum oscillation period of the ramp signal RMP.

Figure 7 is a diagram showing a signal generating circuit 200 in the controller 100 in accordance with an embodiment of the present invention. The switching signal S ₁ is generated by the inverter 271, the delay circuit 350, and the flip-flop 290 to generate the active clamp signal S ₂ . Thus, when the switching signals S ₁ disabled, active clamping signal S ₂ will be enabled after a delay time determined by delay circuit 350. Once the switching signal S _{1 is} disabled, the switch 281 will be turned off. Current source 280 will begin to charge capacitor 285. When the voltage across the capacitor 285 is higher than the threshold value V _W, the comparator 270 through the flip-flop 290 to disable the active clamping signal S _2. The resistance value of the first resistor 81 (shown in FIG. 1) coupled to the terminal RT controls the magnitude of the current source 280. Therefore, the first resistor 81, the capacitor 285, and the threshold V _W determine the pulse width of the active clamp signal S ₂ . The first resistor 81 is implemented to determine the pulse width T _{S2 of the} active clamp signal S ₂ to achieve zero voltage switching. Pulse width T _S2 must meet the following conditions: T _S2> T _CH and _{T S2 <"T CH + T} DS" ( shown in FIG. 3).

Fig. 8A shows waveforms of the ramp signal RMP and the pulse wave signal PLS. The pulse wave signal PLS in Fig. 8A is generated based on the frequency signal CKA as shown in Fig. 6.

Figure 8B are diagrams of the ramp signal RMP, the pulse signal PLS, and a waveform switching signals S ₁ to active clamping signal S _2. The active clamp signal S ₂ will be generated after the switching signal S _{1 is} disabled. The switching signal S ₁ will be generated after the active clamping signal S _{2 is} disabled. That is, the switching signal S ₁ and the active clamping signal S ₂ are generated in an interleaved manner without being simultaneously enabled. The pulse signal PLS is periodically generated to enable the switching signal S ₁ in the case where the switching signal S _{1 is} not enabled during the intermittent switching mode. The pulse wave signal PLS in Fig. 8B is generated in accordance with a click signal generated on the output of the pulse wave generator 300. Furthermore, the maximum on-time of the switching signal S ₁ is limited by the maximum period of the ramp signal RMP.

Figure 9A shows a pulse generator 300 within an oscillating circuit 130, in accordance with an embodiment of the present invention. Referring to Figure 9A, current source 310 is coupled to charge capacitor 325. The transistor 322 is used to discharge the capacitor 325. The signal S _IN1 at the end point IN1 of the pulse generator 300 is passed through the inverter 321 to control the transistor 322. Signal S _{IN1 is} further coupled to the input of AND gate 329. The other input of the AND gate 329 is coupled to the capacitor 325 via an inverter 327. The pulse width of the output pulse signal S _OUT1 at the end point OUT1 of the pulse generator 300 is determined by the current of the current source 310 and the capacitance of the capacitor 325. In this embodiment, the signal S _IN1 received by the pulse generator 300 of FIG. 9A is provided by the output of the inverter 157 (shown in FIG. 6), and the output pulse signal S _OUT1 is supplied to Or the input of gate 165 (shown in Figure 6) as a click signal.

FIG 9B shows a waveform of the input pulse train generator 300 of the signal S _IN1 and the output of the pulse signal S _OUT1. T _P represents the pulse width of the output pulse wave signal S _OUT1 .

Fig. 10A is a circuit diagram showing the delay circuit 350 in the signal generating circuit 200. Referring to FIG. 10A, current source 360 is coupled to charge capacitor 365. The transistor 362 is coupled to discharge the capacitor 365. Signal S _IN2 at terminal IN2 of delay circuit 350 is passed through inverter 361 to control transistor 362. Signal S _{IN2 is} further coupled to the input of AND gate 369. The other input of the AND gate 369 is coupled to the capacitor 365. The pulse width of the output pulse signal S _OUT2 at the terminal OUT2 of the delay circuit 350 is determined by the current of the current source 360 and the capacitance of the capacitor 365. In this embodiment, the signal S _IN2 received by the delay circuit 350 of FIG. 10A is provided by the output of the inverter 271 (shown in FIG. 7), and the output pulse signal S _OUT2 is supplied to the front and back. A 290 (shown in Figure 7) is used to generate the active clamp signal S ₂ .

FIG 10B shows a waveform based on the input signal S _IN2 of the delay circuit 350 and the output _{OUT2 of the} pulse signal S is. T _B represents the delay time generating circuit 350.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

100‧‧‧ Controller

110‧‧‧ comparator

111‧‧‧Factor

112‧‧‧ and gate

113‧‧‧Inverter

115‧‧‧ and gate

117‧‧‧current source

118‧‧‧ switch

119‧‧‧ comparator

120‧‧‧bit shifting transistor

125, 126‧‧‧ resistors

130‧‧‧Oscillation circuit

200‧‧‧Signal generation circuit

CLR‧‧‧clear signal

PLS‧‧‧ pulse signal

RMP‧‧‧ ramp signal

S ₁ ‧‧‧Switching signal

S ₂ ‧‧‧Active clamp signal

V _B ‧‧‧ signal

V _CC ‧‧‧ supply voltage

V _FB ‧‧‧Response signal

V _TL ‧‧‧ load threshold

Claims (12)

A control circuit for an active clamped flyback power converter includes: a low voltage side transistor for switching a transformer; a high side transistor, connected in series with a capacitor to form an active clamp circuit, wherein An active clamping circuit is connected in parallel with the transformer; a high voltage side driving circuit for driving the high voltage side transistor; and a controller for generating a switching signal and an active clamping signal; wherein the switching signal is used to drive the low voltage side current a crystal, and the switching signal is generated according to a feedback signal to adjust an output of the active clamped flyback power converter; and wherein the active clamp signal is coupled to the high side driver circuit to control the high side transistor And a pulse width of the active clamp signal is determined by a first resistor. The control circuit of claim 1, wherein the active clamp signal is enabled after the switching signal is disabled, and the switching signal is enabled after the active clamp signal is disabled. The control circuit of claim 1, wherein a minimum frequency of the switching signal is determined by a second resistor under a heavy load condition. The control circuit of claim 1, wherein the controller comprises: a hysteresis bias generator that generates a hysteresis bias to adjust the feedback signal; A comparator having a light load threshold to control the hysteresis bias; wherein the comparator controls the hysteresis bias based on the value of the feedback signal and the light load threshold. The control circuit of claim 1, wherein the switching signal is enabled according to a pulse signal, and the pulse signal is periodically generated by an oscillation circuit of the controller. The control circuit of claim 1, further comprising a charge pump circuit, wherein the charge pump circuit comprises: a diode coupled to a supply voltage; and a charge pump capacitor, and the diode Connected to each other in series; wherein the charge pump capacitor is coupled to the high side drive circuit. A control method for controlling an active clamped flyback power converter includes: generating a switching signal according to a feedback signal to switch a low voltage side transistor and adjusting an output of the active clamped flyback power converter And generating an active clamping signal after the switching signal is disabled; wherein the low-voltage side transistor switches a transformer, and the switching signal drives the low-voltage side transistor; wherein the active clamping signal is used to drive a high-voltage side a transistor, and a pulse width of the active clamp signal is determined by a first resistor; and wherein the high side transistor is connected in series with a capacitor to form an active clamp circuit, and the active clamp circuit is connected in parallel with the transformer . The control method of claim 7, wherein the active clamp signal is enabled after the switching signal is disabled, and the switching signal is enabled after the active clamp signal is disabled. The control method of claim 7, wherein a minimum frequency of the switching signal is determined by a second resistor under a heavy load condition. The control method of claim 7, further comprising: generating a hysteresis bias to adjust the feedback signal; wherein the hysteresis bias is generated according to the value of the feedback signal and a light load threshold . The control method of claim 7, further comprising: periodically generating a pulse wave signal to enable the switching signal. The control method of claim 11, wherein the pulse wave signal determines a maximum on time of the switching signal.