CN104021257A - Design method for setting 10-degree wiring of high-speed signals on single PCB (Printed Circuit Board) - Google Patents
Design method for setting 10-degree wiring of high-speed signals on single PCB (Printed Circuit Board) Download PDFInfo
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- CN104021257A CN104021257A CN201410284771.8A CN201410284771A CN104021257A CN 104021257 A CN104021257 A CN 104021257A CN 201410284771 A CN201410284771 A CN 201410284771A CN 104021257 A CN104021257 A CN 104021257A
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Abstract
The invention discloses a design method for setting 10-degree wiring of high-speed signals on a single PCB (Printed Circuit Board). A design program for setting 10-degree wiring of the high-speed signals on the single PCB is developed by use of CADENCE AXLSKILL language; during specific operations, the SKILL program is put in a wiring tool installation document; once the SKILL program is executed, a prompting dialog box is popped up; the length of each section of 10-degree wiring is input according to the dialog, and then CLine needing to be designed into 10-degree wiring is selected, and therefore, the design of 10-degree wiring can be completed. Due to the adopted design method, the design of 10-degree wiring of high-speed signals can be realized very simply, either board or PCB design space is saved, and meanwhile, the transmission losses of high-speed signals in the board due to weaving effect are also effectively inhibited; the operating method of the design tool is also very simple and convenient.
Description
Technical field
The present invention relates to electronic applications, relate to single board design and making, use CADENCE ALLEGRO wiring design software and CADENCE AXLSKILL development language to design.
Technical background
At present, the transfer rate of signal is more and more higher, and the dielectric loss of PCB veneer has become a very important factor of restrictive signal transmission.Because the existence of the weave effect of medium, the level that we are traditional or vertical cabling mode are not identical in the loss of same position.
Because the uniform material of PCB non-isotropy, because sheet material is formed by glass fibre and epoxy resin braiding, all has space between glass fibre and epoxy resin in every kind of sheet material.If high-speed-differential cabling is not in the situation that walking 10 °, the loss between PN has a great difference.The specific inductive capacity of glass and resin is different, in the time of difference cabling, two lines may by chance be walked on the inconsistent position of specific inductive capacity, cause common-mode rejection ratio to decline, by after the fiberglass mesh inclination certain angle in cabling and PCB, the change in dielectric constant that two lines run into is above tending towards on average, and a small amount of unbalanced area is also limited in a few glass grid, and adjacent area polarity is contrary, cancels each other.
And if be parallel to grid, may long-term 1 line pressure on glass, another single line is on resin, whole loop area is all asymmetric.
The design of 10 ° of cablings is can well solve because the problem of the loss that medium weave effect brings.But regrettably,, the wiring design software that just we use at present, all cannot design the cabling of 10 ° easily.But along with the miniaturization of electronic product and the development trend of multifunction, the design density of PCB is more and more higher, this just requires our maximum using PCB space in the process of Design PCB, the arbitrarily angled cabling that wiring software is designed very inconvenient adjustment in the situation that of this limited space, not attractive in appearance yet.So we need a kind of loss that weave effect that line design method suppresses PCB veneer medium brings of walking that be convenient to be adjusted to 10 ° of cablings and can improve again PCB space availability ratio.
Being directed to us and using at present CADENCE ALLEGRO wiring design software, is the design that is difficult to realize 10 ° of cablings.Can only design the weave effect that cabling at any angle suppresses medium, but this cabling mode and design space not attractive in appearance and waste cabling are unfavorable for the design of pcb board very much.
Summary of the invention
The technical problem to be solved in the present invention is: the method for designing that 10 ° of cablings of high speed signal on a kind of PCB of setting veneer are provided.
The technical solution adopted in the present invention is:
A kind of method for designing that 10 ° of cablings of high speed signal on PCB veneer are set, by designing program of 10 ° of cablings of high speed signal on a kind of PCB of setting veneer of use CADENCE AXLSKILL language development, when concrete operations, this Skill formula is put in wiring tool installation file, carrying out this SKILL formula will prompted dialog frame, according to the length of every section of 10 ° of cablings of dialog box input, then frame selects the design that needs to be designed to the CLine of 10 ° of cablings and can complete 10 ° of cablings.
The concrete operation step of described method for designing is: first completing after cabling by traditional mode; Carry out described Skill program; Then frame selects the relevant Cline that needs to be designed to 10 ° of cablings; And input every section and be coiled into the length (this length according to whole cabling decides, and can freely fill in) of 10 °, program will complete automatically according to the step in process flow diagram the design of 10 ° of cablings.
Described Skill program design is as follows:
axlCmdRegister(″ tune″ ′tune)
procedure(tune(0;set main function
(defun axlMyCancel ()
axlClearDynamics()
axlCancelEnterFun()
axlUIPopupSet(nil))
(defun axlMyDone ()
axlClearDynamics()
axlFinishEnterFun()
axlUIPopupSet(nil))
mypopup = axlUIPopupDefine (nil (list (list″MyCancel″ ′axlMyCancel) (list ″MyDone″ ′axlMyDone)))
axlUIPopupSet( mypopup)
axlSetFindFilter( enabled list (″noall″ ″clinesegs″) onButtons list (″noall″ ″clinesegs″))
axlClearSelSet(); set done and cancle command
while(axlSingleSelectBox()
desing=axlGetSelSet()
length=length(design)
;design_dbid1=car(axlGetSelSet())
design_dbid1=nth(0 design)
layer=design_dbid1-> layer
startEnd1=design_dbid1-> startEnd
a=nth(0 startEnd1)
b=nth(1 startEnd1)
xa=nth(0 a)
ya=nth(1 a)
xb=nth(0 b)
yb=nth(1 b)
xminmax=min(xa xb);left
xmaxmin=max(xa xb);right
yminup=max(ya yb);up
ymaxdown=min(ya yb);down
lineType=design_dbid1->lineType
; get need to route cline
case(lineType
;;the below is cline is horizontal
(horizontal
ylist=′()
allylist=′()
for ( 1 1 length
mel_db=nth(1-1 design)
staEnd=mei_db->width
ma=nth(0 staEnd)
mb=nth(1 staEnd)
mxa=nth(0 ma)
mxb=nth(0 mb)
mxleft=min(mxa mxb)
mxright=max(mxa mxb)
xminmax=max(mxleft xminmax)
xmaxmin=min(mxright xmaxmin)
my=nth(1 ma)
ylist=cons(width ylist)
ylist=cons(mxright ylist)
ylist=cons(mxleft ylist)
ylist=cons(my ylist)
allylist=cons(ylist allylist)
) ; end for
;get all need to route 10 degree information
paixudy=sortcar(allylist ′greaterp)
d=abs(xmaxmin-xminmax)-50
add_x=atof(axlUIPrompt(″please enter addx_distance″ ″125″))
m=(floor d/(2*add_x)) ;route how much cycle
firstx=nth(1 nth(0 paixudy));get max y coordinate clines x information
axlDeleteObject(design)
if (firstx==xminmax
then
rout=nth(0 paixudy)
qishiy=nth(0 rout)
qishix=nth(1 rout)
zhongx=nth(2 rout)
width=nth(3 rout)
xcank=xminmax+20
xo=xcank
wy1=qishiy-(add_x /5)
wy2=qishiy
path=axlPathStart(list(qishix:qishiy) width)
;axlDBCreateLine(list(qishix:qishiy x0:qishiy) width layer)
axlPathLine( path, width, x0:qishiy)
for(k 1 m
wx1=x0+add_x
wx2=wx1+add_x
;path+axlPathStart(list(xO:qishiy) width)
;axlDBCreateLine(list(x0:qishiy wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:xy1 wx2:wy2) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
xO=wx2
) ; for
; path=axlPathStart(list(wx2:wy2) width)
;axlDBCreateLine(list(wx2:wy2 zhongx:xy2) width layer)
axlPathLine( path,width, zhongx:xy2)
axlDBCreatePath( path,layer)
lasty1=wy1
lasty2=wy2
;xO=xminmax+5
xlast=wx2
for(q 1 length-1
if((m==1) then
rout=nth(g paixudy)
chushiy=nth(0 rout)
chushix=nth(1 rout)
zhongx=nth(2 rout)
width=nth(3 rout)
spac=abs(qishiy-chushiy)
xcank=xcank-(sqrt(26)-5)*spac-0.01
xO=xcank
xmm=xminmax+20
wx1=xmm+add_x
wx2=wx1+add_x
dyt=sqrt(26)*space/5+0.002
wy1=lasty1-dty
wy2=lasty2-dty
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, xO:chushiy)
for(1 1 length
mei_db=nth(1-1 design)
staEnd=mei_db->startEnd
width=mei_db->width
ma=nth(0 staEnd)
mb=nth(1 staEnd)
mya=nth(1 ma)
myb=nth(1 mb)
myup=max(mya myb)
mydown=min(mya myb)
yminup=min(myup yminup);qu up min
ymaxdown=max(mydown ymaxdown);qu down max
mx=nth(0 ma)
ylist=cons(width ylist)
ylist=cons(mydown ylist)
ylist=cons(myup ylist)
ylist=cons(mx ylist)
allylist=cons(ylist allylist)
);for
paixudy=sortcar(allylist ′greaterp)
d=abs(yminup-ymaxdown)-50
;mm=(floor d/add_x)
;m=(floor mm/2)
add_x=atof(axlUIPrompt(″plesae enter addx_distance″″125″))
m=(floor d/(2*add_x))
firsty=nth(1 nth(0 paixudy))
axlDeleteObject(design)
if((firsty==yminup)
then
a=1
rout=nth(0 paixudy)
qishix=nth(0 rout)
qishiy=nth(1 rout)
zhongy=nth(2 rout)
width=nth(3 rout)
ycank=yminup-10
yO=ycank
wx1=qishix-(add_x /5)
wx2=qishix
path=axlPathStart(list(qishix:qishiy) width)
axlPathLine( path,width, qishix:y0)
for(k 1 m
wy1=y0-add_x
wy2=wy1-add_x
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
y0=wy2
);for
axlPathLine( path, width, wx2:zhongy)
axlDBCreatePath( path, layer)
lastx1=wx1
lastx2=wx2
ylast=wy2
for(q 1 length-1
if ((m==1) then
rout=nth(q paixudy)
chushix=nth(0 rout)
chushiy=nth(1 rout)
zhongy=nth(2 rout)
width=nth(3 rout)
spac=abs(qishix-chushix)
ycank=ycank+(sqrt(26)-5)*spac+0.01
y0=ycank
ymm=yminup-10
wy1=ymm-add_x
wy2=wy1-add_x
dtx=sqrt(26)*spac/5+0.002
wx1=lastx1-dtx
wx2=lastx2-dtx
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, chushix:y0)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, chushix:(ylast-(sqrt926)-5*space-0.01)))
axlPathLine( path, width, chushix:zhongy)
axlDBCreatePath( path, layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
dtx=sqrt(26)*spac/5+0.002
wx1=lastx1-dtx
wx2=lastx2-dtx
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, chushix:y0)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
y0=wy2
for(k 1 m-2
wy1=y0-add_x
wy2=wy1-add_x
; path=axlPathStart(list(wx2:y0) width)
;axlDBCreateLine(list (wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 wx2:wy2) width layer)
axlPathLine( path, width, wx1:xy1)
axlPathLine( path, width, wx2:xy2)
y0=wy2
);for
wy1=y0-add_x
wy2=ylast-(sqrt(26)-5)*spac-0.01
; path=axlPathStart(list(wx2:y0) width
;axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
; axlDBCreateLine(list(wx1:wy1 chushix:wy2) width layer)
;axlDBCreateLine(list(chushix:wy2 chushix:zhongy) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine(path, width,chushix:xy2)
axlPathLine(path, width,chushix:zhongy)
axlDBCreatePath(path, layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
ylast=wy2
);if
);for length-1
; path=axlPathStart(list(wx2:y0) width)
; axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 wx2:wy2) width layer)
axlPathLine( path,width,wx1:wy1)
axlPathLine( path,width,wx2:wy2)
y0=wy2
) ; for
wy1=y0-add_x
wy2=ylast-(sqrt(26)-5)*spac-0.01
; path=axlPathStart(list(wx2:y0 ) width)
; axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 chushix:wy2) width layer)
;axlDBCreateLine(list(chushix:wy2 chushix:zhongy) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, chushix:xy2)
axlPathLine( path, width, chushix:zhongy)
axlDBCreatePath( path,layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
ylast=wy2
);if m=1
);for
);if
);vertical
);case
);while
)
Beneficial effect of the present invention is: adopt method for designing of the present invention, can very simply realize the design of 10 ° of cablings of high speed signal, sheet material and PCB design space are not only saved, also effectively suppress the loss that because of weave effect cause of high speed signal in sheet material, also very easy of the method for operating of this design tool simultaneously.
Brief description of the drawings
Fig. 1 is the method for the invention process flow diagram.
Embodiment
With reference to the accompanying drawings, by embodiment, the present invention is further described:
After the cabling of the mode that wiring installation Shi Xianyong is traditional completes, carry out this design tool, then wiring installation's teacher frame selects the relevant Cline that needs to be designed to 10 ° of cablings, and input every section and be coiled into the length of 10 ° (this length according to whole cabling decides, can freely fill in), program will complete automatically according to the step in process flow diagram the design of 10 ° of cablings.
Claims (3)
1. one kind arranges the method for designing of 10 ° of cablings of high speed signal on PCB veneer, it is characterized in that: by designing program of 10 ° of cablings of high speed signal on a kind of PCB of setting veneer of use CADENCE AXLSKILL language development, when concrete operations, this Skill formula is put in wiring tool installation file, carrying out this SKILL formula will prompted dialog frame, according to the length of every section of 10 ° of cablings of dialog box input, then frame selects the Cline that needs to be designed to 10 ° of cablings, can complete the design of 10 ° of cablings.
2. a kind of method for designing that 10 ° of cablings of high speed signal on PCB veneer are set according to claim 1, is characterized in that, the concrete operation step of described method for designing is: first completing after cabling by traditional mode; Carry out described Skill program; Then frame selects the relevant Cline that needs to be designed to 10 ° of cablings; And input every section and be coiled into the length of 10 °, program will complete automatically according to the step in process flow diagram the design of 10 ° of cablings.
3. a kind of method for designing that 10 ° of cablings of high speed signal on PCB veneer are set according to claim 1 and 2, is characterized in that, described Skill program design is as follows:
axlCmdRegister(″ tune″ ′tune)
procedure(tune(0;set main function
(defun axlMyCancel ()
axlClearDynamics()
axlCancelEnterFun()
axlUIPopupSet(nil))
(defun axlMyDone ()
axlClearDynamics()
axlFinishEnterFun()
axlUIPopupSet(nil))
mypopup = axlUIPopupDefine (nil (list (list″MyCancel″ ′axlMyCancel) (list ″MyDone″ ′axlMyDone)))
axlUIPopupSet( mypopup)
axlSetFindFilter( enabled list (″noall″ ″clinesegs″) onButtons list (″noall″ ″clinesegs″))
axlClearSelSet(); set done and cancle command
while(axlSingleSelectBox()
desing=axlGetSelSet()
length=length(design)
;design_dbid1=car(axlGetSelSet())
design_dbid1=nth(0 design)
layer=design_dbid1-> layer
startEnd1=design_dbid1-> startEnd
a=nth(0 startEnd1)
b=nth(1 startEnd1)
xa=nth(0 a)
ya=nth(1 a)
xb=nth(0 b)
yb=nth(1 b)
xminmax=min(xa xb);left
xmaxmin=max(xa xb);right
yminup=max(ya yb);up
ymaxdown=min(ya yb);down
lineType=design_dbid1->lineType
; get need to route cline
case(lineType
;;the below is cline is horizontal
(horizontal
ylist=′()
allylist=′()
for ( 1 1 length
mel_db=nth(1-1 design)
staEnd=mei_db->width
ma=nth(0 staEnd)
mb=nth(1 staEnd)
mxa=nth(0 ma)
mxb=nth(0 mb)
mxleft=min(mxa mxb)
mxright=max(mxa mxb)
xminmax=max(mxleft xminmax)
xmaxmin=min(mxright xmaxmin)
my=nth(1 ma)
ylist=cons(width ylist)
ylist=cons(mxright ylist)
ylist=cons(mxleft ylist)
ylist=cons(my ylist)
allylist=cons(ylist allylist)
) ; end for
;get all need to route 10 degree information
paixudy=sortcar(allylist ′greaterp)
d=abs(xmaxmin-xminmax)-50
add_x=atof(axlUIPrompt(″please enter addx_distance″ ″125″))
m=(floor d/(2*add_x)) ;route how much cycle
firstx=nth(1 nth(0 paixudy));get max y coordinate clines x information
axlDeleteObject(design)
if (firstx==xminmax
then
rout=nth(0 paixudy)
qishiy=nth(0 rout)
qishix=nth(1 rout)
zhongx=nth(2 rout)
width=nth(3 rout)
xcank=xminmax+20
xo=xcank
wy1=qishiy-(add_x /5)
wy2=qishiy
path=axlPathStart(list(qishix:qishiy) width)
;axlDBCreateLine(list(qishix:qishiy x0:qishiy) width layer)
axlPathLine( path, width, x0:qishiy)
for(k 1 m
wx1=x0+add_x
wx2=wx1+add_x
;path+axlPathStart(list(xO:qishiy) width)
;axlDBCreateLine(list(x0:qishiy wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:xy1 wx2:wy2) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
xO=wx2
) ; for
; path=axlPathStart(list(wx2:wy2) width)
;axlDBCreateLine(list(wx2:wy2 zhongx:xy2) width layer)
axlPathLine( path,width, zhongx:xy2)
axlDBCreatePath( path,layer)
lasty1=wy1
lasty2=wy2
;xO=xminmax+5
xlast=wx2
for(q 1 length-1
if((m==1) then
rout=nth(g paixudy)
chushiy=nth(0 rout)
chushix=nth(1 rout)
zhongx=nth(2 rout)
width=nth(3 rout)
spac=abs(qishiy-chushiy)
xcank=xcank-(sqrt(26)-5)*spac-0.01
xO=xcank
xmm=xminmax+20
wx1=xmm+add_x
wx2=wx1+add_x
dyt=sqrt(26)*space/5+0.002
wy1=lasty1-dty
wy2=lasty2-dty
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, xO:chushiy)
for(1 1 length
mei_db=nth(1-1 design)
staEnd=mei_db->startEnd
width=mei_db->width
ma=nth(0 staEnd)
mb=nth(1 staEnd)
mya=nth(1 ma)
myb=nth(1 mb)
myup=max(mya myb)
mydown=min(mya myb)
yminup=min(myup yminup);qu up min
ymaxdown=max(mydown ymaxdown);qu down max
mx=nth(0 ma)
ylist=cons(width ylist)
ylist=cons(mydown ylist)
ylist=cons(myup ylist)
ylist=cons(mx ylist)
allylist=cons(ylist allylist)
);for
paixudy=sortcar(allylist ′greaterp)
d=abs(yminup-ymaxdown)-50
;mm=(floor d/add_x)
;m=(floor mm/2)
add_x=atof(axlUIPrompt(″plesae enter addx_distance″″125″))
m=(floor d/(2*add_x))
firsty=nth(1 nth(0 paixudy))
axlDeleteObject(design)
if((firsty==yminup)
then
a=1
rout=nth(0 paixudy)
qishix=nth(0 rout)
qishiy=nth(1 rout)
zhongy=nth(2 rout)
width=nth(3 rout)
ycank=yminup-10
yO=ycank
wx1=qishix-(add_x /5)
wx2=qishix
path=axlPathStart(list(qishix:qishiy) width)
axlPathLine( path,width, qishix:y0)
for(k 1 m
wy1=y0-add_x
wy2=wy1-add_x
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
y0=wy2
);for
axlPathLine( path, width, wx2:zhongy)
axlDBCreatePath( path, layer)
lastx1=wx1
lastx2=wx2
ylast=wy2
for(q 1 length-1
if ((m==1) then
rout=nth(q paixudy)
chushix=nth(0 rout)
chushiy=nth(1 rout)
zhongy=nth(2 rout)
width=nth(3 rout)
spac=abs(qishix-chushix)
ycank=ycank+(sqrt(26)-5)*spac+0.01
y0=ycank
ymm=yminup-10
wy1=ymm-add_x
wy2=wy1-add_x
dtx=sqrt(26)*spac/5+0.002
wx1=lastx1-dtx
wx2=lastx2-dtx
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, chushix:y0)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, chushix:(ylast-(sqrt926)-5*space-0.01)))
axlPathLine( path, width, chushix:zhongy)
axlDBCreatePath( path, layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
dtx=sqrt(26)*spac/5+0.002
wx1=lastx1-dtx
wx2=lastx2-dtx
path=axlPathStart(list(chushix:chushiy) width)
axlPathLine( path, width, chushix:y0)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, wx2:wy2)
y0=wy2
for(k 1 m-2
wy1=y0-add_x
wy2=wy1-add_x
; path=axlPathStart(list(wx2:y0) width)
;axlDBCreateLine(list (wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 wx2:wy2) width layer)
axlPathLine( path, width, wx1:xy1)
axlPathLine( path, width, wx2:xy2)
y0=wy2
);for
wy1=y0-add_x
wy2=ylast-(sqrt(26)-5)*spac-0.01
; path=axlPathStart(list(wx2:y0) width
;axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
; axlDBCreateLine(list(wx1:wy1 chushix:wy2) width layer)
;axlDBCreateLine(list(chushix:wy2 chushix:zhongy) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine(path, width,chushix:xy2)
axlPathLine(path, width,chushix:zhongy)
axlDBCreatePath(path, layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
ylast=wy2
);if
);for length-1
; path=axlPathStart(list(wx2:y0) width)
; axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 wx2:wy2) width layer)
axlPathLine( path,width,wx1:wy1)
axlPathLine( path,width,wx2:wy2)
y0=wy2
) ; for
wy1=y0-add_x
wy2=ylast-(sqrt(26)-5)*spac-0.01
; path=axlPathStart(list(wx2:y0 ) width)
; axlDBCreateLine(list(wx2:y0 wx1:wy1) width layer)
;axlDBCreateLine(list(wx1:wy1 chushix:wy2) width layer)
;axlDBCreateLine(list(chushix:wy2 chushix:zhongy) width layer)
axlPathLine( path, width, wx1:wy1)
axlPathLine( path, width, chushix:xy2)
axlPathLine( path, width, chushix:zhongy)
axlDBCreatePath( path,layer)
qishix=chushix
lastx1=wx1
lastx2=wx2
ylast=wy2
);if m=1
);for
);if
);vertical
);case
);while
)
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410284771.8A CN104021257A (en) | 2014-06-24 | 2014-06-24 | Design method for setting 10-degree wiring of high-speed signals on single PCB (Printed Circuit Board) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410284771.8A CN104021257A (en) | 2014-06-24 | 2014-06-24 | Design method for setting 10-degree wiring of high-speed signals on single PCB (Printed Circuit Board) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104021257A true CN104021257A (en) | 2014-09-03 |
Family
ID=51438011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410284771.8A Pending CN104021257A (en) | 2014-06-24 | 2014-06-24 | Design method for setting 10-degree wiring of high-speed signals on single PCB (Printed Circuit Board) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104021257A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220424A (en) * | 2017-05-22 | 2017-09-29 | 郑州云海信息技术有限公司 | A kind of isometric system and method for adjust automatically high speed wire harness based on Cadence skill |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030028630A1 (en) * | 2001-07-31 | 2003-02-06 | Gerhard Bischof | Method and system for processing topology data and geometry data of networks |
| CN103761399A (en) * | 2014-01-26 | 2014-04-30 | 浪潮(北京)电子信息产业有限公司 | Method and system for designing wire routing |
| CN103778296A (en) * | 2014-01-26 | 2014-05-07 | 浪潮(北京)电子信息产业有限公司 | Design method and system for quickly generating light painting layer of printed circuit board (PCB) |
-
2014
- 2014-06-24 CN CN201410284771.8A patent/CN104021257A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030028630A1 (en) * | 2001-07-31 | 2003-02-06 | Gerhard Bischof | Method and system for processing topology data and geometry data of networks |
| CN103761399A (en) * | 2014-01-26 | 2014-04-30 | 浪潮(北京)电子信息产业有限公司 | Method and system for designing wire routing |
| CN103778296A (en) * | 2014-01-26 | 2014-05-07 | 浪潮(北京)电子信息产业有限公司 | Design method and system for quickly generating light painting layer of printed circuit board (PCB) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220424A (en) * | 2017-05-22 | 2017-09-29 | 郑州云海信息技术有限公司 | A kind of isometric system and method for adjust automatically high speed wire harness based on Cadence skill |
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Application publication date: 20140903 |