CN104009733A - Hardware Implementation Method of Sample Importance Resampling Particle Filter Based on FPGA - Google Patents

Abstract

The invention discloses a hardware implementation method of a sample importance resampling particle filter based on FPGA, the method is as follows: (1) The particle generation module is used to receive input vectors to generate particles and then output them to the particle update module, resampling module; (2) the particle update module is used to update the particles generated in step (1), that is, the weight calculation and weight normalization are output to the resampling module; (3) the resampling module is used to update the step (2) The updated particles or the particles generated in step (1) are fed back to the step (1) particle generation module after the resampling process and state update; (4) the output generation module is used to update the step (2) Particles or particles generated in step (1) are used for data generation and output.

Description

Hardware Implementation Method of Sample Importance Resampling Particle Filter Based on FPGA

technical field

The invention relates to a hardware implementation method of a particle filter algorithm based on FPGA, a module-level assembly line design method using a data flow structure, and belongs to the field of nonlinear system filtering and electronic technology.

Background technique

Particle filter is a statistical filtering method based on Monte Carlo method and recursive Bayesian estimation, which is suitable for any nonlinear stochastic system with non-Gaussian background that can be represented by state space model and traditional Kalman filter.

However, particle filtering has problems such as particle degradation, loss of particle diversity, year-on-year increase in the number of particles and computational complexity. On the other hand, the particle filter algorithm is more complex and the amount of calculation is relatively large, which makes the real-time performance of the particle filter very poor and hinders its practical application. Considering the independence of each particle and the parallelism of its operation, hardware implementation is one of the effective ways to improve the real-time performance of particle filter. At present, the vast majority of particle filter literature is about its theoretical research and algorithm simulation, but very little about its hardware implementation. The application of particle filter on the hardware system is only in its infancy, and the hardware implementation is a key link in the process of particle filter from theory and algorithm research to practical application. With the in-depth study of particle filter algorithm and the development of embedded microprocessor technology, the hardware realization of particle filter algorithm becomes possible.

Reconfigurable computing was first proposed by Professor Estrin of the University of California, Los Angeles in 1962. Reconfigurable computing refers to the use of systems integrated with programmable hardware for computing, and the functions of programmable hardware can be defined by a series of physically controllable points that change at regular intervals, and the computing hardware structure can be changed (reconfigurable). In the late 1970s, Suetlana P. et al. proposed the concept of a dynamic reconfigurable system, and studied the partial reconfiguration of the system while the system was running, changing its configuration, and improving system performance and resource utilization. In the late 1990s, with the further maturity of FPGA technology, FPGA became the mainstream hardware platform for reconfigurable computing, and many algorithms (such as Kalman filter algorithm) appeared FPGA-based hardware computing methods. Currently, FPGA devices already support more advanced and flexible dynamic reconfiguration techniques.

Contents of the invention

In order to improve the calculation efficiency and precision of the particle filter algorithm implemented by hardware, the present invention proposes a hardware implementation method of the sample importance resampling particle filter based on FPGA, and uses FPGA to design each module of the particle filter algorithm, thereby providing complex solutions for engineering applications. Efficient calculation and hardware implementation of particle filter algorithm provide a novel solution.

The present invention is based on the FPGA-based sample importance resampling particle filter (Samples ImportanceResampling Particle Filter—SIRF) hardware implementation method, the particle filter includes a particle generation module, a particle update module, a resampling module and an output generation module, wherein:

(1) The particle generation module is used to receive the input vector to generate particles and output them to the particle update module and the resampling module respectively;

(2) The particle update module is used to update the particles generated in step (1), that is, the weight calculation and weight normalization are output to the resampling module;

(3) The resampling module is used to feed back to the particle generation module of step (1) after performing a resampling process and state update to the particles after the update described in step (2) or the particles generated in step (1);

(4) The output generating module is used to generate and output data on the updated particles described in step (2) or the particles generated in step (1).

All input and output of the particle generation module in step (1) are M-dimensional (M=4) vectors, and the parameters of the buffer controller are the same.

All input and output data of the resampling module are M-dimensional.

The particle update module described in step (2) is divided into three processing modules: PU1, PU2 and PU3;

The PU1 processing module receives the input from the particle generation module, and outputs the M-dimensional temporary data t _PU1 to the PU2 processing module;

The PU2 module receives the M-dimensional temporary data t _PU1 from the PU1 processing module and the external observation input (z(n)) for weight calculation to form an output stream t _PU2 , and simultaneously generates the weight accumulation value sum;

The PU3 processing module receives the output stream t _PU2 and the weight accumulation value sum from the PU2 processing module for weight normalization, then stores the normalized weight w in the output buffer, and outputs it to the resampling module and the particle generation module.

The output generation module standardization output described in step (4) is:

${\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; sum</span>}\underset{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; PU</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; .</span>$

Among them: u _x is the output variable of the output generation module; sum is the weight sum; t _PU2 is the output of the PU2 module.

The hardware design method proposed by the invention can be extended to dynamic reconfiguration of different particle filters. For each particle filter, first define the operation of each processing module, then define the data flow structure, and finally design the buffer controller and global controller.

The most important part is the data center, which is responsible for handling the large amount of data transfer between modules. The entire filter is designed using a block-level pipeline, which greatly simplifies the design process. Module-level pipelines achieve synchronous execution through distributed controllers that control the data generation and transmission of individual processing modules.

The main beneficial effect of the design of the present invention is to provide the specific process of designing particle filter hardware using the module-level pipeline design idea. At the same time, the weight normalization step in the particle filter algorithm is removed by adopting the loop fusion method, thereby realizing Parallel distributed structure of sampling, weight calculation and resampling process. This particle filter design method speeds up the execution time of the filter, and at the same time reduces the algorithmic complexity of the particle filter algorithm.

Description of drawings

Figure 1 The data flow diagram of SIRF;

Figure 2 The data relationship between the various modules of the SIRF algorithm;

Figure 3 The data flow diagram of SIRF implemented in FPGA.

Detailed ways

The particle filter algorithm has the following two unique execution characteristics: (1) It can be expressed as a data flow graph, and nodes (or modules) can be executed concurrently. Although the complexity of each module is different, the data flow graph can clearly represent the data dependencies between modules; (2) Each module in the data flow graph processes a set of data in each cycle.

In order to apply hardware to implement particle filtering, the present invention adopts a module-level pipeline design method, and divides particle filtering into a particle generation module, a particle update module, a resampling module, and an output generation module. Each module is executed in parallel, which can significantly improve the operating efficiency of the algorithm. At the same time, in order to make full use of the buffer controller, the processing modules are designed according to the following three requirements: (1) The processing modules are designed on the basis of eliminating the dependence of control signals (except for data dependencies) among the processing modules. If there are dependencies on the control signals between any two processing modules, these dependencies are engineered through the temporal data. If the dependency between the control signals is completely unavoidable, the control signal is used as data and the control is realized through the buffer controller. (2) Select the size of the processing module under the premise of ensuring that the data is generated and used at a certain speed, and at the same time ensure that the amount of generated and used data is consistent. (3) There is only one global clock, and the clock signals of other processing modules all come from the global clock.

The present invention adopts a distributed controller, uses a module-level pipeline design method to design a sample importance resampling particle filter (SIRF), takes two-dimensional orientation-only target tracking as the processing object, and the unknown state mainly estimated is the Cartesian coordinate system (X _n = [x, V _x , y, V _y ] ^T ), where x and y refer to the position coordinates of the target, and V _x and V _y are the velocity components in the x and y directions respectively. The whole particle filter is composed of several processing modules, each processing various complex arithmetic operations, and each processing module has a local controller for controlling its operation. Distributed control can efficiently handle the data dependencies among various data modules.

The whole particle filter is divided into several processing modules, each processing module has a local controller for controlling its operation. First define the operation of each processing module, and then define the data flow structure. At the same time, a buffer controller and a global controller are designed. The global controller controls the data generation and transmission of each processing module, and uses distributed control to efficiently process the data dependencies between each data module. The module-level pipeline is implemented through the distributed controller. Implement synchronous execution. The entire filter is designed using a block-level pipeline, which greatly simplifies the design process.

The present invention has designed each processing module of SIRF, comprises particle generation module (PG), particle update module (PU), average calculation/generate output (MC/OG), resampling (RS) module etc., as shown in Figure 1 SIRF's module data flow diagram.

(1) Module design

Particle Generation Module (PG): The main function of this module is to generate particles. In the PG processing module, there are four connected input vectors and 4 buffers connecting the output vectors (x,V _x ,y,V _y ). The output of the PG block is used for the resampling (RS) block. In addition, two buffers connected (x,y) are used for the particle update module PU1. All input and output are M-dimensional vectors, and the parameters of the buffer controller are the same. The particle generation module obtains all outputs through parallel computing.

Particle update module (PU): The main function of the particle update module is to complete weight calculation and weight normalization. The arithmetic operations completed by this module include multiplication, classification, division, inverse trigonometric function arctan() and exponential function exp( ). The operators used for artan() and exp() are expanded using the Coordinate Rotation Digital Computation Method (CORDIC). According to the dimension of the operation unit, the particle update operation is functionally divided into three processing modules: PU1, PU2 and PU3.

The PU1 processing module has 2 input buffers that receive (x,y) from the PG processing module and 1 buffer that delivers the output t _PU1 to the PU2 processing module. The PU1 processing module completes the calculation of artan(y/x) and generates M-dimensional temporary data t _PU1 . For the artan() operation, in order to distinguish between (-x,y) and (x,-y), a constant value π/2 and a multiplexer are used to adjust the angle. Since there is no data dependency between the PG and PU1 processing modules, once the input buffer of the PU1 module gets data, the PU1 processing module directly calculates its output.

The PU2 module has two input buffers, one from the PU1 processing module (t _PU1 ) and the external observation input (z(n)). During the nth iteration, the value of z(n) does not change. PU2 has two output buffers. are (t _PU2 ) and (sum) output to the PU3 processing module, respectively. The two output buffers of the PU2 module deliver (t _PU2 ) and (sum) to the PU3 module. The function of the PU2 module is mainly responsible for weight calculation, but this module does not normalize the weights, but defines them as output stream (t _PU2 ). At the same time, at the end of the weight calculation, these weights are accumulated to generate a sum, and the sum is used as the input of the PU3 processing module for weight normalization. The PU3 processing module has two input buffers (t _PU2 , sum) from the PU2 processing module, PU3 normalizes each unnormalized t _PU2 and sum, and then stores the normalized weight w in the output buffer and uses it for the RS processing module and A PG processing module that generates particles.

Resampling module (RS): The RS module mainly performs the resampling process and state update calculation, so there is no need to design a separate state update module. The RS module has 5 input buffers, of which 4 buffers connected to (x,V _x ,y,V _y ) come from the PG processing module, and one buffer comes from the normalized weight (w) in the PU3 processing module buffer. resampled output Stored in 4 output buffers. All input and output data of the RS module are M-dimensional.

The RS processing module replicates particles with larger weights and eliminates particles with lower weights. This is done by reading each weight and duplicating the particle based on the weight. Because all the weights are normalized and the sum of the weights is equal to 1. Therefore, there are the same number of particles after resampling. The whole resampling process needs at least M clock cycles, because in the worst case, all weights may be zero, so valid particles may be generated after M cycles. The output of the RS processing module must be available after M cycles. Therefore, the PG and OG processing modules must wait for M cycles before reading valid data.

Output Generation Module (MC/OG): To share module buffers and interconnections, this module is designed using the data generated by the PG processing module and the weights and sums calculated by the PU2 processing module. Then execute this module and normalize the output by the value of sum as:

${\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; sum</span>}\underset{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; PU</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The data relationship between the various modules of the SIRF algorithm is shown in Figure 2, which shows the data connection relationship between the processing module and the buffer. Resampling and state updating are combined into the same module and the output (estimation) calculation step gets data directly from the sampling step.

(2) Controller design

The buffer controller is used to realize the overall operation of the filter, and the parameters that determine the structure of the controller and the overall realization are as follows: L _maxi , L _i , _nri , _nwi , Mi _, C _i , P _i , F _i and D _i . Where L _maxi refers to the logical delay between processing modules; the actual range of L _i is 0<L _i <L _maxi ; nr _i is the offset between the write buffer and the read buffer; nw _i is The offset between reading the buffer controller at the previous moment and writing the current buffer controller; C _i , P _i and F _i refer to the data usage rate, data generation speed and processing speed of processing module i respectively; Di is Refers to the delay coefficient of data generated by processing module i. The parameter M _i is the data flow dimension of the data generation module, the parameters (M _i ,nri _{, nwi} ) are obtained by the description function, and the parameters (L _i ,C _i ,P _i ,F _i ,D _i ) are obtained by the processing module Realize the program to get.

(3) FPGA implementation

The data flow diagram of SIRF implemented by FPGA is shown in Figure 3, and the connection relationship between the processing module and the buffer is shown in the figure. Table 1 lists the main parameters of each processing module. The actual speed range of the processing module is between 206MHz and 351MHz. Due to the speed limit of the CORDIC method and to simplify the controller design, 206MHz is selected as the global clock. The delay value can be obtained from the internal data flow, and the table also shows the FPGA resources occupied by each module when the FPGA is implemented.

Table 1 processing module information table

Table 2 shows the data dependencies among the various modules. Except for E3, E4, E6, E7 and E8 in this table, other connection parameters are default. For connection E3 and E4, since the last data of t _PU2 is used to generate sum at the same time, then there are nw ₃ =M+1, nw ₄ =2 respectively. It can be seen from the timing diagram that sum is used by the PU2 module after M cycles The Mth data generation of t _PU2 . For E6 there is nr ₆ =M+60, where nr ₁ +L _PU1 +nr ₂ +nw ₂ +L _PU2 +nr ₄ +nw ₄ +L _PU3 +nr ₅ =1+23+1+1+20+2+ 1+10+1=60. In order to wait for the RS module to generate the first data, nw ₇ =M, nw ₈ =M for E7 and E8 respectively. Since there is no rate mismatch, the values of D are all 1, and only when E5 transmits 1 data, other links transmit M data (that is, data vectors). The number of buffers used simultaneously is about 5M, where M is the number of particles used by the filter. In order to assign different addresses to the read and write logic, storing one data per buffer requires multiple memory units.

Table 2 Link Information Table (EIT) of SIRF

The parameters of all buffer controllers of SIRF are deduced from Table 1 and Table 2, as shown in Table 3. This table gives the start time, write start time and read start time for each buffer controller.

Pay attention to several key synchronization points of the data flow structure: (1) The start time of the buffer controllers of E1 and E6 is the same as the start time of writing; (2) Since the RS module processes two data, the buffer controllers of E5 and E6 read The start time is the same; (3) The buffer controllers of E7 and E8 are used at the same time; (4) The buffer controllers of E3 and E4 are started at the same time.

Table 3 Buffer controller parameters of SIRF

Claims (5)

1. a Hardware Implementation for the sample importance Resampling Particle Filter based on FPGA, is characterized in that described particle filter comprises particle generation module, particle update module, resampling module and output generation module, wherein:

(1) particle generation module exports respectively particle update module, resampling module to after being used for receiving input vector generation particle;

(2) it is to export resampling module to after weights calculating and weights normalization that the particle that particle update module is used for that step (1) is generated upgrades;

(3) resampling module feeds back to step (1) particle generation module for the particle of the particle after the described renewal of step (2) or step (1) generation being carried out after resampling process and state upgrade;

(4) output generation module generates output for the particle of the particle after the described renewal of step (2) or step (1) generation is carried out to data.

2. the Hardware Implementation of the sample importance Resampling Particle Filter based on FPGA according to claim 1, it is characterized in that all input and output of the described particle generation module of step (1) are all M (M=4) dimensional vectors, and the parameter of buffer control unit is identical.

3. the Hardware Implementation of the sample importance Resampling Particle Filter based on FPGA according to claim 1, is characterized in that all inputoutput datas of described resampling module are all M (M=4) dimensions.

4. the Hardware Implementation of the sample importance Resampling Particle Filter based on FPGA according to claim 1, is characterized in that the described particle update module of step (2) is divided into three processing module: PU1, PU2 and PU3;

PU1 processing module receives the input from particle generation module, will export M dimension ephemeral data t _pU1be transported to PU2 processing module;

PU2 module receives the M dimension ephemeral data t from PU1 processing module _pU1carry out weights with external observation input (z (n)) and calculate formation output stream t _pU2, generate weights accumulated value sum simultaneously;

PU3 processing module receives the output stream t from PU2 processing module _pU2sum carries out weights normalization with weights accumulated value, then standardized weight w is stored in to output buffer, and exports resampling module and particle generation module to.

5. the Hardware Implementation of the sample importance Resampling Particle Filter based on FPGA according to claim 1, is characterized in that the described output generation module normalization output of step (4) is:

${\mathrm{\&mu;}}_x=1/\mathrm{sum}\underset{m=1}{\overset{M}{\mathrm{\&Sigma;}}}x\left(m\right)t_{\mathrm{PU}2}\left(m\right)$

Wherein: u _xoutput variable for output generation module; Sum be weights and; t _pU2output for PU2 module.