CN104009682A - Brushless DC motor controller and control method - Google Patents

Brushless DC motor controller and control method Download PDF

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Publication number
CN104009682A
CN104009682A CN201410253909.8A CN201410253909A CN104009682A CN 104009682 A CN104009682 A CN 104009682A CN 201410253909 A CN201410253909 A CN 201410253909A CN 104009682 A CN104009682 A CN 104009682A
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port
ports
circuit module
resistance
oxide
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CN201410253909.8A
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CN104009682B (en
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鲁文其
王玮
史伟民
胡旭东
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Zhejiang University of Technology ZJUT
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Zhejiang University of Technology ZJUT
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Abstract

The invention discloses a brushless DC motor controller. The brushless DC motor controller includes a CPLD and peripheral circuit module and the like. The CPLD and peripheral circuit module produces a drive signal after receiving a control command sent by a man-machine interface module, a PWM wave generation circuit module and a protective circuit module and a three-phase Hall signal sent by a brushless DC motor; a drive circuit module receives the drive signal from the CPLD and peripheral circuit module and generates a control signal according to the drive signal; a three-phase bridge inverter circuit module receives the control signal from the drive circuit module and controls the brushless DC motor; the protective circuit module detects the three-phase bridge inverter circuit module and the drive circuit module and feeds back detection results to the CPLD and peripheral circuit module in the form of control commands; a power supply module converts 28V total voltage into 5V voltage and 15V voltage and correspondingly transmits the 5V voltage or the 15V voltage to the CPLD and peripheral circuit module, the three-phase bridge inverter circuit module, the drive circuit module, the protective circuit module, the man-machine interface module and the PWM wave generation circuit module.

Description

Brushless direct current motor controller and control method
Technical field
The present invention relates to a kind of controller of brshless DC motor, relate in particular to a kind of controller and control method of brshless DC motor operation of the low-voltage, high-current for rotating band Hall element.
Background technology
Brshless DC motor (Brushless Direct Current Motor, BLDC) utilize electronics commutation device to replace having the mechanical commutation device of brushless motor, make its both had that DC motor speed regulating performance is good, volume is little, lightweight, efficiency is high, without features such as excitation losses, there is again the advantages such as ac motor structure is simple, reliable, easy to maintenance simultaneously, in the every field of national economy, as the aspects such as medical machinery, instrument and meter, chemical industry, weaving and household electrical appliance and office automation are all widely used.The present invention is directed to the industries such as electri forklift, electric golf car, electronic touring car, designed a kind of brushless direct current motor driver that this occasion drives that is applicable to, there is low-voltage, high-current, fast response time, cost is low and reliability is high feature.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of brushless direct current motor controller simple in structure and control method.
In order to solve the problems of the technologies described above, the invention provides a kind of brushless direct current motor controller, comprise brshless DC motor, CPLD and peripheral circuit module, three-phase bridge inverter circuit module, drive circuit module, protective circuit module, power supply module, human-machine interface module and PWM ripple generative circuit module; Described CPLD and peripheral circuit module receive respectively the control command that human-machine interface module, PWM ripple generative circuit module and protective circuit module are sent, and after the three-phase hall signal that sends of brshless DC motor, produce and drive signal; Drive circuit module receives the driving signal of CPLD and peripheral circuit module, and will drive signal to generate control signal; Three-phase bridge inverter circuit module receives the control signal of drive circuit module, and controls the operation of brshless DC motor; Protective circuit module detects three-phase bridge inverter circuit module and drive circuit module, and testing result is fed back to CPLD and peripheral circuit module with the form of control command; Described power supply module is transformed into 5V and 15V by 28V total voltage, and 5V or 15V voltage are transported in corresponding CPLD and peripheral circuit module, three-phase bridge inverter circuit module, drive circuit module, protective circuit module, human-machine interface module and PWM ripple generative circuit module.
As the improvement to brushless direct current motor controller of the present invention: described PWM ripple generative circuit module comprises the Schmidt trigger circuit that 555 chips form, and this Schmidt trigger circuit sends corresponding control command to CPLD and peripheral circuit module.
As the further improvement to brushless direct current motor controller of the present invention: described human-machine interface module comprises motor positive and inverse and brake control circuit and system mode display circuit, and motor positive and inverse and brake control circuit send corresponding control command to CPLD and peripheral circuit module; Described CPLD and peripheral circuit module are fed back corresponding signal to system mode display circuit.
As the further improvement to brushless direct current motor controller of the present invention: described CPLD and peripheral circuit module are comprised of CPLD chip U5,5 needle interface P1, JTAG mouth P2, active crystal oscillator U6, resistance R 34, R35, R36, R37, R44, R45, R46 and capacitor C 15, C16, C17; Described drive circuit module is by integrated drive chips U13, U14, U15, capacitor C 24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, and diode D29, D30, D31, D32, D33, D34 form; Described three-phase bridge inverter circuit module adopts three phase full bridge structure, by P3 interface, N-channel MOS pipe Q1, Q1, Q1, Q1, Q1, Q6, resistance R 1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, capacitor C 1, C2, diode D1, D2, D3, D4, D7, D8, D9, D10, D13, D14, D15, D16, voltage stabilizing didoe D5, D6, D11, D12, D17, D18 form; Described protective circuit module comprises metal-oxide-semiconductor current foldback circuit and busbar voltage over under-voltage protection circuit; Described metal-oxide-semiconductor current foldback circuit is by optocoupler U7, U8, U9, U10, U11, U12, resistance R 47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, capacitor C 18, C19, C20, C21, C22, C23, the adjustable voltage-stabiliser tube D23 of three ends, D24, D25, D26, D27, D28 form; Described busbar voltage over under-voltage protection circuit is by operational amplifier U3A, U3B, and resistance R 24, R25, R26, R29, R30, R31, R32, R33 form; Described PWM ripple generative circuit module is by 555 chip U1, resistance R 21, R23, and slide rheostat R22, capacitor C 3, C4, diode D19, D20 form; Described human-machine interface module comprises motor positive and inverse and brake control circuit and system mode display circuit; Described motor positive and inverse and brake control circuit are by self-locking button S1-F/R, S2-STOP, polarity free capacitor C5, C6, C8, C9, C10, C11, resistance R 27, R28; Described system mode display circuit comprises resistance R 38, R39, R40, R41 and R42, and light-emitting diode DS1, DS2, DS3, DS4 and DS5 form; Comprise+15V of power supply module output port and+5V output port, by power supply chip U2, U4, polar capacitor C7, C12, C13, C14, diode D21, D22, inductance L 1, L2 form; The syndeton of described power supply module is as follows: 1 port of described power supply chip U2 is general supply port; 3, the 5 port ground connection of power supply chip U2; The positive pole of polar capacitor C7 connects 1 port of power supply chip U2, negative pole; 2 ports of power inductance L1 mono-termination power supply chip U2, other end conduct+15V output port; Connect+15V of the positive pole of polar capacitor C12 output port, minus earth; The negative pole of Schottky diode D21 connects 2 ports of power supply chip U2, plus earth, and 4 ports of power supply chip U2 are unsettled; 1 port of described power supply chip U4 is general supply port; 3 and the 5 port ground connection of power supply chip U4; The positive pole of polar capacitor C13 connects 1 port of power supply chip U4, minus earth; The port 2 of power inductance L2 mono-termination power supply chip U4, other end conduct+5V output port; Connect+5V of the positive pole of polar capacitor C14 output port, minus earth; The negative pole of Schottky diode D22 connects 2 ports of power supply chip U4, plus earth, and 4 ports of power supply chip U4 are unsettled; The syndeton of described CPLD and peripheral circuit module is as follows: positive pole and the negative pole of described capacitor C 15, C16 and be connected respectively to+5V of C17 output port; 16,38 connect+5V of the port output ports of CPLD chip U5; 6,17,28, the 39 port ground connection of CPLD chip U5; 40,41,42 ports of CPLD chip U5 connect respectively 2,3,4 ports of 5 needle interface P1, and 2,3,4 ports of 5 needle interface P1 are respectively by move on resistance R 44, R45, R46+5V output port; Connect+5V of the 1 port output port of 5 needle interface P1, the 5 port ground connection of 5 needle interface P1; 7 ports of CPLD chip U5 are connected to 1 port of JTAG mouth P2, and 26 ports of CPLD chip U5 are connected to 3 ports of JTAG mouth P2; 4 ports of CPLD chip U5 are connected to 5 ports of JTAG mouth P2; 29 ports of CPLD chip U5 are connected to 7 ports of JTAG mouth P2; 1,3,5,7 move on resistance R 34, R35, R36 and R37 respectively+5V of the port output ports of described JTAG mouth P2; Connect+5V of the 6 ports output port of JTAG mouth P2,4,8 port ground connection; All the other ports of JTAG mouth P2 are unsettled; 5 ports of CPLD chip U5 are connected to 3 ports of source crystal oscillator U6, connect+5V of the 4 ports output port of active crystal oscillator U6, and the 2 port ground connection of active crystal oscillator U6,1 port of active crystal oscillator U6 is unsettled;
Connecting the drive circuit module is structured as follows: 1 integrated driver chip U13 port labeled U_Hin port and 35-port connected to the CPLD chip U5; integrated driver chip U13 2-port labeled U_Lin port, and with the CPLD chip U5 the 34 ports are connected; 4-port integrated driver IC U13 mark for LO1 port; 6 port labeled integrated driver chip U13 is VS1 port; 7 port labeled integrated driver chip U13 is HO1 port; integrated 8-port driver chip U13's mark to V_HB1 port; grounding integrated 3-port driver chip U13's; integrated driver IC U13 5-port connected to + 15V power supply positive; 6 and 8-port integrated driver IC U13 direct parallel connection of two non-polar capacitors C24 and C27; diode D29 and negative poles 6 ports, positive ground integrated driver IC U13's; diode D32 cathode connected to an integrated 8-port driver chip U13, positive connection + 15V power supply positive; polar and non-polar capacitor capacitance C30 C33 parallel series after the + 15V power supply; integrated drive chip a port labeled U14 is V_Hin port and 33-port connected to the CPLD chip U5; integrated 2-port marked U14 driver chips for V_Lin port and 32-port connected to the CPLD chip U5; integrated driver IC U14 4 port labeled LO2 port; integrated driver IC U14 6-port labeled VS2 port; integrated driver IC U14 7 port labeled HO2 port; integrated driver IC U14 8-port labeled V_HB2 port; integrated driver IC 3 port grounded U14's ; integrated 5-port driver chip U14 pick + 15V power supply positive; 6 and 8-port direct parallel connection of two non-polar capacitor C25 integrated driver chips U14 and C28; diode D30 cathode connected to the integrated driver IC 6 ports, positive ground U14's; diode D33 negative then integrated 8-port driver chip U14, positive connection + 15V power supply positive; after polar and non-polar capacitor C31 C34 parallel capacitor in series with the + 15V power supply; integrated driver chip U15 is a port labeled W_Hin port, and with CPLD chip U5 is connected to port 31; 2 port labeled integrated driver chip U15 is W_Lin port and 30-port connected to the CPLD chip U5; 4-port integrated driver IC U15 mark for LO3 port; integrated driver IC U15 6 port labeled VS3 port; 7 port labeled integrated driver chip U15 is HO3 port; eight integrated driver IC U15 port labeled as V_HB3 port; grounding integrated 3-port driver chip U15's; integrated 5-port driver chip U15 pick + 15V power supply positive; 6 and 8-port integrated driver chip U15 direct parallel of the two non-polar capacitors C26 and C29; diode D31 negative six ports, positive ground connection integrated driver chip U15's; diode D34 cathode connected to an integrated 8-port driver chip U15, positive then + 15V power supply positive; polar and non-polar capacitor capacitance C32 C35 parallel series after the + 15V power supply; connection structure of the three-phase bridge inverter circuit module are as follows: P3 is a port of the interface connected to the mains positive, interface 2 ports connected to the main power P3 negative; after polar capacitors C1 and C2 coupled to the total power; after two resistors R1 and R2 in series connected to the main power supply; MOS transistors Q1 and Q2, Q3 and Q4 and Q5 and Q6 respectively constitute the three-phase full-bridge arm; source MOS transistor Q1 is marked as VS1 output port, and connected with integrated driver IC U13's VS1 port; source MOS transistor Q3 pole output port labeled VS2 and connected with integrated driver IC U14's VS2 port; source MOS transistor Q5 is marked as VS3 output port, and with integrated driver IC U15's VS3 port is connected; two diodes D1, D3 in the same direction after the series, the negative pole MOS tube Q1 drain, positive mark for FAULT_1 port; termination resistors R5 a gate MOS transistor Q1, and the other end is marked as HO1 port, and connected with integrated driver IC U13's HO1 port; regulator D5 negative pole gate MOS transistor Q1 , cathode connected MOS transistor Q1 source; resistor R7 in parallel on the regulator D5; between HO1 port three-phase bridge inverter circuit module FAULT_1 port and three-phase bridge inverter circuit module resistor R3 is connected; two diodes D2, D4 in the same direction after the series MOS transistor Q2 is connected to the drain of the negative electrode, a positive labeled FAULT_2 port; one end of the resistor R6 is the gate of MOS transistor, and the other end Q2 labeled LO1 port and connected to the integrated driver IC U13 port LO1 ; D6 negative regulator connected MOS Q2 gate tubes, cathode connected MOS transistor Q2 source, in parallel with the resistor R8 regulator D6; phase bridge inverter circuit module FAULT_2 port and three-phase bridge inverter circuit module LO1 port connection between resistors R4; two diodes D7, D9 to the same series, the negative pole drain MOS transistor Q3, positive mark for FAULT_3 port; termination resistor R11 a gate MOS transistor Q3, the other end of the port labeled HO2 , and connected with integrated driver IC U14's HO2 port; D11 negative regulator connected MOS transistor Q3 gate MOS transistor Q3 positive then the source, resistor R13 in parallel with the zener diode D11; phase bridge inverter circuit module the FAULT_3 port HO2 port connection between the resistor R9 and a three-phase bridge inverter circuit modules; two diodes D8, D10 to the same series MOS transistor Q4 connected to the drain of the negative, positive mark for FAULT_4 port; one end of the resistor R12 MOS Q4 pipe gate, and the other end is marked as LO2 port, and connected with integrated driver IC U14's LO2 port; negative regulator D12 Q4 gate MOS transistor connected to the positive source connected MOS transistor Q4, resistor R14 connected in parallel regulator tube D12; LO2 between resistor R10 FAULT_4 port connector port and three-phase bridge inverter circuit module three-phase bridge inverter circuit modules; two diodes D13, D15 series after the same direction, negative then drain MOS transistor Q5, positive mark for FAULT_5 port; termination resistor R17 a gate MOS transistor Q5, and the other end is marked as HO3 port, and connected with HO3 port integrated driver chip U15's; D17 Q5 negative gate MOS transistor connected to the regulator, the positive connection MOS Q5 tube source, resistor R19 in parallel with the zener diode D17; between HO3 port three-phase bridge inverter circuit module FAULT_5 port and three-phase bridge inverter circuit module is connected with the resistor R15; two diodes D14, D16 in the same direction after the series MOS transistor Q6 connected to the drain of the negative electrode, a positive labeled FAULT_6 port; one end of resistor R18 is the gate of MOS transistor Q6, and the other end is marked as LO3 port and connected to the integrated driver IC U15 LO3 port; regulator D18 negative pole gate MOS transistor Q6, cathode connected MOS transistor Q6 source, resistor R20 in parallel with the regulator D17; LO3 port between the three-phase bridge inverter circuit module FAULT_6 port and three-phase bridge inverter circuit modules with resistance R16 connection; connection structure of the protection circuit module are as follows: one end of a port and the other end of the resistor R47 mark optocoupler U7 is V_HB1 port, and connect with integrated driver IC U13's V_HB1 port phase; one end of the resistor R48 three terminal adjustable regulator D23 2-port and the other end is marked as FAULT_1 port, and connected with FAULT_1 port three-phase bridge inverter circuit modules; three-terminal adjustable regulator D23's three ports marked as VS1 port and and VS1 port three-phase bridge inverter circuit module is connected; non-polar capacitor C18 in parallel on a three-terminal adjustable regulator D23 2,3 port; three-terminal adjustable regulator D23 is a port to connect optocoupler U7 2-port; one end of the resistor R49 of U8 1-port optical coupler, the other end of + 15V output port; one end of the resistor R50 of the three-terminal adjustable regulator port D24 of pipe 2, and the other end is marked as FAULT_2 ports, and with FAULT_2 port is connected to a three-phase bridge inverter circuit modules; three-terminal adjustable regulator 3-port ground D24's; nonpolar capacitor C19 in parallel three-terminal adjustable regulator 2,3 port D24; third terminal can D24 is a tone regulator port connection optocoupler U8 2-port; one port of a termination resistor R51 optocoupler U9, and the other end is marked as V_HB2 port, and connected with integrated driver IC U14's V_HB2 port; resistor R52 of one end of the three-terminal adjustable regulator D25 2-port and the other end is marked as FAULT_3 port, and connected with FAULT_3 port three-phase bridge inverter circuit modules; three-terminal adjustable regulator 3-port labeled D25 is VS2 port, and connected with a three-phase bridge inverter circuit VS2 port modules; nonpolar capacitor C20 in parallel three-terminal adjustable regulator D25 of 2,3 port; 1 port connection three-terminal adjustable regulator D25's the 2-port optical coupler U9; port 1 a termination resistor R53 optocoupler U10, the other end of the + 15V output port; one end of the resistor R54 of the three-terminal adjustable 2 port and the other end of the Zener diode D26 to the port labeled FAULT_4 , and connected with FAULT_4 port three-phase bridge inverter circuit modules; three-terminal adjustable regulator 3-port ground D26's; nonpolar capacitor C21 in parallel on a three-terminal adjustable regulator D26 2,3 port; three-terminal adjustable regulator D27 is a port to connect optocoupler U10 2-port; one port of a termination resistor R55 optocoupler U11, and the other end is marked as V_HB3 port, and connected with integrated driver IC U15's V_HB3 port; a termination resistor R56 adjustable three-terminal regulator 2 port and the other end of the D27 is labeled FAULT_5 port, and connected with FAULT_5 port three-phase bridge inverter circuit modules; three-terminal adjustable regulator D27's three ports labeled VS3 port, and connected with VS3 port three-phase bridge inverter circuit modules; nonpolar capacitor C22 in parallel three-terminal adjustable regulator D27 of 2,3 ports; three-terminal adjustable regulator D27's port a connection optocoupler U11 2-port; one port of a termination resistor R57 optocoupler U12, the other end of the + 15V output ports; one end of the three-terminal adjustable resistor R58 D28 2-port regulator, the other end of the mark to FAULT_6 port, and connected with FAULT_6 port three-phase bridge inverter circuit modules; three-terminal adjustable regulator D28 port 3 ground; nonpolarized capacitors C23 three-terminal adjustable shunt regulator 2,3 D28 the port; three-terminal adjustable regulator D28 is a port to connect optocoupler U12 2-port; optocoupler U7, U8, U9, U10, U11 and U12 are grounded 3-port; optocoupler U7, U8, U9, U10 after four interconnected U11 and U12 port, port labeled Protect; and optocoupler U7, U8, U9, U10, U11 and U12 port after four interconnected levels pulled through a resistor R59 + 5V output port; resistance is provided between the R1 and R2 VoltageTest port; resistors R24, R25 are connected in series constitutes the voltage divider network, and is connected to the second port of the operational amplifier U3A; grounded at one end of the resistor R24 + 5V output port of a termination resistor R25 is; VoltageTest port after three port operational amplifier U3A resistor R26 is connected; an operational amplifier U3A port labeled as OVER_V port; one port, the other end of the resistor R29 a termination of the operational amplifier U3A + 5V output port; operational amplifier U3A 8-port connection ground 5V + 4-port output port of the operational amplifier U3A; resistors R30, R31 are connected in series constitutes the voltage divider network, and is connected to port 5 of the operational amplifier U3B; one end of the resistor R30 + 5V output port termination resistor R31 of the ground; port VoltageTest port 6 via a resistor R32 and is connected to the operational amplifier U3B; port 7 of the operational amplifier U3B is labeled LACK_V port; port 7 one end of the resistor R33 of the operational amplifier U3B, the other end of the + 5V output port; operational amplifier U3B 8-port connection + 4-port ground 5V output port, operational amplifiers U3B; said PWM wave generating circuit module connection is structured as follows: 4,8 U1 chip access port 555 + 5V output port, port 555 chip U1 is a grounded , 3-port labeled U1 555 chip for PWM port; 5 port Promise 555 chip capacitor C4 U1 one end and the other end is grounded; 7 port diode D20 cathode connected to the 555 chip U1, the negative pole 555 chip U1 2 and 6 port; one end of the resistor R23 + 5V output port, the other end of a sliding rheostat R22 port; 7 port sliding rheostat R22 555 2-port chip U1 is connected; sliding rheostat R22 end of three ports connected resistor R21; resistor R21 another negative termination of the diode D19; 2,6 diode D19 cathode connected to the port 555 of the chip U1; nonpolarized capacitors C3 positive one end of the diode D19, the other end; connection structure of the human-machine interface module are as follows: nonpolarized capacitors C5, C6 and C8 + 5V output after the parallel port connection; self-locking button S1-F / R 3 + 5V output port connected to the port, lock button S1-F / R 2-port resistor R27's end, since a port grounding lock button S1-F / R; the other end of the resistor R27 is marked as F / R port; nonpolarized capacitors C9 and C11 in parallel, the end of the ground, the other end of the man-machine interface module F / R port; 3-port self-locking button S2-STOP pick + end 5V output port, lock button S2-STOP 2-port resistor R28, and a port ground self-locking button S2-STOP; the other end of the resistor R28 is labeled STOP port ; nonpolar end of the capacitor C10 is grounded, and the other end STOP port; end of the resistor R38 is labeled OVER_C ports, one port 2 of the light-emitting diodes DS1 port grounding one end of another of the light emitting diode DS1; end of the resistor R39 is labeled F / R port, the other one end of a light-emitting diode DS2 port, 2-port ground emitting diode DS2's; end of the resistor R40 is marked as NOMAL port, in addition to a termination of a light-emitting diode DS3 port, light-emitting diodes 2 port DS3's ground; resistance R41 of end labeled OVER_V port, another port terminating a light-emitting diode, light emitting diodes 2 port of DS4 DS4 ground; the end of the resistor R42 is marked as LACK_VOUT port, a port, 2-port light-emitting diode DS5 grounded another termination of light-emitting diodes DS5 ; CPLD chip U5 3-port connection Protect port; CPLD chip U5 2-port connection PWM port; CPLD chip U5 of 1,44,25,37,36 port, respectively, then pick the man-machine interface module two F / R, STOP , LACK_VOUT, OVER_C, NOMAL port; CPLD chip U5 43,8 ports respectively connected OVER_V, LAVK_V port; 35,34,33,32,31,30 port CPLD chip U5 respectively connected U_Hin, U_Lin, V_Hin, V_Lin, W_Hin , W_Lin port; CPLD chip U5 rest of the port float.
A kind of implementation method of brushless direct current motor controller: comprise that rotor-position detects the judgement of output hall signal, the judgement of input PWM ripple, rotating judgement and the processing of metal-oxide-semiconductor logical drive signal, fault and brake signal judgement and according to the steps such as logic output pwm signal of load signal.
As the improvement to the implementation method of brushless direct current motor controller of the present invention: described step is as follows: the first step: the first initialization of system after start, refreshes LED show state; Second step: the Hall element of brshless DC motor provides the three-phase hall signal of rotor-position, and the PWM ripple that PWM ripple generative circuit module provides is input to CPLD chip U5; CPLD chip U5 makes corresponding judgement, and according to the rotating instruction in human-machine interface module 1, metal-oxide-semiconductor logical drive signal is processed; And fault-signal and the brake signal of input are judged, according to judged result, generate the pwm signal of driven MOS pipe, make the conducting of metal-oxide-semiconductor logic, finally realize brshless DC motor by instruction operation; The 3rd step: when judgement metal-oxide-semiconductor overcurrent, LED can light warning, and turn-off corresponding metal-oxide-semiconductor and burn out preventing; When bus overvoltage, under voltage fault and brake signal input, corresponding LED can light warning, and turn-offs pwm signal output, and all metal-oxide-semiconductors are turn-offed.
The beneficial effect that the present invention has is as follows:
1. the brushless direct current motor controller of the present invention design has low-voltage, high-current, open loop speed governing and lower-cost feature, is suitable for storage battery power supply, low-voltage, high-current drives and be not very high applications to speed stable state accuracy.
2 due to the controller design adopting based on CPLD chip, and it is higher than the controller cost performance based on dsp chip, and higher than the controller design flexibility based on proprietary integrated circuit (ASIC).
3. the current foldback circuit of controller adopts the internal resistance of inverter circuit metal-oxide-semiconductor to design; saved the high-accuracy sampling resistor of normal controller; not only cost is lower; and coordinate three terminal regulator and diode to carry out that design flexibility is higher, overcurrent protection response is faster, can effectively prevent that metal-oxide-semiconductor is because certain is former thereby overcurrent burns.
4. in controller, adopt the PWM ripple generative circuit of 555 chips and peripheral circuit structure, it obtains the PWM ripple with the corresponding duty ratio of rotating speed of target by regulator potentiometer, makes not have the CPLD chip of AD interface can identify this analog quantity of rotating speed of target.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Fig. 1 is overall structure block diagram of the present invention;
Fig. 2 is the circuit theory diagrams of CPLD of the present invention and peripheral circuit module 5 thereof;
Fig. 3 is the circuit theory diagrams of three-phase bridge inverter circuit module 7 of the present invention;
Fig. 4 is the circuit theory diagrams of drive circuit module 6 of the present invention;
Fig. 5 and Fig. 6 are the circuit theory diagrams of protective circuit module 4 of the present invention;
Fig. 7 is the circuit theory diagrams of power supply unit module 2 of the present invention;
Fig. 8 is the circuit theory diagrams of PWM ripple generative circuit module 3 of the present invention;
Fig. 9 is the motor positive and inverse of human-machine interface module 1 of the present invention and the circuit theory diagrams of brake control circuit;
Figure 10 is the circuit theory diagrams of the system mode display circuit of human-machine interface module 1 of the present invention;
Figure 11 is software realization flow figure of the present invention.
Embodiment
Embodiment 1, Fig. 1～Figure 10 have provided a kind of brushless direct current motor controller, comprise and brshless DC motor 8, CPLD and peripheral circuit module 5, three-phase bridge inverter circuit module 7, drive circuit module 6, protective circuit module 4, power supply module 2, human-machine interface module 1 and PWM ripple generative circuit module 3.
CPLD and peripheral circuit module 5 interconnect with brshless DC motor 8, by brshless DC motor 8, export three-phase hall signals to CPLD and peripheral circuit module 5, three-phase hall signal generates and drives signal in conjunction with control command, CPLD and peripheral circuit module 5 output to drive circuit module 6 by driving signal, by drive circuit module 6, will drive signal to generate actual effectively control signal, and again this control signal is outputed to three-phase bridge inverter circuit module 7, by three-phase bridge inverter circuit module 7, controlled the operation of brshless DC motor 8.
Above-described control command refers to the control signal that CPLD and peripheral circuit module 5 obtain from PWM ripple generative circuit module 3, human-machine interface module 1 and protective circuit module 4.Protective circuit module 4 detects three-phase bridge inverter circuit module 7 and drive circuit modules 6, when the electric current of three-phase bridge inverter circuit module 7 or drive circuit module 6 or voltage occur when abnormal, will send out control signal corresponding to CPLD and peripheral circuit module 5.PWM ripple generative circuit module 3 mainly comprises the Schmidt trigger circuit that 555 chips form, and Schmidt trigger circuit sends out control signal corresponding to CPLD and peripheral circuit module 5.Human-machine interface module 1 comprises motor positive and inverse and brake control circuit and system mode display circuit, by motor positive and inverse and brake control circuit, send out control signal corresponding to CPLD and peripheral circuit module 5, and by CPLD and the corresponding signal of peripheral circuit module 5 feedback to system mode display circuit.Power supply module 2 is transformed into 5V and 15V by the total voltage of 28V, and 5V or 15V voltage are transported in corresponding CPLD and peripheral circuit module 5, three-phase bridge inverter circuit module 7, drive circuit module 6, protective circuit module 4, human-machine interface module 1 and PWM ripple generative circuit module 3.
Below in conjunction with the circuit theory diagrams of each module, introducing in detail controller forms.
As shown in Figure 2, CPLD and peripheral circuit module 5 be by piece of CPLD chip U5,5 needle interface P1, and JTAG mouth P2, active crystal oscillator U6 and resistance R 34, R35, R36, R37, R44, R45 and R46 and capacitor C 15, C16 and C17 form.Above-described CPLD chip U5 can adopt for example M4A5-32/32-10VC chip of Lattice company, but is not limited to this.
Capacitor C 15, C16 and C17 be+filter capacitor of 5V power supply, and positive pole and the negative pole of be connected respectively to+5V power supply.16,38 connect+5V of the port power supplys (+5V positive source) of CPLD chip U5; 6,17,28, the 39 port ground connection of CPLD chip U5.40,41,42 ports of CPLD chip U5 are (as target motor, be the access interface of the three-phase hall signal output of brshless DC motor 8) connect respectively 2,3,4 ports of 5 needle interface P1, and these 3 ports are respectively by move on resistance R 44, R45, R46+5V power supply (+5V positive source); Connect+5V of the 1 port power supply (+5V positive source) of 5 needle interface P1, the 5 port ground connection of 5 needle interface P1.The TCK port of CPLD chip U5 is connected to 1 port of JTAG mouth P2; The TMS port of CPLD chip U5 is connected to 3 ports of JTAG mouth P2; The TDI port of CPLD chip U5 is connected to 5 ports of JTAG mouth P2; The TDO port of CPLD chip U5 is connected to 7 ports of JTAG mouth P2; 1 of JTAG mouth P2,3,5,7 move on resistance R 34, R35, R36 and R37 respectively+5V of port power supplys (+5V positive source) wherein; Connect+5V of the 6 ports power supply (+5V positive source) of JTAG mouth P2,4-and 8-port ground connection; All the other ports of JTAG mouth P2 are unsettled.3 ports of CPLD chip U5 connect the Protect port (Protect port is signal output part) of protective circuit 4.2 ports of CPLD chip U5 connect the PWM port (PWM port is signal output part) of PWM ripple generative circuit module 3.1 port of CPLD chip U5 connects two F/R ports of human-machine interface module 1, and (two F/R ports are included as the motor positive and inverse of human-machine interface module 1 and the F/R port in brake control circuit and the F/R port in system mode display circuit, and above-described two F/R ports also interconnect simultaneously, the level of controlling F/R by button changes, this F/R signal feeds back in CPLD chip U5 on the one hand, feeds back on the other hand diode DS2 and does state demonstration; F/R port is signal output part); 44 ports of CPLD chip U5 connect the STOP port (STOP port is signal output part) of human-machine interface module 1; 25 ports of CPLD chip U5 connect the LACK_VOUT port (LACK_VOUT port is signal input part) of human-machine interface module 1; 37 ports of CPLD chip U5 connect the OVER_C port (OVER_C port is signal input part) of human-machine interface module 1; 36 ports of CPLD chip U5 connect the NOMAL port (NOMAL port is signal input part) of human-machine interface module 1.43 ports of CPLD chip U5 connect the OVER_V port (OVER_V port is signal output part) of power supply module 2; 8 ports of CPLD chip U5 connect the LAVK_V port (LAVK_V port is signal output part) of power supply module 2.35 ports of CPLD chip U5 connect the U_Hin port (U_Hin port is signal output part) of drive circuit 6; 34 ports of CPLD chip U5 connect the U_Lin port (U_Lin port is signal output part) of drive circuit 6; 33 ports of CPLD chip U5 connect the V_Hin port (V_Hin port is signal output part) of drive circuit 6; 32 ports of CPLD chip U5 connect the V_Lin port (V_Lin port is signal output part) of drive circuit 6; 31 ports of CPLD chip U5 connect the W_Hin port (W_Hin port is signal output part) of drive circuit 6; 30 ports of CPLD chip U5 connect the W_Lin port (W_Lin port is signal output part) of drive circuit 6.5 ports of CPLD chip U5 are connected to 3 ports (3 ports of active crystal oscillator U6 are clock signal output) of source crystal oscillator U6, connect+5V of the 4 ports power supply (+5V positive source) of active crystal oscillator U6, the 2 port ground connection of active crystal oscillator U6,1 port of active crystal oscillator U6 is unsettled, and all the other ports of CPLD chip U5 are unsettled.
The course of work of described CPLD and peripheral circuit module 5 is as follows:
First input control signal I in CPLD chip U5, control signal I comprises inverter bridge metal-oxide-semiconductor overcurrent protection signal Protect (Protect port), is adjusted to the rotating speed of target signal PWM (PWM port) of PWM ripple, motor positive and inverse control signal F/R (F/R port), motor braking signal STOP (STOP port), general supply overvoltage signal OVER_V (OVER_V port) and general supply over-current signal LACK_V (LAVK_V port);
Then on the basis of control signal I, according to the three-phase hall signal (40,41,42 ports of CPLD chip U5) from 8 inputs of target brshless DC motor, generate the control signal II of corresponding each metal-oxide-semiconductor of inverter bridge, control signal II comprises U_Hin (U_Hin port), U_Lin (U_Lin port), V_Hin (V_Hin port), V_Lin (V_Lin port), W_Hin (W_Hin port) and W_Lin (W_Lin port) again;
Meanwhile, in said process, CPLD chip U5 also corresponding generation OVER_C (OVER_C port), NOMAL (NOMAL port) and LACK_VOUT (LACK_VOUT port) gives human-machine interface module 1.
Above-described JTAG mouth P2 is for downloading to CPLD chip U5.By source crystal oscillator U6, provide clock signal to CPLD chip U5.
As shown in Figure 3, three-phase bridge inverter circuit module 7 has adopted three phase full bridge structure, comprising P3 interface, N-channel MOS pipe Q1, Q1, Q1, Q1, Q1 and Q6, resistance R 1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19 and R20, capacitor C 1 and C2, diode D1, D2, D3, D4, D7, D8, D9, D10, D13, D14, D15 and D16, voltage stabilizing didoe D5, D6, D11, D12, D17 and D18.It is IRFP2907 that described metal-oxide-semiconductor adopts model, but is not limited to this.Wherein P3 interface is general supply interface, and 1 port of interface P3 connects positive source, and 2 ports of interface P3 connect power cathode, power acquisition use+28V power supply, but be not limited to this.
After two polar capacitor C1 and C2 parallel connection, receive in general supply, for preventing power-supply fluctuation; After two resistance R 1 and R2 series connection, receive in general supply, form potential-divider network, the sampled signal VoltageTest (being labeled as VoltageTest port) of output general supply voltage.Metal-oxide-semiconductor Q1 and Q2, Q3 and Q4 and Q5 and Q6 form respectively three brachium pontis of three phase full bridge; The source electrode output token of metal-oxide-semiconductor Q1 is VS1 port, and the source electrode output token of metal-oxide-semiconductor Q3 is VS2 port, and the source electrode output token of metal-oxide-semiconductor Q5 is VS3 port.
After two diode D1, D3 series aiding connection, negative pole connects metal-oxide-semiconductor Q1 drain electrode, and positive pole is labeled as FAULT_1 port; Resistance R 5 one termination metal-oxide-semiconductor Q1 grids, the other end is labeled as HO1 port; Voltage-stabiliser tube D5 negative pole connects metal-oxide-semiconductor Q1 grid, and positive pole connects metal-oxide-semiconductor Q1 source electrode; Resistance R 7 is connected in parallel on voltage-stabiliser tube D5; Between FAULT_1 port and HO1 port, with resistance R3, be connected.
After two diode D2, D4 series aiding connection, negative pole connects metal-oxide-semiconductor Q2 drain electrode, and positive pole is labeled as FAULT_2 port; Resistance R 6 one termination metal-oxide-semiconductor Q2 grids, the other end is labeled as LO1 port; Voltage-stabiliser tube D6 negative pole connects metal-oxide-semiconductor Q2 grid, and positive pole connects metal-oxide-semiconductor Q2 source electrode, and resistance R 8 is connected in parallel on voltage-stabiliser tube D6; Between FAULT_2 port and LO1 port, with resistance R4, be connected.
After two diode D7, D9 series aiding connection, negative pole connects metal-oxide-semiconductor Q3 drain electrode, and positive pole is labeled as FAULT_3 port; Resistance R 11 1 termination metal-oxide-semiconductor Q3 grids, the other end is labeled as HO2 port; Voltage-stabiliser tube D11 negative pole connects metal-oxide-semiconductor Q3 grid, and positive pole connects metal-oxide-semiconductor Q3 source electrode, and resistance R 13 is connected in parallel on voltage-stabiliser tube D11; Between FAULT_3 port and HO2 port, with resistance R9, be connected.
After two diode D8, D10 series aiding connection, negative pole connects metal-oxide-semiconductor Q4 drain electrode, and positive pole is labeled as FAULT_4 port; Resistance R 12 1 termination metal-oxide-semiconductor Q4 grids, the other end is labeled as LO2 port; Voltage-stabiliser tube D12 negative pole connects metal-oxide-semiconductor Q4 grid, and positive pole connects metal-oxide-semiconductor Q4 source electrode, and resistance R 14 is connected in parallel on voltage-stabiliser tube D12; Between FAULT_4 port and LO2 port, with resistance R10, be connected.
After two diode D13, D15 series aiding connection, negative pole connects metal-oxide-semiconductor Q5 drain electrode, and positive pole is labeled as FAULT_5 port; Resistance R 17 1 termination metal-oxide-semiconductor Q5 grids, the other end is labeled as HO3 port; Voltage-stabiliser tube D17 negative pole connects metal-oxide-semiconductor Q5 grid, and positive pole connects metal-oxide-semiconductor Q5 source electrode, and resistance R 19 is connected in parallel on voltage-stabiliser tube D17; Between FAULT_5 port and HO3 port, with resistance R15, be connected.
After two diode D14, D16 series aiding connection, negative pole connects metal-oxide-semiconductor Q6 drain electrode, and positive pole is labeled as FAULT_6 port; Resistance R 18 1 termination metal-oxide-semiconductor Q6 grids, the other end is labeled as LO3 port; Voltage-stabiliser tube D18 negative pole connects metal-oxide-semiconductor Q6 grid, and positive pole connects metal-oxide-semiconductor Q6 source electrode, and resistance R 20 is connected in parallel on voltage-stabiliser tube D17; Between FAULT_6 port and LO3 port, with resistance R16, be connected.
The course of work of described three-phase bridge inverter circuit module 7 is as follows:
When by voltage of HO1 port input being the driving signal of 15V left and right (the HO1 port output of drive circuit module 6), grid and the source voltage drop of metal-oxide-semiconductor Q1 are approximately 5V, make Q1 conducting, thereby VS1 port obtains 28V voltage; The grid source breakdown voltage V of metal-oxide-semiconductor Q1 gS=± 20V, due to the pressure stabilization function of voltage stabilizing didoe D5, therefore can prevent from damaging metal-oxide-semiconductor Q1 due to drive circuit fault or the environment static of metal-oxide-semiconductor Q1; Diode D1 wherein, D3 and resistance R 3 form the current sampling circuit of metal-oxide-semiconductor Q1, and D1 and D3, always in dead band, produce a dead band voltage, internal resistance generation conduction voltage drop during metal-oxide-semiconductor Q1 conducting, thus form together FAULT_1 voltage signal; When flowing through metal-oxide-semiconductor Q1 electric current and becoming large, FAULT_1 magnitude of voltage also can become greatly, when reaching certain value, can protect metal-oxide-semiconductor Q1 by trigger protection circuit.Operation principle and the metal-oxide-semiconductor Q1 of metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q5 and metal-oxide-semiconductor Q6 are in full accord.
As shown in Figure 4, drive circuit module 6 comprises integrated drive chips U13, U14 and U15, capacitor C 24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34 and C35, diode D29, D30, D31, D32, D33 and D34.Integrated drive chips U13 adopts IR1281 chip, but is not limited to this.
1 port label of integrated drive chips U13 is U_Hin port, 2 port label of integrated drive chips U13 are U_Lin port, 4 port label of integrated drive chips U13 are LO1 port (and being connected with the LO1 port of three-phase bridge inverter circuit module 7), 6 port label of integrated drive chips U13 are VS1 port (and being connected with the VS1 port of three-phase bridge inverter circuit module 7), 7 port label of integrated drive chips U13 are HO1 port (and being connected with the HO1 port of three-phase bridge inverter circuit module 7), and 8 port label of integrated drive chips U13 are V_HB1 port.The 3 port ground connection of integrated drive chips U13, connect+15V of the 5 ports positive source (+15V positive source) of integrated drive chips U13,6 and 8 ports of integrated drive chips U13 are two polarity free capacitor C24 in parallel and C27 directly; Diode D29 negative pole connects 6 ports of integrated drive chips U13, plus earth, and diode D32 negative pole connects the port 8 of integrated drive chips U13, connect+15V of positive pole positive source (+15V positive source).After polar capacitor C30 and polarity free capacitor C33 parallel connection on be connected on+15V power supply (+15V positive source).
1 port label of integrated drive chips U14 is V_Hin port, 2 port label of integrated drive chips U14 are V_Lin port, 4 port label of integrated drive chips U14 are LO2 port (and being connected with the LO2 port of three-phase bridge inverter circuit module 7), 6 port label of integrated drive chips U14 are VS2 port (and being connected with the VS2 port of three-phase bridge inverter circuit module 7), 7 port label of integrated drive chips U14 are HO2 port (and being connected with the HO2 port of three-phase bridge inverter circuit module 7), and 8 port label of integrated drive chips U14 are V_HB2 port.The 3 port ground connection of integrated drive chips U14, connect+15V of the 5 ports positive source (+15V positive source) of integrated drive chips U14,6 and 8 ports of integrated drive chips U14 are two polarity free capacitor C25 in parallel and C28 directly; Diode D30 negative pole connects 6 ports of integrated drive chips U14, plus earth; Diode D33 negative pole connects 8 ports of integrated drive chips U14, connect+15V of positive pole positive source (+15V positive source).After polar capacitor C31 and polarity free capacitor C34 parallel connection on be connected on+15V power supply (+15V positive source).
1 port label of integrated drive chips U15 is W_Hin port, 2 port label of integrated drive chips U15 are W_Lin port, 4 port label of integrated drive chips U15 are LO3 port (and being connected with the LO3 port of three-phase bridge inverter circuit module 7), 6 port label of integrated drive chips U15 are VS3 port (and being connected with the VS3 port of three-phase bridge inverter circuit module 7), 7 port label of integrated drive chips U15 are HO3 port (and being connected with the HO3 port of three-phase bridge inverter circuit module 7), and 8 port label of integrated drive chips U15 are V_HB3 port.The 3 port ground connection of integrated drive chips U15, connect+15V of the 5 ports positive source (+15V positive source) of integrated drive chips U15,6 and 8 these parts of port of integrated drive chips U15 are two polarity free capacitor C26 in parallel and C29 directly; Diode D31 negative pole connects 6 ports of integrated drive chips U15, plus earth; Diode D34 negative pole connects 8 ports of integrated drive chips U15, connect+15V of positive pole positive source (+15V positive source).After polar capacitor C32 and polarity free capacitor C35 parallel connection on be connected on+15V power supply (+15V positive source).
As shown in Figure 5 and Figure 6, protective circuit module 4 comprises metal-oxide-semiconductor current foldback circuit and busbar voltage over under-voltage protection circuit.
Fig. 5 is metal-oxide-semiconductor current foldback circuit (being comprised of metal-oxide-semiconductor On current testing circuit and light-coupled isolation protective circuit); comprise optocoupler U7, U8, U9, U10, U11 and U12; resistance R 47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58 and R59; capacitor C 18, C19, C20, C21, C22 and C23, the adjustable voltage-stabiliser tube D23 of three ends, D24, D25, D26, D27 and D28.It is TLP281 that optocoupler adopts model, and it is LM431 that the adjustable voltage-stabiliser tube of three ends adopts model, but is not limited to this.
1 port of one termination optocoupler U7 of resistance R 47, the other end is labeled as V_HB1 port (and being connected with the V_HB1 port of drive circuit module 6); 2 ports of the adjustable voltage-stabiliser tube D23 of one termination three end of resistance R 48, the other end is labeled as FAULT_1 port (and being connected with the FAULT_1 port of three-phase bridge inverter circuit module 7); 3 ports of the adjustable voltage-stabiliser tube D23 of three ends are connected with the VS1 port of three-phase bridge inverter circuit module 7; Polarity free capacitor C18 is connected in parallel on the port 2,3 of the adjustable voltage-stabiliser tube D23 of three ends; 1 port of the adjustable voltage-stabiliser tube D23 of three ends connects 2 ports of optocoupler U7.
1 port of one termination optocoupler U8 of resistance R 49, another termination+15V power supply (+15V positive source); 2 ports of the adjustable voltage-stabiliser tube D24 of one termination three end of resistance R 50, the other end is labeled as FAULT_2 port (and being connected with the FAULT_2 port of three-phase bridge inverter circuit module 7); The 3 port ground connection of the adjustable voltage-stabiliser tube D24 of three ends; Polarity free capacitor C19 is connected in parallel on the port 2,3 of the adjustable voltage-stabiliser tube D24 of three ends; 1 port of the adjustable voltage-stabiliser tube D24 of three ends connects 2 ports of optocoupler U8.
1 port of one termination optocoupler U9 of resistance R 51, the other end is labeled as V_HB2 port (and being connected with the V_HB2 port of drive circuit module 6); 2 ports of the adjustable voltage-stabiliser tube D25 of one termination three end of resistance R 52, the other end is labeled as FAULT_3 port (and being connected with the FAULT_3 port of three-phase bridge inverter circuit module 7); 3 ports of the adjustable voltage-stabiliser tube D25 of three ends are connected with the VS2 port of three-phase bridge inverter circuit module 7; Polarity free capacitor C20 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D25 of three ends; 1 port of the adjustable voltage-stabiliser tube D25 of three ends connects 2 ports of optocoupler U9.
1 port of one termination optocoupler U10 of resistance R 53, another termination+15V power supply (+15V positive source); 2 ports of the adjustable voltage-stabiliser tube D26 of one termination three end of resistance R 54, the other end is labeled as FAULT_4 port (and being connected with the FAULT_4 port of three-phase bridge inverter circuit module 7); The 3 port ground connection of the adjustable voltage-stabiliser tube D26 of three ends; Polarity free capacitor C21 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D26 of three ends; 1 port of the adjustable voltage-stabiliser tube D27 of three ends connects 2 ports of optocoupler U10.
1 port of one termination optocoupler U11 of resistance R 55, the other end is labeled as V_HB3 port (and being connected with the V_HB3 port of drive circuit module 6); 2 ports of the adjustable voltage-stabiliser tube D27 of one termination three end of resistance R 56, the other end is labeled as FAULT_5 port (and being connected with the FAULT_5 port of three-phase bridge inverter circuit module 7); 3 ports of the adjustable voltage-stabiliser tube D27 of three ends are connected with the VS3 port of three-phase bridge inverter circuit module 7; Polarity free capacitor C22 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D27 of three ends; The port one of the adjustable voltage-stabiliser tube D27 of three ends connects 2 ports of optocoupler U11.
1 port of one termination optocoupler U12 of resistance R 57, another termination+15V power supply; 2 ports of the adjustable voltage-stabiliser tube D28 of one termination three end of resistance R 58, the other end is labeled as FAULT_6 port (and being connected with the FAULT_6 port of three-phase bridge inverter circuit module 7); Port 3 ground connection of the adjustable voltage-stabiliser tube D28 of three ends; Polarity free capacitor C23 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D28 of three ends; 1 port of the adjustable voltage-stabiliser tube D28 of three ends connects 2 ports of optocoupler U12.
3 ports of optocoupler U7, U8, U9, U10, U11 and U12 are ground connection all, and port 4 all links together, and is labeled as port Protect, and these port 4 level are by move in resistance R 59+5V.
If Fig. 6 is bus overvoltage and under voltage protection circuit (bus is owed overvoltage detection sub-module, detects general supply voltage and whether is less than or greater than certain value, and trigger corresponding control signal by operational amplifier); Comprise operational amplifier U3 (operational amplifier U3 comprises U3A and U3B), resistance R 24, R25, R26, R29, R30, R31, R32 and R33.Described operational amplifier adopts LM358 dual operational amplifier, but is not limited to this.
Resistance R 24, R25 form potential-divider network, and the voltage signal obtaining are passed to 2 ports (resistance R 24 one end by+5V positive source obtain voltage signal) of operational amplifier U3A; From the VoltageTest signal (from the output of VoltageTest port) of three-phase bridge inverter circuit module 7, after resistance R 26, pass to 3 ports of operational amplifier U3A.1 port of operational amplifier U3A is labeled as OVER_V port as overvoltage control signal output.1 port of resistance R 29 1 termination operational amplifier U3A, another termination+5V power supply (+5V positive source); Connect+5V of the 8 ports power supply (+5V positive source) of operational amplifier U3A, the 4 port ground connection of operational amplifier U3A.
Resistance R 30, R31 form potential-divider network, and the voltage signal obtaining are passed to 5 ports (resistance R 30 one end by+5V positive source obtain voltage signal) of operational amplifier U3B; From the VoltageTest signal (from the output of VoltageTest port) of three-phase bridge inverter circuit module 7, after resistance R 32, pass to the port 6 of operational amplifier U3B.The port 7 of operational amplifier U3B is labeled as LACK_V port as under-voltage control signal output.7 ports of resistance R 33 1 termination operational amplifier U3B, another termination+5V power supply (+5V positive source); Connect+5V of the 8 ports power supply (+5V positive source) of operational amplifier U3B, the 4 port ground connection of operational amplifier U3B.
The metal-oxide-semiconductor current foldback circuit course of work of described protective circuit module 4 is as follows:
Metal-oxide-semiconductor (metal-oxide-semiconductor Q1-Q6) is crossed to fail to be convened for lack of a quorum and is shown that (wherein N is 1-6 to FAULT_N; correspond to metal-oxide-semiconductor Q1-Q6) on the voltage of signal; when FAULT_N signal reaches set point; can trigger the adjustable voltage-stabiliser tube of three ends (the adjustable voltage-stabiliser tube D23-D28 of three ends; corresponding to metal-oxide-semiconductor Q1-Q6) conducting; thereby make optocoupler (optocoupler U7-U12) conducting; and produce 3 ports that Protect signal is transferred to CPLD chip U5, finally turn-off metal-oxide-semiconductor (metal-oxide-semiconductor Q1-Q6) and form protection.
As shown in Figure 7, power supply module 2+5V and+15V power supply generates submodule, adopted be respectively output as+5V and+the integrated switch voltage stabilizing chip of these two kinds of voltages of 15V constructs this two power supply submodules, it comprises power supply chip U2, U4, polar capacitor C7, C12, C13 and C14, diode D21 and D22, inductance L 1 and L2.Power supply chip U2, U4 can adopt respectively LM2575-15 and LM2575-5.0 chip, but are not limited to this.
1 port of power supply chip U2 meets general supply+28V, the 3 and 5 port ground connection of power supply chip U2; Wherein the positive pole of polar capacitor C7 connects 1 port of power supply chip U2, minus earth; The port 2 of power inductance L1 mono-termination power supply chip U2, the output of other end conduct+15V power supply, and this port of mark is+15V positive source.Connect+15V of the positive pole of polar capacitor C12 positive source, minus earth; The negative pole of Schottky diode D21 connects 2 ports of power supply chip U2, plus earth, and 4 ports of power supply chip U2 are unsettled.
1 port of power supply chip U4 meets general supply+28V, the 3 and 5 port ground connection of power supply chip U4; Wherein the positive pole of polar capacitor C13 connects 1 port of power supply chip U4, minus earth; The port 2 of power inductance L2 mono-termination power supply chip U4, the output of other end conduct+5V power supply, and this port of mark is+5V positive source.Connect+5V of the positive pole of polar capacitor C14 positive source, minus earth; The negative pole of Schottky diode D22 connects 2 ports of power supply chip U4, plus earth, and 4 ports of power supply chip U4 are unsettled.
As shown in Figure 8, PWM ripple generative circuit module 3 comprises 555 chip U1, resistance R 21, R23, slide rheostat R22, capacitor C 3 and C4, diode D19 and D20.
Connect+5V of the 4-and 8-port of 555 chip U1 positive source (by+5V positive source input power), the 1 port ground connection of 555 chip U1,3 ports of 555 chip U1, as PWM wave output terminal mouth, are labeled as PWM port (joining with 2 ports of CPLD chip U5); 5 ports of polarity free capacitor C4 mono-termination 555 chip U1, other end ground connection; The positive pole of diode D20 connects 7 ports of 555 chip U1, and negative pole connects 2 and 6 ports of 555 chip U1; One termination of resistance R 23+5V power supply, 1 port of another termination slide rheostat R22; 2 ports of slide rheostat R22 connect 7 ports of 555 chip U1; One end of the 3 port connecting resistance R21 of slide rheostat R22; The negative pole of another terminating diode D19 of resistance R 21.The positive pole of diode D19 connects 2 and 6 ports of 555 chip U1.The positive pole of a terminating diode D19 of polarity free capacitor C3, other end ground connection.
The course of work of described PWM ripple generative circuit module 3 is as follows:
From the structure of 555 chips, it forms a Schmidt trigger; Voltage-transfer characteristic by Schmidt trigger is known, the substantially proportional routine relationship change of angle that the PWM ripple duty ratio of output and linear potentiometer R22 (being slide rheostat R22) turn over.Because tach signal is an analog quantity, generally need to be converted into corresponding analog voltage signal, and adopt AD chip that signal is passed to control core; And adopt the form of PWM ripple that rotating speed of target signal is passed on to CPLD chip U5, and just can directly realize the stepless time adjustment of brshless DC motor, avoided controller to take AD chip, thus cost-saving.
As shown in Figure 9, be motor positive and inverse and the brake control circuit of human-machine interface module 1; Comprise self-locking button S1-F/R and S2-STOP, polarity free capacitor C5, C6, C8, C9, C10 and C11, resistance R 27 and R28.
After polarity free capacitor C5, C6 and C8 parallel connection, be connected on+5V power supply (+5V positive source) is upper, for filter out power noise; Connect+5V of the 3 ports power supply (+5V positive source) of self-locking button S1-F/R, one end of the 2 port connecting resistance R27 of self-locking button S1-F/R, the 1 port ground connection of self-locking button S1-F/R; The other end of resistance R 27, as rotating control signal output, is labeled as F/R port; After polarity free capacitor C9 and C11 parallel connection, one end ground connection, another termination F/R port, the noise in output signal producing for filtering button; Connect+5V of the 3 ports power supply (+5V positive source) of self-locking button S2-STOP, one end of the 2 port connecting resistance R28 of self-locking button S2-STOP, the 1 port ground connection of self-locking button S2-STOP; The other end of resistance R 28, as brake control signal output, is labeled as STOP port; Polarity free capacitor C10 one end ground connection, another termination STOP port, the noise in output signal producing for filtering button.
The step realizing is as follows:
When 3 ports of self-locking button S1-F/R are connected with 2 ports of self-locking button S1-F/R, output F/R signal;
When 1 port of self-locking button S1-F/R is connected with 2 ports of self-locking button S1-F/R, non-output signal;
When 3 ports of self-locking button S2-STOP are connected with 2 ports of self-locking button S2-STOP, output STOP signal;
When 1 port of self-locking button S2-STOP is connected with 2 ports of self-locking button S2-STOP, non-output signal.
As shown in figure 10, be the system mode display circuit of human-machine interface module 1; Comprise resistance R 38, R39, R40, R41 and R42, light-emitting diode DS1, DS2, DS3, DS4 and DS5.One end of resistance R 38 is labeled as OVER_C port, 1 port of one end sending and receiving optical diode DS1 in addition, the 2 port ground connection of light-emitting diode DS1; One end of resistance R 39 is labeled as F/R port, 1 port of one end sending and receiving optical diode DS2 in addition, the 2 port ground connection of light-emitting diode DS2; One end of resistance R 40 is labeled as NOMAL port, 1 port of one end sending and receiving optical diode DS3 in addition, the 2 port ground connection of light-emitting diode DS3; One end of resistance R 41 is labeled as OVER_V port, 1 port of one end sending and receiving optical diode DS4 in addition, the 2 port ground connection of light-emitting diode DS4; One end of resistance R 42 is labeled as LACK_VOUT port, 1 port of one end sending and receiving optical diode DS5 in addition, the 2 port ground connection of light-emitting diode DS5; OVER_C signal from CPLD chip U5 passes to light-emitting diode DS1 positive pole, the minus earth of light-emitting diode DS1 through resistance R 38 (that is, the OVER_C port of resistance R 38 one end is connected with 37 ports of CPLD chip U5); F/R signal from motor positive and inverse and brake control circuit passes to light-emitting diode DS2 positive pole, the minus earth of light-emitting diode DS2 through resistance R 39 (that is, the F/R port of resistance R 39 one end is connected with 1 port of CPLD chip U5).NOMAL signal from CPLD chip U5 passes to light-emitting diode DS3 positive pole, the minus earth of light-emitting diode DS3 through resistance R 40 (that is, the NOMAL port of resistance R 40 one end is connected with 36 ports of CPLD chip U5).Come the OVER_V signal of self-protection circuit's module 4 to pass to light-emitting diode DS4 positive pole, the minus earth of light-emitting diode DS4 through resistance R 41 (that is, the OVER_V port of resistance R 41 one end is connected with 43 ports of CPLD chip U5).From CPLD chip U5 LACK_VOUT signal through resistance R 42 (that is, the LACK_VOUT port of resistance R 42 one end is connected with 25 ports of CPLD chip U5), to pass to light-emitting diode DS5 anodal, the minus earth of light-emitting diode DS5.
Real work step of the present invention as shown in figure 11, comprise that rotor-position detects the judgement of output hall signal, the judgement of input PWM ripple, rotating judgement and the processing of metal-oxide-semiconductor logical drive signal, fault and brake signal judgement and according to the logic output pwm signal of load signal, actual step is as follows:
The first step: the first initialization of system after start, refreshes LED show state;
Second step: the Hall element of brshless DC motor 8 provides the three-phase hall signal of rotor-position, and the PWM ripple that PWM ripple generative circuit module 3 provides is input to CPLD chip U5; CPLD chip U5 makes corresponding judgement, and according to the rotating instruction in human-machine interface module 1 (that is, motor positive and inverse control signal F/R), metal-oxide-semiconductor logical drive signal (metal-oxide-semiconductor logical drive signal now refers to from the signal of the pwm signal input of CPLD chip U5) is processed; And (metal-oxide-semiconductor overcurrent, bus overvoltage or bus are under-voltage to the fault-signal of input;; inverter bridge metal-oxide-semiconductor overcurrent protection signal Protect) and brake signal (output of STOP port) judge; according to judged result, generate the pwm signal (U_Hin, U_Lin, V_Hin, V_Lin, W_Hin and W_Lin) of driven MOS pipe; make the conducting of metal-oxide-semiconductor logic, finally realize brshless DC motor by instruction operation.
The 3rd step: when judgement metal-oxide-semiconductor overcurrent, LED can light warning, and turn-off corresponding metal-oxide-semiconductor and burn out preventing; When bus overvoltage, under voltage fault and brake signal input, corresponding LED can light warning, and turn-offs pwm signal output, and all metal-oxide-semiconductors are turn-offed.
Finally, it is also to be noted that, what more than enumerate is only a specific embodiment of the present invention.Obviously, the invention is not restricted to above embodiment, can also have many distortion.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention, all should think protection scope of the present invention.

Claims (6)

1. brushless direct current motor controller, comprises brshless DC motor (8), CPLD and peripheral circuit module (5), three-phase bridge inverter circuit module (7), drive circuit module (6), protective circuit module (4), power supply module (2), human-machine interface module (1) and PWM ripple generative circuit module (3); It is characterized in that: described CPLD and peripheral circuit module (5) receive respectively the control command that human-machine interface module (1), PWM ripple generative circuit module (3) and protective circuit module (4) are sent, and after the three-phase hall signal that sends of brshless DC motor (8), produce and drive signal;
Drive circuit module (6) receives the driving signal of CPLD and peripheral circuit module (5), and will drive signal to generate control signal;
Three-phase bridge inverter circuit module (7) receives the control signal of drive circuit module (6), and controls the operation of brshless DC motor (8);
Protective circuit module (4) detects three-phase bridge inverter circuit module (7) and drive circuit module (6), and testing result is fed back to CPLD and peripheral circuit module (5) with the form of control command;
Described power supply module (2) is transformed into 5V and 15V by 28V total voltage, and 5V or 15V voltage are transported in corresponding CPLD and peripheral circuit module (5), three-phase bridge inverter circuit module (7), drive circuit module (6), protective circuit module (4), human-machine interface module (1) and PWM ripple generative circuit module (3).
2. brushless direct current motor controller according to claim 1, it is characterized in that: described PWM ripple generative circuit module (3) comprises the Schmidt trigger circuit that 555 chips form, and this Schmidt trigger circuit sends corresponding control command to CPLD and peripheral circuit module (5).
3. brushless direct current motor controller according to claim 2, it is characterized in that: described human-machine interface module (1) comprises motor positive and inverse and brake control circuit and system mode display circuit, motor positive and inverse and brake control circuit send corresponding control command to CPLD and peripheral circuit module (5);
Described CPLD and peripheral circuit module (5) are fed back corresponding signal to system mode display circuit.
4. brushless direct current motor controller according to claim 3, is characterized in that: described CPLD and peripheral circuit module (5) are comprised of CPLD chip U5,5 needle interface P1, JTAG mouth P2, active crystal oscillator U6, resistance R 34, R35, R36, R37, R44, R45, R46 and capacitor C 15, C16, C17;
Described drive circuit module (6) is by integrated drive chips U13, U14, U15, capacitor C 24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, and diode D29, D30, D31, D32, D33, D34 form;
Described three-phase bridge inverter circuit module (7) adopts three phase full bridge structure, by P3 interface, N-channel MOS pipe Q1, Q1, Q1, Q1, Q1, Q6, resistance R 1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, capacitor C 1, C2, diode D1, D2, D3, D4, D7, D8, D9, D10, D13, D14, D15, D16, voltage stabilizing didoe D5, D6, D11, D12, D17, D18 form;
Described protective circuit module (4) comprises metal-oxide-semiconductor current foldback circuit and busbar voltage over under-voltage protection circuit; Described metal-oxide-semiconductor current foldback circuit is by optocoupler U7, U8, U9, U10, U11, U12, resistance R 47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, capacitor C 18, C19, C20, C21, C22, C23, the adjustable voltage-stabiliser tube D23 of three ends, D24, D25, D26, D27, D28 form; Described busbar voltage over under-voltage protection circuit is by operational amplifier U3A, U3B, and resistance R 24, R25, R26, R29, R30, R31, R32, R33 form;
Described PWM ripple generative circuit module (3) is by 555 chip U1, resistance R 21, R23, and slide rheostat R22, capacitor C 3, C4, diode D19, D20 form;
Described human-machine interface module (1) comprises motor positive and inverse and brake control circuit and system mode display circuit; Described motor positive and inverse and brake control circuit are by self-locking button S1-F/R, S2-STOP, polarity free capacitor C5, C6, C8, C9, C10, C11, resistance R 27, R28; Described system mode display circuit comprises resistance R 38, R39, R40, R41 and R42, and light-emitting diode DS1, DS2, DS3, DS4 and DS5 form;
Comprise+15V of power supply module (2) output port and+5V output port, by power supply chip U2, U4, polar capacitor C7, C12, C13, C14, diode D21, D22, inductance L 1, L2 form;
The syndeton of described power supply module (2) is as follows:
1 port of described power supply chip U2 is general supply port; 3, the 5 port ground connection of power supply chip U2; The positive pole of polar capacitor C7 connects 1 port of power supply chip U2, negative pole; 2 ports of power inductance L1 mono-termination power supply chip U2, other end conduct+15V output port; Connect+15V of the positive pole of polar capacitor C12 output port, minus earth; The negative pole of Schottky diode D21 connects 2 ports of power supply chip U2, plus earth, and 4 ports of power supply chip U2 are unsettled;
1 port of described power supply chip U4 is general supply port; 3 and the 5 port ground connection of power supply chip U4; The positive pole of polar capacitor C13 connects 1 port of power supply chip U4, minus earth; The port 2 of power inductance L2 mono-termination power supply chip U4, other end conduct+5V output port; Connect+5V of the positive pole of polar capacitor C14 output port, minus earth; The negative pole of Schottky diode D22 connects 2 ports of power supply chip U4, plus earth, and 4 ports of power supply chip U4 are unsettled;
The syndeton of described CPLD and peripheral circuit module (5) is as follows:
Positive pole and the negative pole of described capacitor C 15, C16 and be connected respectively to+5V of C17 output port; 16,38 connect+5V of the port output ports of CPLD chip U5; 6,17,28, the 39 port ground connection of CPLD chip U5; 40,41,42 ports of CPLD chip U5 connect respectively 2,3,4 ports of 5 needle interface P1, and 2,3,4 ports of 5 needle interface P1 are respectively by move on resistance R 44, R45, R46+5V output port; Connect+5V of the 1 port output port of 5 needle interface P1, the 5 port ground connection of 5 needle interface P1; 7 ports of CPLD chip U5 are connected to 1 port of JTAG mouth P2, and 26 ports of CPLD chip U5 are connected to 3 ports of JTAG mouth P2; 4 ports of CPLD chip U5 are connected to 5 ports of JTAG mouth P2; 29 ports of CPLD chip U5 are connected to 7 ports of JTAG mouth P2; 1,3,5,7 move on resistance R 34, R35, R36 and R37 respectively+5V of the port output ports of described JTAG mouth P2; Connect+5V of the 6 ports output port of JTAG mouth P2,4,8 port ground connection; All the other ports of JTAG mouth P2 are unsettled; 5 ports of CPLD chip U5 are connected to 3 ports of source crystal oscillator U6, connect+5V of the 4 ports output port of active crystal oscillator U6, and the 2 port ground connection of active crystal oscillator U6,1 port of active crystal oscillator U6 is unsettled;
The syndeton of described drive circuit module (6) is as follows:
1 port label of integrated drive chips U13 is U_Hin port, and is connected with 35 ports of CPLD chip U5; 2 port label of integrated drive chips U13 are U_Lin port, and are connected with 34 ports of CPLD chip U5; 4 port label of integrated drive chips U13 are LO1 port; 6 port label of integrated drive chips U13 are VS1 port; 7 port label of integrated drive chips U13 are HO1 port; 8 port label of integrated drive chips U13 are V_HB1 port; The 3 port ground connection of integrated drive chips U13; Connect+15V of the 5 ports positive source of integrated drive chips U13; 6 and 8 ports of integrated drive chips U13 are two polarity free capacitor C24 in parallel and C27 directly; Diode D29 negative pole connects 6 ports of integrated drive chips U13, plus earth; Diode D32 negative pole connects 8 ports of integrated drive chips U13, connect+15V of positive pole positive source; After polar capacitor C30 and polarity free capacitor C33 parallel connection on be connected on+15V power supply;
1 port label of integrated drive chips U14 is V_Hin port, and is connected with 33 ports of CPLD chip U5; 2 port label of integrated drive chips U14 are V_Lin port, and are connected with 32 ports of CPLD chip U5; 4 port label of integrated drive chips U14 are LO2 port; 6 port label of integrated drive chips U14 are VS2 port; 7 port label of integrated drive chips U14 are HO2 port; 8 port label of integrated drive chips U14 are V_HB2 port; The 3 port ground connection of integrated drive chips U14; Connect+15V of the 5 ports positive source of integrated drive chips U14; 6 and 8 ports of integrated drive chips U14 are two polarity free capacitor C25 in parallel and C28 directly; Diode D30 negative pole connects 6 ports of integrated drive chips U14, plus earth; Diode D33 negative pole connects 8 ports of integrated drive chips U14, connect+15V of positive pole positive source; After polar capacitor C31 and polarity free capacitor C34 parallel connection on be connected on+15V power supply;
1 port label of integrated drive chips U15 is W_Hin port, and is connected with 31 ports of CPLD chip U5; 2 port label of integrated drive chips U15 are W_Lin port, and are connected with 30 ports of CPLD chip U5; 4 port label of integrated drive chips U15 are LO3 port; 6 port label of integrated drive chips U15 are VS3 port; 7 port label of integrated drive chips U15 are HO3 port; 8 port label of integrated drive chips U15 are V_HB3 port; The 3 port ground connection of integrated drive chips U15; Connect+15V of the 5 ports positive source of integrated drive chips U15; 6 and 8 ports of integrated drive chips U15 are two polarity free capacitor C26 in parallel and C29 directly; Diode D31 negative pole connects 6 ports of integrated drive chips U15, plus earth; Diode D34 negative pole connects 8 ports of integrated drive chips U15, connect+15V of positive pole positive source; After polar capacitor C32 and polarity free capacitor C35 parallel connection on be connected on+15V power supply;
The syndeton of described three-phase bridge inverter circuit module (7) is as follows:
1 port of described interface P3 connects general supply positive pole, and 2 ports of interface P3 connect general supply negative pole; After polar capacitor C1 and C2 parallel connection, receive in general supply; After two resistance R 1 and R2 series connection, receive in general supply; Metal-oxide-semiconductor Q1 and Q2, Q3 and Q4 and Q5 and Q6 form respectively three brachium pontis of three phase full bridge; The source electrode output token of metal-oxide-semiconductor Q1 is VS1 port, and is connected with the VS1 port of integrated drive chips U13; The source electrode output token of metal-oxide-semiconductor Q3 is VS2 port, and is connected with the VS2 port of integrated drive chips U14; The source electrode output token of metal-oxide-semiconductor Q5 is VS3 port, and is connected with the VS3 port of integrated drive chips U15;
After two diode D1, D3 series aiding connection, negative pole connects metal-oxide-semiconductor Q1 drain electrode, and positive pole is labeled as FAULT_1 port; Resistance R 5 one termination metal-oxide-semiconductor Q1 grids, the other end is labeled as HO1 port, and is connected with the HO1 port of integrated drive chips U13; Voltage-stabiliser tube D5 negative pole connects metal-oxide-semiconductor Q1 grid, and positive pole connects metal-oxide-semiconductor Q1 source electrode; Resistance R 7 is connected in parallel on voltage-stabiliser tube D5; Between the HO1 port of the FAULT_1 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R3, be connected;
After two diode D2, D4 series aiding connection, negative pole connects metal-oxide-semiconductor Q2 drain electrode, and positive pole is labeled as FAULT_2 port; Resistance R 6 one termination metal-oxide-semiconductor Q2 grids, the other end is labeled as LO1 port, and is connected with the LO1 port of integrated drive chips U13; Voltage-stabiliser tube D6 negative pole connects metal-oxide-semiconductor Q2 grid, and positive pole connects metal-oxide-semiconductor Q2 source electrode, and resistance R 8 is connected in parallel on voltage-stabiliser tube D6; Between the LO1 port of the FAULT_2 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R4, be connected;
After two diode D7, D9 series aiding connection, negative pole connects metal-oxide-semiconductor Q3 drain electrode, and positive pole is labeled as FAULT_3 port; Resistance R 11 1 termination metal-oxide-semiconductor Q3 grids, the other end is labeled as HO2 port, and is connected with the HO2 port of integrated drive chips U14; Voltage-stabiliser tube D11 negative pole connects metal-oxide-semiconductor Q3 grid, and positive pole connects metal-oxide-semiconductor Q3 source electrode, and resistance R 13 is connected in parallel on voltage-stabiliser tube D11; Between the HO2 port of the FAULT_3 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R9, be connected;
After two diode D8, D10 series aiding connection, negative pole connects metal-oxide-semiconductor Q4 drain electrode, and positive pole is labeled as FAULT_4 port; Resistance R 12 1 termination metal-oxide-semiconductor Q4 grids, the other end is labeled as LO2 port, and is connected with the LO2 port of integrated drive chips U14; Voltage-stabiliser tube D12 negative pole connects metal-oxide-semiconductor Q4 grid, and positive pole connects metal-oxide-semiconductor Q4 source electrode, and resistance R 14 is connected in parallel on voltage-stabiliser tube D12; Between the LO2 port of the FAULT_4 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R10, be connected;
After two diode D13, D15 series aiding connection, negative pole connects metal-oxide-semiconductor Q5 drain electrode, and positive pole is labeled as FAULT_5 port; Resistance R 17 1 termination metal-oxide-semiconductor Q5 grids, the other end is labeled as HO3 port, and is connected with the HO3 port of integrated drive chips U15; Voltage-stabiliser tube D17 negative pole connects metal-oxide-semiconductor Q5 grid, and positive pole connects metal-oxide-semiconductor Q5 source electrode, and resistance R 19 is connected in parallel on voltage-stabiliser tube D17; Between the HO3 port of the FAULT_5 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R15, be connected;
After two diode D14, D16 series aiding connection, negative pole connects metal-oxide-semiconductor Q6 drain electrode, and positive pole is labeled as FAULT_6 port; Resistance R 18 1 termination metal-oxide-semiconductor Q6 grids, the other end is labeled as LO3 port, and is connected with the LO3 port of integrated drive chips U15; Voltage-stabiliser tube D18 negative pole connects metal-oxide-semiconductor Q6 grid, and positive pole connects metal-oxide-semiconductor Q6 source electrode, and resistance R 20 is connected in parallel on voltage-stabiliser tube D17; Between the LO3 port of the FAULT_6 port of three-phase bridge inverter circuit module (7) and three-phase bridge inverter circuit module (7), with resistance R16, be connected;
The syndeton of described protective circuit module (4) is as follows:
1 port of one termination optocoupler U7 of resistance R 47, the other end is labeled as V_HB1 port, and is connected with the V_HB1 port of integrated drive chips U13; 2 ports of the adjustable voltage-stabiliser tube D23 of one termination three end of resistance R 48, the other end is labeled as FAULT_1 port, and is connected with the FAULT_1 port of three-phase bridge inverter circuit module (7); 3 port label of the adjustable voltage-stabiliser tube D23 of three ends are VS1 port, and are connected with the VS1 port of three-phase bridge inverter circuit module (7); Polarity free capacitor C18 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D23 of three ends; 1 port of the adjustable voltage-stabiliser tube D23 of three ends connects 2 ports of optocoupler U7;
1 port of one termination optocoupler U8 of resistance R 49, another termination+15V output port; 2 ports of the adjustable voltage-stabiliser tube D24 of one termination three end of resistance R 50, the other end is labeled as FAULT_2 port, and is connected with the FAULT_2 port of three-phase bridge inverter circuit module (7); The 3 port ground connection of the adjustable voltage-stabiliser tube D24 of three ends; Polarity free capacitor C19 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D24 of three ends; 1 port of the adjustable voltage-stabiliser tube D24 of three ends connects 2 ports of optocoupler U8;
1 port of one termination optocoupler U9 of resistance R 51, the other end is labeled as V_HB2 port, and is connected with the V_HB2 port of integrated drive chips U14; 2 ports of the adjustable voltage-stabiliser tube D25 of one termination three end of resistance R 52, the other end is labeled as FAULT_3 port, and is connected with the FAULT_3 port of three-phase bridge inverter circuit module (7); 3 port label of the adjustable voltage-stabiliser tube D25 of three ends are VS2 port, and are connected with the VS2 port of three-phase bridge inverter circuit module (7); Polarity free capacitor C20 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D25 of three ends; 1 port of the adjustable voltage-stabiliser tube D25 of three ends connects 2 ports of optocoupler U9;
1 port of one termination optocoupler U10 of resistance R 53, another termination+15V output port; 2 ports of the adjustable voltage-stabiliser tube D26 of one termination three end of resistance R 54, the other end is labeled as FAULT_4 port, and is connected with the FAULT_4 port of three-phase bridge inverter circuit module (7); The 3 port ground connection of the adjustable voltage-stabiliser tube D26 of three ends; Polarity free capacitor C21 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D26 of three ends; 1 port of the adjustable voltage-stabiliser tube D27 of three ends connects 2 ports of optocoupler U10;
1 port of one termination optocoupler U11 of resistance R 55, the other end is labeled as V_HB3 port, and is connected with the V_HB3 port of integrated drive chips U15; 2 ports of the adjustable voltage-stabiliser tube D27 of one termination three end of resistance R 56, the other end is labeled as FAULT_5 port, and is connected with the FAULT_5 port of three-phase bridge inverter circuit module (7); 3 port label of the adjustable voltage-stabiliser tube D27 of three ends are VS3 port, and are connected with the VS3 port of three-phase bridge inverter circuit module (7); Polarity free capacitor C22 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D27 of three ends; The port one of the adjustable voltage-stabiliser tube D27 of three ends connects 2 ports of optocoupler U11;
1 port of one termination optocoupler U12 of resistance R 57, another termination+15V output port; 2 ports of the adjustable voltage-stabiliser tube D28 of one termination three end of resistance R 58, the other end is labeled as FAULT_6 port, and is connected with the FAULT_6 port of three-phase bridge inverter circuit module (7); Port 3 ground connection of the adjustable voltage-stabiliser tube D28 of three ends; Polarity free capacitor C23 is connected in parallel on 2,3 ports of the adjustable voltage-stabiliser tube D28 of three ends; 1 port of the adjustable voltage-stabiliser tube D28 of three ends connects 2 ports of optocoupler U12;
3 ports of optocoupler U7, U8, U9, U10, U11 and U12 are ground connection all; After the port 4 of optocoupler U7, U8, U9, U10, U11 and U12 interconnects, be labeled as port Protect; And 4 level of the port after optocoupler U7, U8, U9, U10, U11 and U12 interconnect are by move in resistance R 59+5V output port; VoltageTest port is set between resistance R 1 and R2;
Resistance R 24, R25 form potential-divider network after mutually connecting, and are connected with 2 ports of operational amplifier U3A; One termination of resistance R 24+5V output port, one end ground connection of resistance R 25; VoltageTest port is connected with 3 ports of operational amplifier U3A through resistance R 26; 1 port label of operational amplifier U3A is OVER_V port; 1 port of resistance R 29 1 termination operational amplifier U3A, another termination+5V output port; Connect+5V of the 8 ports output port of operational amplifier U3A, the 4 port ground connection of operational amplifier U3A;
Resistance R 30, R31 form potential-divider network after mutually connecting, and are connected with 5 ports of operational amplifier U3B; One termination of resistance R 30+5V output port, one end ground connection of resistance R 31; VoltageTest port is connected with 6 ports of operational amplifier U3B through resistance R 32; 7 port label of operational amplifier U3B are LACK_V port; 7 ports of resistance R 33 1 termination operational amplifier U3B, another termination+5V output port; Connect+5V of the 8 ports output port of operational amplifier U3B, the 4 port ground connection of operational amplifier U3B;
The syndeton of described PWM ripple generative circuit module (3) is as follows:
4,8 connect+5V of the port output ports of 555 chip U1, the 1 port ground connection of 555 chip U1,3 port label of 555 chip U1 are PWM port; 5 ports of polarity free capacitor C4 mono-termination 555 chip U1, other end ground connection; The positive pole of diode D20 connects 7 ports of 555 chip U1, and negative pole connects 2 and 6 ports of 555 chip U1; One termination of resistance R 23+5V output port, 1 port of another termination slide rheostat R22; 2 ports of slide rheostat R22 connect 7 ports of 555 chip U1; One end of the 3 port connecting resistance R21 of slide rheostat R22; The negative pole of another terminating diode D19 of resistance R 21; The positive pole of diode D19 connects 2,6 ports of 555 chip U1; The positive pole of a terminating diode D19 of polarity free capacitor C3, other end ground connection;
The syndeton of described human-machine interface module (1) is as follows:
Connect+5V output port after polarity free capacitor C5, C6 and C8 parallel connection; Connect+5V of the 3 ports output port of self-locking button S1-F/R, one end of the 2 port connecting resistance R27 of self-locking button S1-F/R, the 1 port ground connection of self-locking button S1-F/R; The other end of resistance R 27 is labeled as F/R port; After polarity free capacitor C9 and C11 parallel connection, one end ground connection, the F/R port of another termination human-machine interface module (1); Connect+5V of the 3 ports output port of self-locking button S2-STOP, one end of the 2 port connecting resistance R28 of self-locking button S2-STOP, the 1 port ground connection of self-locking button S2-STOP; The other end of resistance R 28 is labeled as STOP port; Polarity free capacitor C10 one end ground connection, another termination STOP port; One end of resistance R 38 is labeled as OVER_C port, 1 port of one end sending and receiving optical diode DS1 in addition, the 2 port ground connection of light-emitting diode DS1; One end of resistance R 39 is labeled as F/R port, 1 port of one end sending and receiving optical diode DS2 in addition, the 2 port ground connection of light-emitting diode DS2; One end of resistance R 40 is labeled as NOMAL port, 1 port of one end sending and receiving optical diode DS3 in addition, the 2 port ground connection of light-emitting diode DS3; One end of resistance R 41 is labeled as OVER_V port, 1 port of one end sending and receiving optical diode DS4 in addition, the 2 port ground connection of light-emitting diode DS4; One end of resistance R 42 is labeled as LACK_VOUT port, 1 port of one end sending and receiving optical diode DS5 in addition, the 2 port ground connection of light-emitting diode DS5;
3 ports of CPLD chip U5 connect Protect port; 2 ports of CPLD chip U5 connect PWM port; 1,44,25,37,36 ports of CPLD chip U5 connect respectively two F/R, STOP, LACK_VOUT, OVER_C, the NOMAL port of human-machine interface module (1); 43,8 ports of CPLD chip U5 connect respectively OVER_V, LAVK_V port; 35,34,33,32,31,30 ports of CPLD chip U5 connect respectively U_Hin, U_Lin, V_Hin, V_Lin, W_Hin, W_Lin port; All the other ports of CPLD chip U5 are unsettled.
5. the implementation method of brushless direct current motor controller, is characterized in that: comprise that rotor-position detects the judgement of output hall signal, the judgement of input PWM ripple, rotating judgement and the processing of metal-oxide-semiconductor logical drive signal, fault and brake signal judgement and according to the steps such as logic output pwm signal of load signal.
6. the implementation method of brushless direct current motor controller according to claim 5, is characterized in that: described step is as follows:
The first step: the first initialization of system after start, refreshes LED show state;
Second step: the Hall element of brshless DC motor (8) provides the three-phase hall signal of rotor-position, and the PWM ripple that PWM ripple generative circuit module (3) provides is input to CPLD chip U5; CPLD chip U5 makes corresponding judgement, and according to the rotating instruction in human-machine interface module 1, metal-oxide-semiconductor logical drive signal is processed; And fault-signal and the brake signal of input are judged, according to judged result, generate the pwm signal of driven MOS pipe, make the conducting of metal-oxide-semiconductor logic, finally realize brshless DC motor by instruction operation; The 3rd step: when judgement metal-oxide-semiconductor overcurrent, LED can light warning, and turn-off corresponding metal-oxide-semiconductor and burn out preventing; When bus overvoltage, under voltage fault and brake signal input, corresponding LED can light warning, and turn-offs pwm signal output, and all metal-oxide-semiconductors are turn-offed.
CN201410253909.8A 2014-06-09 2014-06-09 Brushless direct current motor controller and control method Active CN104009682B (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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CN104943562A (en) * 2015-06-30 2015-09-30 郑州日产汽车有限公司 Automobile grade permanent magnet synchronous motor controller suitable for electric automobile
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CN112683115A (en) * 2020-12-16 2021-04-20 陕西航天时代导航设备有限公司 Torpedo steering engine driving system based on CPLD control
CN112865625A (en) * 2021-04-12 2021-05-28 上海宏英智能科技股份有限公司 Integrated multi-path direct current motor controller
CN113346458A (en) * 2020-03-02 2021-09-03 广东威灵电机制造有限公司 Motor control method, motor control device, motor system, and storage medium

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104734578A (en) * 2013-12-18 2015-06-24 南京沃特电机有限公司 Brushless direct current motor water pump
CN104734578B (en) * 2013-12-18 2017-08-04 南京沃特电机有限公司 A kind of brshless DC motor water pump
CN104300845A (en) * 2014-10-17 2015-01-21 中国石油天然气股份有限公司 Automobile brushless DC motor driver
CN104943562A (en) * 2015-06-30 2015-09-30 郑州日产汽车有限公司 Automobile grade permanent magnet synchronous motor controller suitable for electric automobile
CN105058983A (en) * 2015-07-31 2015-11-18 苏州蓝王机床工具科技有限公司 Power supply self-learning motor controller floating calibration apparatus
CN105058983B (en) * 2015-07-31 2016-11-23 周芒 A kind of power supply self study electric machine controller floating calibration device
CN113346458A (en) * 2020-03-02 2021-09-03 广东威灵电机制造有限公司 Motor control method, motor control device, motor system, and storage medium
CN112683115A (en) * 2020-12-16 2021-04-20 陕西航天时代导航设备有限公司 Torpedo steering engine driving system based on CPLD control
CN112683115B (en) * 2020-12-16 2024-01-30 陕西航天时代导航设备有限公司 Torpedo steering engine driving system based on CPLD control
CN112865625A (en) * 2021-04-12 2021-05-28 上海宏英智能科技股份有限公司 Integrated multi-path direct current motor controller
CN112865625B (en) * 2021-04-12 2022-11-15 上海宏英智能科技股份有限公司 Integrated multi-path direct current motor controller

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