CN104009041B

CN104009041B - Logic MTP of the NAND flash memory structure compatible with CMOS technology

Info

Publication number: CN104009041B
Application number: CN201410264647.5A
Authority: CN
Inventors: 方钢锋
Original assignee: Su Zhoufeng Microtronics Of Speeding AS
Current assignee: Su Zhoufeng Microtronics Of Speeding AS
Priority date: 2014-06-13
Filing date: 2014-06-13
Publication date: 2016-08-24
Anticipated expiration: 2034-06-13
Also published as: CN104009041A

Abstract

The present invention relates to logic MTP of a kind of NAND flash memory structure compatible with CMOS technology, comprising: a PMOS transistor and a NCAP electric capacity component units, wherein the drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the grid of PMOS transistor；Then being combined in series by 2 or multiple this unit, the drain electrode of the most each PMOS transistor is connected to the source electrode of next PMOS transistor；In the head and the tail PMOS transistor of tandem compound respectively series connection one PMOS transistor, the substrate of all PMOS transistor is linked together by N trap, and the substrate of all NCAP electric capacity is linked together by p-well.Described p-well can not be made in deep N-well, it is also possible to is made in deep N-well, isolates the p-well inside deep N-well and p-substrate by deep N-well.The invention have the advantage that the realization storage function that the elementary cell that PMOS transistor and NCAP form is together in series, the connection in PMOS transistor source electrode and drain electrode can be saved, substantially reduce the area of the bit of single elementary cell, reduce cost.

Description

Logic MTP of the NAND flash memory structure compatible with CMOS technology

Technical field

The present invention relates to a kind of non-volatility memory, especially one can be with CMOS logic process compatible Non-volatility memory, belong to technical field of integrated circuits.

Background technology

SOC(system on a chip) (SoC) is applied, has the module of many block difference in functionalitys to be integrated into an integrated electricity Road.Typically require non-volatility memory to store data, ID etc., but common embedded Flash needs Special technique and high cost, the R&D cycle is long, and with common CMOS logic technique is incompatible.

Summary of the invention

It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of compatible with CMOS technology Logic MTP of NAND flash memory structure, cost can be reduced, individual bit area is little, and with biography The semiconductor technology of system, CMOS logic technique are completely compatible.

The technical scheme provided according to the present invention, logic MTP of described NAND flash memory structure includes: One PMOS transistor and a NCAP electric capacity component units, wherein the drain electrode of NCAP electric capacity connects Line program, the floating boom of NCAP electric capacity connects the grid of PMOS transistor；Then by 2 or multiple this Unit is combined in series, and the drain electrode of the most each PMOS transistor is connected to next PMOS transistor Source electrode；Each one PMOS transistor of series connection in the head and the tail PMOS transistor of tandem compound, all The substrate of PMOS transistor is linked together by N trap, and the substrate of all NCAP electric capacity is by p-well even It is connected together.

Described p-well can not be made in deep N-well, it is also possible to is made in deep N-well, isolates by deep N-well P-well inside deep N-well and p-substrate

Specifically, wherein the source electrode of first PMOS transistor PMOS1 is connected to a PMOS The drain electrode of pipe PMOS0, the grid of PMOS PMOS0 is as the control line WL of byte, source electrode conduct The control line BL of bit, the drain electrode of last PMOS transistor PMOSn reconnects a PMOS The source electrode of pipe PMOSn+1, the grid of PMOS PMOSn+1 is as the control line of the byte of drain electrode end SWL, drain the control line SL as drain electrode end.N is the natural number more than or equal to 2.

The invention have the advantage that logic MTP of this most basic NAND structure, be a PMOS Transistor and NCAP component units, then this elementary cell be together in series realization storage function.Due to logical Cross the mode of series connection, the connection in PMOS transistor source electrode and drain electrode can be saved, be thus greatly reduced The area of the bit of single elementary cell, thus reduce cost.

Accompanying drawing explanation

Fig. 1 is the structural representation of an embodiment of the present invention.

Fig. 2 is the generalized section that p-well is not made in deep N-well.

Fig. 3 is the structure chart of another embodiment that p-well is made in deep N-well.

Fig. 4 is the generalized section that p-well is made in deep N-well.

Fig. 5 is the example structure figure as a example by two unit.

Detailed description of the invention

The invention will be further described with embodiment below in conjunction with the accompanying drawings.

Logic MTP of NAND flash memory structure of the present invention includes: a PMOS transistor and one Individual NCAP (NMOS is made in N trap) electric capacity component units, wherein NCAP electric capacity has floating boom, The drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the grid of PMOS transistor； Such as NCAP1 and the PMOS1 component units in Fig. 1, NCAP2 and PMOS2 component units, etc.. NCAP electric capacity NCAP1, NCAP2 ..., the drain electrode of NCAPn connect line program P1, P2 ... Pn respectively. Then being combined in series by 2 or multiple this unit, the drain electrode of the most each PMOS transistor is connected to The source electrode of next PMOS transistor, such as the PMOS1 of series connection, PMOS2 ..., PMOSn in Fig. 1. The source electrode of first PMOS transistor PMOS1 is connected to the drain electrode of PMOS PMOS0, The grid of PMOS PMOS0 is as the control line WL (word line) of byte, and source electrode is as bit Control line BL (Bit line), the drain electrode of last PMOS transistor PMOSn reconnects a PMOS The source electrode of pipe PMOSn+1, the grid of PMOS PMOSn+1 is as the control line of the byte of drain electrode end SWL, drain the control line SL as drain electrode end.The substrate of all PMOS transistor passes through N trap (NW) Link together.The substrate of all NCAP electric capacity is linked together by p-well (PW).

Described p-well (Pwell) can not be made in deep N-well, such as Fig. 2, p-well and P type substrate (P-Sub) It it is connection；Deep N-well (D-Nwell) can also be made in inner, such as Fig. 3 and 4, isolate by deep N-well P-well inside deep N-well and p-substrate；Deep N-well is to beat in P type substrate depths, needs in p-well Make a circle in week beat N trap (Nwell) thus it is picked out, N trap is the substrate NW with PMOS transistor Link together.

PMOS transistor PMOS0 treats as transmission gate (pass gate), by the control line (word line) of byte Form with the control line (Bit line) of bit.Connected other PMOS crystal by this PMOS transistor Logic MTP (memorizer of multiple programmable) of pipe one most basic a string NAND structure of composition.

As it is shown in figure 5, illustrate as a example by the following structure with two unit Cell1, Cell2 composition, Cell1 Comprise NCAP1 and PMOS1, Cell2 and comprise NCAP2 and PMOS2.

A, writing PMOS PMOS1 i.e. cell1 is to choose write, cell2 is be not written into.

WL

BL

P1

P2

SWL

SL

NW

0V

7V

0V

So, at P1 end, and bigger pressure reduction between Poly1, will be produced, to carrying out FN The voltage difference of tunneling (FN tunnelling) or the condition of electric field, such electronics is just from floating boom floating poly1 Being raised to P1 by FN tunnelling, the threshold V T of PMOS1, ratio is less easily energized.Do not have accordingly There is the cell2 chosen because of P2 end with the voltage difference of the grid poly2 of PMOS2 is 0, not to entering The voltage difference of row FN tunnelling or the condition of electric field, so PMOS2 does not becomes.

B, erasing (wiping two, together erasing)

WL

BL

P1

P2

SWL

SL

NW

5V

-5V

5V

So, between P1 end and Poly1, will between P2 end and Poly2 (grid of PMOS2) Producing bigger pressure reduction, to carrying out the voltage difference of FN tunnelling or the condition of electric field, such electronics is just From P1 to floating boom floating poly1, P2 to floating boom floating poly2 by FN tunnelling, PMOS1 Threshold V T raise, ratio is less easily energized.

C, reading PMOS PMOS1

WL

BL

P1

P2

SWL

SL

NW

0

1V

0

3V

So electric current is from SL to BL, by the size comparing electric current judge write P1 be the state write also It it is the state wiped.

If such as Fig. 3, p-well being made in deep N-well shown in 4, being advantageous in that, negative pressure can be added in p-well, So there is no need to high pressure, just improve the reliability of transistor and the simple of periphery circuit.Such as, 7v Being segmented into 3.5V and-3.5V to come, effect is the same.

Claims

1. logic MTP of the NAND flash memory structure compatible with CMOS technology, is characterized in that, including: a PMOS transistor and a NCAP electric capacity component units, wherein the drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the grid of PMOS transistor；Then being combined in series by 2 or multiple this unit, the drain electrode of the most each PMOS transistor is connected to the source electrode of next PMOS transistor；In the head and the tail PMOS transistor of tandem compound respectively series connection one PMOS transistor, the substrate of all PMOS transistor is linked together by N trap, and the substrate of all NCAP electric capacity is linked together by p-well.

2. logic MTP of the NAND flash memory structure with CMOS technology compatibility as claimed in claim 1, it is characterized in that, wherein the source electrode of first PMOS transistor PMOS1 is connected to the drain electrode of PMOS PMOS0, the grid of PMOS PMOS0 is as the control line WL of byte, source electrode is as the control line BL of bit, the drain electrode of last PMOS transistor PMOSn reconnects the source electrode of PMOS PMOSn+1, the grid of PMOS PMOSn+1 is as the control line SWL of the byte of drain electrode end, drain electrode is the natural number more than or equal to 2 as the control line SL, n of drain electrode end.

3. logic MTP of the NAND flash memory structure with CMOS technology compatibility as claimed in claim 1, is characterized in that, The p-well of the substrate of described NCAP electric capacity is separated by deep N-well with the P type substrate of whole chip.

4. logic MTP of the NAND flash memory structure with CMOS technology compatibility as claimed in claim 3, is characterized in that, when adding negative voltage in p-well, NCAP electric capacity can pass negative voltage.