CN104008216B - Method of using a memory compiler to generate optimized memory instances - Google Patents

Abstract

A method of using a memory compiler to generate optimized memory instances. Data describing the designed memory is provided, and front-end models and back-end models are generated to provide a database. Design criteria are received through a user interface. The memory design is optimized in terms of both speed, power, and area according to the provided database and design criteria, resulting in memory instances.

Description

Method of using a memory compiler to generate optimized memory instances

technical field

The present invention relates to a memory compiler, in particular to a memory compiler which simultaneously considers and automatically optimizes speed, power and area.

current technology

A memory compiler (eg, a random access memory compiler) can be used to automatically generate memory instances. The memory compiler can also be used to support system-on-chip (SoC) design capabilities. However, conventional memory compilers only provide a single characteristic specification of speed, power, or density when generating memory instances. Therefore, the generated memory instance usually does not consider the optimization of the three aspects at the same time to meet the customer's requirements.

Furthermore, conventional memory compilers operate at the device level when generating memory instances. Due to the large number of components themselves, the overall efficiency is almost adjusted on the order of millions or more, so the optimization of the memory instance takes a considerable amount of time.

Since traditional memory compilers cannot efficiently and quickly generate optimized memory instances, it is urgent to propose a novel memory compiler to overcome the shortcomings of traditional memory compilers.

Contents of the invention

In view of the above-mentioned problems in the prior art, one of the purposes of the embodiments of the present invention is to provide a method for using a memory compiler to generate an optimized memory instance, which simultaneously considers the three factors of speed, power and area to optimize the memory the design of. In one embodiment, the proposed memory compiler executes at the architecture level, block level and device level to accelerate the generation of memory instances.

According to the embodiment of the present invention, relevant description data of the designed memory is provided, and a front-end model and a back-end model are generated to provide a database. Receive design guidelines through the user interface. According to the database and design criteria, the three factors of speed, power and area are considered simultaneously to optimize the design of the memory, so as to generate memory instances.

In a specific embodiment, the optimization step uses a top-down approach to decompose the designed memory architecture into multiple blocks, analyze and select the best combination according to the characteristics of the blocks; for these decomposed areas block, obtain at least one high-speed database, at least one low-power database, and at least one small-area database from the database; select and adjust the blocks in the general direction according to the performance characteristics of these blocks; when the best combination of blocks is selected Finally, adjust the component parameters in this block to make more detailed adjustments to achieve optimization. The optimization step also connects the adjustment elements to form the blocks using a bottom-up approach, and combines the blocks to form the memory to see the overall optimized performance.

Description of drawings

FIG. 1 shows a flowchart of a method for using a memory compiler to generate an optimized memory instance according to an embodiment of the present invention.

FIG. 2 shows a detailed flowchart of the optimization steps of FIG. 1 .

Figure 3 shows the block decomposition.

Figure 4 shows a three-dimensional constraint surface.

Explanation of reference signs

11: Provide memory related data

12: Front-end model and back-end model

13: Memory Compiler User Interface

14: Optimization

141: Defining Formulas

142: Select the relevant part of the database

143: Architecture Decomposition

144: Obtain high-speed, low-power, small-area database

145: Component adjustment

146: Block remapping

147: Schema Remapping

148: Whether it meets the restriction

149: Instance generation

15: Candidate list

16: Whether it meets the requirements

41: 3D constraint surface

2A: Top-Down Approach

2B: Bottom-up approach

XDEC: X decoder

IO: input and output circuit

detailed description

FIG. 1 shows a flowchart of a method for using a memory compiler to generate an optimized memory instance according to an embodiment of the present invention. This embodiment can be used to create optimized memory instances, such as static random access memory (SRAM), read only memory (ROM), content addressable memory (CAM) or flash memory.

First, in step 11, relevant description data of the designed memory is provided, such as provided by a semiconductor foundry. The data provided in step 11 can be circuits described by the integrated circuit simulation program (SPICE), design rules (such as integrated circuit topology layout rules (TLR)) or device types (such as random access memory components), but are not limited to this. According to the provided data, generate a front-end (F/E) model and a back-end (B/E) model in step 12 to provide the database (library) with the design behavior model to the optimizer (optimizer), the The optimizer simultaneously considers the three factors of speed, power and area (or density) to optimize the memory design. In contrast, conventional memory compilers are developed for a single characteristic factor of speed, power or density, but not all three. In this specification, the front-end model is related to the current, voltage and/or power of the designed memory, while the back-end model is related to the layout pattern of the designed memory. In a preferred embodiment, the proposed method can be adapted to design small-area (or high-density) memories. Compared to conventional methods, the preferred embodiment is more efficient in designing optimized small area (or high density) memory instances.

On the other hand, at step 13 , a user interface, such as a graphical user interface (GUI), is installed on a computer with a memory compiler for receiving design criteria, such as instance configuration, from the customer. The user interface also receives priorities for speed, power and area. In addition, the user interface also receives the storage capacity of the designed memory (for example, 2MB or 1GB). In the next step, the memory is designed and optimized in terms of storage capacity and priority.

Next, in step 14 , the design of speed, power and area is optimized according to the database provided in step 12 and the constraints received in step 13 . Details about the optimization will be described below with reference to FIG. 2 .

After performing the optimization in step 14, a candidate list is prepared in step 15, which contains a plurality of generated memory instances for final evaluation according to customer requirements. At step 16, one of the generated memory instances is selected from the candidate list, which best meets the customer's requirements.

FIG. 2 shows a detailed flowchart of the optimization (ie, step 14 ) of FIG. 1 . In step 141 , according to the constraints received in step 13 , control rules (or formulas) are defined for the speed, power and area of the designed memory. Simultaneously, at step 142 , according to the constraints received at step 13 , the relevant portion of the provided database is selected.

According to one of the features of this embodiment, the design of the memory is optimized using a top-down approach 2A. Wherein, in step 143 , as shown in FIG. 3 , the whole structure of the designed memory is decomposed into multiple blocks: memory unit, X decoder (XDEC), control circuit and input-output circuit (IO). Therefore, the architecture of the memory can be represented at the block level, so as to analyze the characteristics of the blocks and select the best combination. On the contrary, the traditional memory compiler is executed at the device level, so its memory design is more difficult to control. The block in this embodiment may be a leaf-cell-based block, but is not limited thereto.

Next, at step 144 , at least one high-speed database, at least one low-power database, and at least one small-area (or high-density) database related to these blocks are obtained from the database provided in step 12 . In this embodiment, the modifiers "high" or "low/small" respectively refer to a value of a physical quantity (such as speed, power or area) being greater than or less than a preset critical value. Then, select and adjust blocks in the general direction according to the performance characteristics of these blocks. Finally, in step 145, after the blocks with the best combination are selected, if necessary, the parameters of the components (eg, transistors) in these blocks are adjusted or fine-tuned in more detail. In this embodiment, the adjusted parameters may include threshold voltage (such as low-level threshold voltage, standard threshold voltage or high-level threshold voltage), P-type metal oxide semiconductor (PMOS) or N-type metal oxide semiconductor ( NMOS) width/length, physical layout style parallel/serial elements and dynamic/static combination/sequential (combinational/sequential) gate (gate) circuit type.

According to another feature of this embodiment, the optimization is fine-tuned using a bottom-up approach 2B. At step 146, these adjusted elements (e.g., some adjusted and some not adjusted) are concatenated (or remapped) to form individual blocks; at step 147, these blocks are combined (or remapped) to form A memory is formed, and then the overall combination of the memory is simulated to see the overall optimal performance. If the simulation result meets the constraint condition (step 148), then generate the relevant memory instance (step 149); otherwise, according to the priority order received in step 13, go to step 142 to select another part of the provided database, and execute the top-down method again Bottom-up approach 2A and bottom-up approach 2B. Thus, the top-down approach 2A and the bottom-up approach 2B are performed one or more times, thereby obtaining a candidate list, which includes a plurality of generated memory instances.

As mentioned above, this embodiment optimizes the design of the memory by simultaneously considering the three factors of speed, power and area. Therefore, as shown in FIG. 4 , a three-dimensional constraint surface (constraint surface) 41 is constructed during the optimization process. One or more memory instances that are close to the three-dimensional constraint surface 41 are then selected as the best candidates.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; other equivalent changes or modifications that do not deviate from the disclosed spirit of the invention should be included within the scope of the present application .

Claims (16)

1. A method of using a memory compiler to generate an optimized memory instance, comprising: Provide relevant description data of the designed memory; generating a front-end model and a back-end model to provide a database; Receive design guidelines through the user interface; and According to the database and the design criteria, the design of the memory is optimized while considering speed, power and area, thereby generating a memory instance, wherein the design criteria include priorities for speed, power, and area, Wherein, the optimization step includes: defining control rules for the speed, power and area of the designed memory according to the priority order and specification requirements; select relevant parts of said database according to said priorities and specifications; Decomposing the architecture of the designed memory into a plurality of blocks; For these decomposed blocks, at least one high-speed database, at least one low-power database and at least one small-area database are obtained from said databases; According to the performance characteristics of these blocks, make block selection and adjustment in the general direction; adjust the parameters of the elements of these blocks; linking the adjusted elements to form the blocks; combining said blocks to form said memory; and An overall combinational simulation is performed on the memory. 2. The method of using a memory compiler to generate an optimized memory instance according to claim 1, further comprising: preparing a candidate list for evaluation; the candidate list includes a plurality of said memory instances; and One of these memory instances is selected from the candidate list. 3. The method of using a memory compiler to generate an optimized memory instance according to claim 1, wherein the description data includes described circuits, design rules or device types. 4. The method of using a memory compiler to generate an optimized memory instance of claim 1, wherein the front-end model is related to current, voltage and/or power of the designed memory. 5. The method of using a memory compiler to generate an optimized memory instance of claim 1, wherein the backend model is related to a layout pattern of the designed memory. 6. The method of using a memory compiler to generate an optimized memory instance according to claim 1, further comprising: receiving the storage capacity of the designed memory. 7. The method of generating an optimized memory instance using a memory compiler as claimed in claim 1, wherein said decomposed blocks include memory cells, X decoders, control circuits, and I/O circuits. 8. The method of using a memory compiler to generate an optimized memory instance according to claim 1, wherein said parameters include threshold voltage, width/width of PMOS or NMOS Length, parallel/series elements and dynamic/static gate types. 9. The method of using a memory compiler to generate optimized memory instances according to claim 1, wherein said optimizing step generates a three-dimensional constraint surface, one or more memory instances approximating the three-dimensional constraint surface was selected as the best candidate. 10. A method for optimizing a three-dimensional memory compiler, comprising: According to the three-dimensional priority order of speed, power and area, define the control rules for the three-dimensional design of the memory, thereby generating a three-dimensional constraint surface; Decomposing the designed memory into a plurality of blocks; For the decomposed blocks, at least one high-speed database, at least one low-power database, and at least one small-area database are obtained from a provision database; According to the performance characteristics of these blocks, make block selection and adjustment in the general direction; adjust the parameters of the elements of these blocks; linking the adjustment elements to form the blocks; combine the blocks to produce multiple memory instances; and One or more memory instances close to the three-dimensional constraint surface are selected as the best candidates. 11. The method for optimizing a 3D memory compiler according to claim 10, wherein the decomposed blocks include memory units, X decoders, control circuits, and input-output circuits. 12. The method for optimizing a three-dimensional memory compiler according to claim 10, wherein said parameters include threshold voltage, width/length of PMOS or NMOS, parallel connection/serial connection Components and dynamic/static gate circuit types. 13. A method for memory compiler optimization, comprising: Define the governing rules for the speed, power and area of the designed memory according to the order of priority; According to this order of priority, select one to provide the relevant part of the database; In a top-down manner, the architecture of the designed memory is decomposed into multiple blocks, and then divided into multiple components; In a bottom-up manner, connecting the elements to form blocks, and then combining the blocks to form the architecture of the memory; and An overall combinatorial simulation of this memory is performed, The top-down steps described therein include: Decompose the architecture of the designed memory into multiple blocks; For the decomposed blocks, at least one high-speed database, at least one low-power database, and at least one small-area database are obtained from the database; Based on the performance characteristics of these blocks, select and adjust blocks in the general direction; and Adjust the parameters of the components of these blocks. 14. The method for memory compiler optimization according to claim 13, wherein the bottom-up step comprises: linking the tuning elements to form the blocks; and These blocks are combined to form the memory. 15. The memory compiler optimization method according to claim 13, wherein the decomposed blocks include memory units, X decoders, control circuits, and I/O circuits. 16. The method for optimizing a memory compiler according to claim 13, wherein said parameters include threshold voltage, width/length of PMOS or NMOS, parallel/serial elements And dynamic/static gate circuit type.