CN104008216A - Method for utilizing storage complier to generate optimized storage example - Google Patents
Method for utilizing storage complier to generate optimized storage example Download PDFInfo
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- CN104008216A CN104008216A CN201310056648.6A CN201310056648A CN104008216A CN 104008216 A CN104008216 A CN 104008216A CN 201310056648 A CN201310056648 A CN 201310056648A CN 104008216 A CN104008216 A CN 104008216A
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- storer
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Abstract
Provided is a method for utilizing a storage complier to generate an optimized storage example. Data used for scanning a designed storage are provided, and a front end model and a rear end model are produced to provide a database, a design criterion is received through a user interface, and the design of the storage is optimized by considering the speed, the power and the area simultaneously according to the provided database and the design criterion to generate a storage example.
Description
Technical field
The present invention relates to a kind of storer compiler (compiler), particularly relate to a kind of also storer compiler of self-optimization speed, power and area of simultaneously considering.
Prior art
Storer compiler (for example random access memory compiler) can be used for automatically producing memory example (memory instance).Storer compiler also can be used for the designed capacity that support system is integrated wafer (SoC).Yet traditional storer compiler, when producing memory example, only provides the single characteristic specification of speed, power or density to formulate.Therefore the optimization that the memory example, producing is not considered three aspects: conventionally is simultaneously to meet client's requirement.
In addition,, when producing memory example, traditional storer compiler operations is in element (device) level.Because the quantity of element own is various, be almost to adjust whole efficiency with more than 1,000,000 orders of magnitude, therefore, the optimization of memory example need expend the suitable time.
Cannot be effectively and produce fast optimizing memory example in view of traditional storer compiler, therefore need the storer compiler that proposes a kind of novelty badly, to overcome the shortcoming of legacy memory compiler.
Summary of the invention
The problems referred to above in view of prior art, one of object of the embodiment of the present invention is to propose a kind of storer compiler that uses to produce the method for optimizing memory example, and it considers tripartite's factor of speed, power and area with the design of optimizing memory simultaneously.In one embodiment, the storer compiler proposing is executed in framework (architecture) level, block (block) level and element level, in order to the generation of speeds up memory example.
According to embodiments of the invention, the associated description data of designed storer are provided, and produce front end model and rear end model so that a database to be provided.By user interface, receive design criteria.According to described database and design criteria, consider speed, power and area tripartite factor with the design of this storer of optimization simultaneously, thereby produce memory example.
In a specific embodiment, this optimization step is used top-down mode, and the framework of designed storer is decomposed into a plurality of blocks, according to the characteristic of block, does and analyzes and select best of breed; For these, decompose block, from database, obtain at least one high rate data storehouse, at least one miniwatt database and at least one small size database; For the performance characteristic of these blocks, doing the block of general orientation selects and adjusts; After the block of best of breed is selected, adjust the component parameters of this block the inside and do the adjustment of thinner portion, to realize optimization.This optimization step is also used mode from bottom to top, links these and adjusts element, to form these blocks; And combine these blocks, to form storer, and then check the performance of global optimization.
Accompanying drawing explanation
Fig. 1 shows that the use storer compiler of the embodiment of the present invention is to produce the process flow diagram of the method for optimizing memory example.
Fig. 2 shows the detail flowchart of the optimization step of Fig. 1.
Fig. 3 illustrates block and decomposes.
Fig. 4 illustrates three-dimensional restrictive condition curved surface.
Description of reference numerals
11: storer related data is provided
12: front end model and and rear end model
13: storer compiler user interface
14: optimization
141: defined formula
142: the relevant portion of selecting database
143: framework decomposes
144: obtain high-speed, miniwatt, small size database
145: element adjustment
146: block remaps
147: framework remaps
148: whether meet restrictive condition
149: example produces
15: candidate list
16: whether meet the requirements
41: three-dimensional restrictive condition curved surface
2A: mode from top to bottom
2B: mode from bottom to top
XDEC:X demoder
IO: imput output circuit
Embodiment
Fig. 1 shows that the use storer compiler of the embodiment of the present invention is to produce the process flow diagram of the method for optimizing memory example.The present embodiment can be in order to produce optimizing memory example, for example static RAM (SRAM), ROM (read-only memory) (ROM), Content Addressable Memory (content addressable memory, CAM) or flash memory.
First, in step 11, provide the associated description data of designed storer, for example, by semiconductor foundry factory, provided.The data that step 11 provides can be the described circuit of simulation of integrated circuit program (SPICE), Design Rule (for example integrated circuit topological layout rule (TLR)) or element kenel (for example random access memory), but are not limited to this.According to provided data, in step 12, produce front end (F/E) model and rear end (B/E) model, in order to the database (library) with design behavior model is offered to optimizer (optimizer), this optimizer is considered this tripartite of speed, power and area (or density) because of the usually design of optimizing memory simultaneously.On the contrary, traditional storer compiler is only developed for the single characteristic factor in speed, power or density, but not all three factors.In this manual, front end model is electric current, voltage and/or the power that is relevant to designed storer, and rear end model is relevant to the layout pattern (pattern) of designed storer.In a preferred embodiment, the method proposing is applicable to design small size (or high density) storer.Than classic method, this preferred embodiment is more effective in optimization of design small size (or high density) memory example.
On the other hand, in step 13, user interface (for example graphic user interface (GUI)) is installed on the computer with storer compiler, for example, for receive design criteria (design criteria), exemplary configuration (configuration) from client.User interface is the priority of inbound pacing, power and area also.In addition, user interface also receives the storage volume (for example 2MB or 1GB) of designed storer.In step next, according to storage volume with priority designs and this storer of optimization.
Then,, in step 14, the restrictive condition that the database providing according to step 12 and step 13 receive (constraint) carrys out the design of optimization speed, power and area.Will be hereinafter, in conjunction with Fig. 2, relevant optimized details is described.
After the optimization of execution step 14, in step 15, prepare candidate list (candidate list), the memory example that it comprises a plurality of generations, in order to finally to assess according to customer requirement.In step 16, from candidate list, select in produced memory example, it meets client's requirement most.
Fig. 2 shows optimization (that is, the detail flowchart of step 14) of Fig. 1.In step 141, the restrictive condition receiving according to step 13, defines control law (or formula) to the speed of designed storer, power and area.Meanwhile, in step 142, according to the restrictive condition receiving in step 13, the relevant portion of the database that selection provides.
According to one of feature of the present embodiment, use mode (top-down approach) 2A from top to bottom to carry out the design of optimizing memory.Wherein, in step 143, as illustrated in Fig. 3, the whole framework of designed storer is decomposed into a plurality of blocks: memory cell, X demoder (XDEC), control circuit and imput output circuit (IO).Thus, can block level represent the framework of storer, with the specificity analysis that carries out block with select best of breed.Contrary, traditional storer compiler is to be executed in element level, so its reservoir designs is more difficult controls.The block of the present embodiment can be the block based on leaf unit (leaf-cell-based), but is not limited to this.
Next, in step 144, the database providing from step 12, obtain at least one high rate data storehouse, at least one miniwatt database and at least one small size (or high density) database that these blocks are relevant.In the present embodiment, qualifier " height " or " low/little " refer to that respectively the value of a physical quantity (for example speed, power or area) is greater than or less than a preset critical.Then, for these block performance characteristics, do the block selection and adjustment of general orientation.Finally, in step 145, after the block of best of breed is selected, if necessary, the parameter of the element of these blocks (for example, electric crystal) is carried out to adjustment or the fine setting of thinner portion.In the present embodiment, the parameter of adjusting can comprise critical voltage (for example low level critical voltage, standard critical voltage or high levle critical voltage), P-type mos (PMOS) or the width/height of N-type metal-oxide semiconductor (MOS) (NMOS), the parallel/series element of physical layout's pattern and dynamically/(combinational/sequential) gate (gate) circuit kenel of static combination/in proper order.
According to another feature of the present embodiment, use mode (bottom-up approach) 2B from bottom to top to finely tune optimization.In step 146, these are adjusted to element (for example, another part is not adjusted to partly adjusting) and linked (or remapping) to form indivedual blocks; In step 147, these blocks are combined to (or remapping) to form storer, then this storer is carried out to entire combination simulation, to check the performance of global optimization.If analog result meets restrictive condition (step 148), produce relevant memory example (step 149); Otherwise the priority receiving according to step 13, another part of the database that provides is provided to step 142, and is again carried out mode 2A and from bottom to top mode 2B from top to bottom.Thus, carry out mode 2A and from bottom to top mode 2B one or many from top to bottom, thereby obtain candidate list, the memory example that it comprises a plurality of generations.
As previously mentioned, the present embodiment is considered the design that this three of speed, power and area factor carrys out optimizing memory simultaneously.Therefore,, as illustrated in Fig. 4, in optimization procedures, construction goes out three-dimensional restrictive condition curved surface (constraint surface) 41.The one or more memory example that approach three-dimensional restrictive condition curved surface 41 are chosen as best candidate.
The above is only the preferred embodiments of the present invention, is not intended to limit scope of the present invention; Other does not depart from the equivalence change completing under the disclosed spirit of invention or modifies, in the application's that all should be included in scope.
Claims (19)
1. use storer compiler to produce a method for optimizing memory example, comprise:
The associated description data of designed storer are provided;
Produce front end model and rear end model, so that a database to be provided;
By user interface, receive design criteria; And
According to this database and this design criteria, consider speed, power and area with the design of this storer of optimization simultaneously, thereby produce memory example.
2. use storer compiler according to claim 1, to produce the method for optimizing memory example, also comprises:
Prepare a candidate list, in order to assess; This candidate list comprises a plurality of described memory example; And
From this candidate list, select in these memory example.
3. use storer compiler according to claim 1 is to produce the method for optimizing memory example, the circuit that wherein said data of description comprises description, Design Rule or element kenel.
4. use storer compiler according to claim 1 is to produce the method for optimizing memory example, and wherein, described front end model is relevant to electric current, voltage and/or the power of described designed storer.
5. use storer compiler according to claim 1 is to produce the method for optimizing memory example, and wherein, described rear end model is relevant to the layout pattern of described designed storer.
6. use storer compiler according to claim 1 to be to produce the method for optimizing memory example, wherein, and the priority that described design criteria comprises speed, power and area.
7. use storer compiler according to claim 1, to produce the method for optimizing memory example, also comprises: the storage volume that receives described designed storer.
8. use storer compiler according to claim 6 is to produce the method for optimizing memory example, and wherein, described optimization step comprises:
According to described priority and specification requirement, the speed of described designed storer, power and area are defined to control law;
According to described priority and specification requirement, select the relevant portion of described database;
The framework of described designed storer is decomposed into a plurality of blocks;
For the block of these decomposition, from described database, obtain at least one high rate data storehouse, at least one miniwatt database and at least one small size database;
For these block performance characteristics, do the block of general orientation and select and adjust;
Adjust the parameter of the element of these blocks;
The element that links these adjustment, to form described these blocks;
Described these blocks of combination, to form described storer; And
Described storer is carried out to entire combination simulation.
9. use storer compiler according to claim 8 is to produce the method for optimizing memory example, and wherein, described these decompose block and comprise memory cell, X demoder, control circuit and imput output circuit.
10. use storer compiler according to claim 8 is to produce the method for optimizing memory example, wherein, the width/height that described parameter comprises critical voltage, P-type mos PMOS or N-type metal-oxide semiconductor (MOS) NMOS, parallel/series element and dynamically/static gate circuit kenel.
11. use storer compilers according to claim 1 are to produce the method for optimizing memory example, wherein, described optimization step produces three-dimensional restrictive condition curved surface, and the one or more memory example that approach this three-dimensional restrictive condition curved surface are chosen as best candidate.
12. 1 kinds of three-dimensional storage compiler method for optimizing, comprise:
Three-dimensional priority according to speed, power and area, defines control law to the three-dimensional of designed storer, thereby produces three-dimensional restrictive condition curved surface;
Described designed storer is decomposed into a plurality of blocks;
For the block of these decomposition, from one, provide database to obtain at least one high rate data storehouse, at least one miniwatt database and at least one small size database;
For these block performance characteristics, do the block of general orientation and select and adjust;
Adjust the parameter of the element of these blocks;
Link these and adjust element, to form these blocks;
Combine these blocks, to produce a plurality of memory example; And
Select to approach described three-dimensional restrictive condition curved surface one respectively or a plurality of memory example, as best candidate.
13. three-dimensional storage compiler method for optimizing according to claim 12, wherein, these decompose block and comprise memory cell, X demoder, control circuit and imput output circuit.
14. three-dimensional storage compiler method for optimizing according to claim 12, the width/height that wherein said parameter comprises critical voltage, P-type mos PMOS or N-type metal-oxide semiconductor (MOS) NMOS, parallel/series element and dynamically/static gate circuit kenel.
15. 1 kinds of storer compiler method for optimizing, comprise:
According to priority, the speed of designed storer, power and area are defined to control law;
According to this priority, selection one provides the relevant portion of database;
In top-down mode, the framework of this designed storer is decomposed into a plurality of blocks, be further divided into a plurality of elements;
In mode from bottom to top, link these elements to form block, this block of recombinant is to form the framework of this storer; And
This storer is carried out to entire combination simulation.
16. storer compiler method for optimizing according to claim 15, wherein said top-down step comprises:
The framework of this designed storer is decomposed into a plurality of blocks;
For the block of these decomposition, from this database, obtain at least one high rate data storehouse, at least one miniwatt database and at least one small size database;
For these block performance characteristics, do the block of general orientation and select and adjust; And
Adjust the parameter of the element of these blocks.
17. storer compiler method for optimizing according to claim 16, wherein this step from bottom to top comprises:
Link these and adjust element, to form these blocks; And
Combine these blocks, to form this storer.
18. storer compiler method for optimizing according to claim 16, wherein, these decompose block and comprise memory cell, X demoder, control circuit and imput output circuit.
19. storer compiler method for optimizing according to claim 16, the width/height that wherein said parameter comprises critical voltage, P-type mos PMOS or N-type metal-oxide semiconductor (MOS) NMOS, parallel/series element and dynamically/static gate circuit kenel.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106383938A (en) * | 2016-09-07 | 2017-02-08 | 北京深维科技有限公司 | FPGA memory inference method and apparatus |
| CN116362199A (en) * | 2023-05-26 | 2023-06-30 | 上海韬润半导体有限公司 | Method and device for optimizing type selection of memory in chip design |
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| US7424687B2 (en) * | 2005-11-16 | 2008-09-09 | Lsi Corporation | Method and apparatus for mapping design memories to integrated circuit layout |
| EP2477109B1 (en) * | 2006-04-12 | 2016-07-13 | Soft Machines, Inc. | Apparatus and method for processing an instruction matrix specifying parallel and dependent operations |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106383938A (en) * | 2016-09-07 | 2017-02-08 | 北京深维科技有限公司 | FPGA memory inference method and apparatus |
| CN116362199A (en) * | 2023-05-26 | 2023-06-30 | 上海韬润半导体有限公司 | Method and device for optimizing type selection of memory in chip design |
| CN116362199B (en) * | 2023-05-26 | 2023-08-11 | 上海韬润半导体有限公司 | Method and device for optimizing type selection of memory in chip design |
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