CN104008071A - Signal processing method, connector and memory memorizing device - Google Patents

Signal processing method, connector and memory memorizing device Download PDF

Info

Publication number
CN104008071A
CN104008071A CN201310056502.1A CN201310056502A CN104008071A CN 104008071 A CN104008071 A CN 104008071A CN 201310056502 A CN201310056502 A CN 201310056502A CN 104008071 A CN104008071 A CN 104008071A
Authority
CN
China
Prior art keywords
frequency
signal string
spread spectrum
signal
transmission frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310056502.1A
Other languages
Chinese (zh)
Other versions
CN104008071B (en
Inventor
陈安忠
陈志铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phison Electronics Corp
Original Assignee
Phison Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phison Electronics Corp filed Critical Phison Electronics Corp
Priority to CN201310056502.1A priority Critical patent/CN104008071B/en
Publication of CN104008071A publication Critical patent/CN104008071A/en
Application granted granted Critical
Publication of CN104008071B publication Critical patent/CN104008071B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a signal processing method, a connector and a memory memorizing device. The signal processing method is applied to the connector which does not comprise a quartz oscillator. The signal processing method comprises receiving a first signal string from a host system; tracking the transmission frequency of the first signal string and obtaining frequency offset of the first signal string relative to the transmission frequency; judging whether the first signal string is performed spread spectrum operation or not according to the frequency offset to generate a judgment result; generating a second signal string according to the judgment result and the transmission frequency. According to the signal processing method, the spread spectrum operation can be processed under the condition that the quartz oscillator is not arranged.

Description

Signal processing method, connector and memory storage apparatus
Technical field
The invention relates to a kind of signal processing method, and particularly relevant for a kind of signal processing method, connector and memory storage apparatus of connector.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and consumer is also increased rapidly to the demand of medium.For example, because duplicative non-volatile memory module (, flash memory) has that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be applicable to being built in above-mentioned given an example various portable multimedia devices very much.
In general, duplicative non-volatile memory module can be electrically connected to a host computer system by a connector.In some communication standards, the train of signal transmitting between connector and host computer system likely can pass through spread spectrum (spread spectrum clock, be designated hereinafter simply as SSC) operation, the frequency that is train of signal can change within the specific limits along with the time, to allow signal energy be dispersed in a frequency band range, therefore the electromagnetic interference (EMI) (Electromagnetic interference, EMI) of signal is inhibited.Although spread spectrum operation can be resisted noise (noise) or be disturbed impacts such as (interference), can use larger frequency range, and the frequency of train of signal may be along with time fluctuation.Yet in some applications, in connector, quartz (controlled) oscillator does not produce clock pulse signal accurately, now connector is that the train of signal transmitting with reference to host computer system produces clock pulse signal.Therefore, how, in the situation that this does not have quartz (controlled) oscillator, how connector produces a more accurate and satisfactory output signal, the subject under discussion that those skilled in the art are concerned about for this reason.
Summary of the invention
Exemplary embodiment of the present invention provides a kind of signal processing method, connector and memory storage apparatus, can make not have the connector of quartz (controlled) oscillator to produce an output signal that meets specific specifications.
The present invention's one exemplary embodiment proposes a kind of signal processing method, and for a connector, wherein connector does not comprise a quartz (controlled) oscillator, and signal processing method comprises: receive a first signal string from a host computer system; Follow the trail of the transmission frequency of first signal string, and obtain first signal string with respect to a frequency offset of transmission frequency; According to this frequency offset, judge whether first signal string operates to produce a judged result through spread spectrum; According to this judged result and transmission frequency, produce a secondary signal string.
In an exemplary embodiment, the step of the transmission frequency of above-mentioned tracking first signal string comprises: an average frequency that continues to detect first signal string; Judgement is in a very first time interval, and whether this average frequency is in a mobility scale; And if this average frequency is all within the scope of earthquake in very first time interval, setting this average frequency is above-mentioned transmission frequency.
In an exemplary embodiment, above-mentionedly according to frequency offset, judge that whether first signal string comprises through the step of spread spectrum operation: whether determination frequency side-play amount meets first critical value; And if frequency offset meets the first critical value, the operation of judgement first signal string process spread spectrum.
In an exemplary embodiment, above-mentioned frequency offset is the poor of a maximum frequency of first signal string and transmission frequency, or is the poor of a minimum frequency of first signal string and transmission frequency.
In an exemplary embodiment, above-mentionedly according to frequency offset, judge that whether first signal string comprises through the step of spread spectrum operation: cumulative frequency offset is to produce a cumulative frequency difference value in second time interval; Judge whether this cumulative frequency difference value meets second critical value; And if cumulative frequency difference value meets the second critical value, the operation of judgement first signal string process spread spectrum.
In an exemplary embodiment, the above-mentioned step according to judged result and transmission frequency generation secondary signal string comprises: if first signal string is through spread spectrum operation, according to an adjustment signal, to meeting a data-signal string implementation center spread spectrum of transmission frequency, operate to produce secondary signal string.
In an exemplary embodiment, the above-mentioned step according to judged result and transmission frequency generation secondary signal string comprises: if first signal string is to operate through spread spectrum, one data-signal string is converted to a compensating frequency from transmission frequency, and wherein compensating frequency is greater than transmission frequency; According to an adjustment signal, to meeting the data-signal string of compensating frequency, carry out a downward spread spectrum and operate to produce secondary signal string.
From another one angle, the present invention's one exemplary embodiment proposes a kind of connector.This connector does not comprise quartz (controlled) oscillator, and this connector comprises receiving circuit, frequency tracking circuit and transfer circuit.Receiving circuit is in order to receive the first signal string from host computer system.Frequency tracking circuit is to be electrically connected to receiving circuit, in order to follow the trail of the transmission frequency of first signal string.Transfer circuit is to be electrically connected to receiving circuit and frequency tracking circuit.Receiving circuit is also in order to obtain first signal string with respect to a frequency offset of transmission frequency, and judges according to this frequency offset whether first signal string operates to produce judged result through spread spectrum.Transfer circuit is also in order to produce a secondary signal string according to this judged result and transmission frequency.
In an exemplary embodiment, the operation that said frequencies is followed the trail of the transmission frequency of circuit tracking first signal string comprises: frequency tracking device continues to detect an average frequency of first signal string, and judgement is in a very first time interval, and whether this average frequency is in a mobility scale; If this average frequency is all within the scope of earthquake in very first time interval, it is above-mentioned transmission frequency that frequency tracking device can be set this average frequency.
In an exemplary embodiment, above-mentioned receiving circuit comprises a spread spectrum detecting device.Above-mentioned receiving circuit judges that according to frequency offset the operation whether first signal string operates through spread spectrum comprises: whether spread spectrum detecting device determination frequency side-play amount meets first critical value; And if frequency offset meets the first critical value, the operation of spread spectrum detecting device judgement first signal string process spread spectrum.
In an exemplary embodiment, above-mentioned receiving circuit judges that according to frequency offset the operation whether first signal string operates through spread spectrum comprises: spread spectrum detecting device adds up frequency offset to produce a cumulative frequency difference value in second time interval; Spread spectrum detecting device judges whether this cumulative frequency difference value meets second critical value; If cumulative frequency difference value meets the second critical value, spread spectrum detecting device judgement first signal string is through spread spectrum operation.
In an exemplary embodiment, the operation that above-mentioned transfer circuit produces secondary signal string according to judged result and transmission frequency comprises: if first signal string is through spread spectrum operation, transfer circuit is carried out a center spread spectrum and operated to produce secondary signal string meeting a data-signal string of transmission frequency according to an adjustment signal.
In an exemplary embodiment, above-mentioned transfer circuit comprises according to the operation of judged result and transmission frequency generation secondary signal string: if first signal string is to operate through spread spectrum, transfer circuit is converted to a compensating frequency by a data-signal string from this transmission frequency, and wherein compensating frequency is greater than transmission frequency; Transfer circuit carries out a downward spread spectrum and operates to produce secondary signal string meeting the data-signal string of compensating frequency according to an adjustment signal.
With another one angle, the present invention's one exemplary embodiment proposes a kind of memory storage apparatus, comprises duplicative non-volatile memory module, Memory Controller and connector.Duplicative non-volatile memory module comprises a plurality of entities unit of erasing.Memory Controller is to be electrically connected to duplicative non-volatile memory module.Connector is to be electrically connected to Memory Controller, in order to be electrically connected to a host computer system.This connector does not comprise a quartz (controlled) oscillator, and this connector comprises receiving circuit, frequency tracking circuit and transfer circuit.Receiving circuit is in order to receive the first signal string from host computer system.Frequency tracking circuit is to be electrically connected to receiving circuit, in order to follow the trail of the transmission frequency of first signal string.Transfer circuit is to be electrically connected to receiving circuit and frequency tracking circuit.Receiving circuit is also in order to obtain first signal string with respect to a frequency offset of transmission frequency, and judges according to this frequency offset whether first signal string operates to produce judged result through spread spectrum.Transfer circuit is also in order to produce a secondary signal string according to this judged result and transmission frequency.
Based on above-mentioned, signal processing method, connector and memory storage apparatus that exemplary embodiment of the present invention proposes, whether the train of signal that can detect in the situation that there is no quartz (controlled) oscillator from host computer system operates through spread spectrum, and to sending the train of signal of host computer system to, carry out spread spectrum operation accordingly.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is according to host computer system and the memory storage apparatus shown in an exemplary embodiment;
Figure 1B is according to the schematic diagram of computer, input/output device and the memory storage apparatus shown in an exemplary embodiment;
Fig. 1 C is according to the host computer system shown in an exemplary embodiment and the schematic diagram of memory storage apparatus;
Fig. 2 means the summary calcspar of the memory storage apparatus shown in Figure 1A;
Fig. 3 is according to the part calcspar of connector shown in an exemplary embodiment;
Fig. 4 is according to the part calcspar of connector 102 shown in an exemplary embodiment;
Fig. 5 is according to the schematic diagram of following the trail of first signal string shown in an exemplary embodiment;
Fig. 6 and 7 is according to the schematic diagram judging whether shown in an exemplary embodiment through spread spectrum operation;
Fig. 8 A and Fig. 8 B are according to the schematic diagram that produces secondary signal string shown in an exemplary embodiment;
Fig. 9 is according to the process flow diagram of signal processing method shown in an exemplary embodiment.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212: flash disk;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connector;
104: Memory Controller;
106: duplicative non-volatile memory module;
108 (0)~108 (R): the entity unit of erasing;
302: first signal string;
304: frequency information;
306: clock pulse signal;
308: judged result;
310: receiving circuit;
320: frequency tracking circuit;
330: transfer circuit;
402: control code;
404: pulse reference clock;
410: frequency detector;
420: time clock data restoring circuit;
430: spread spectrum detecting device;
440: frequency tracking device;
450: clock pulse generating circuit;
452: phase-locked loop;
454: pulse reference clock generator;
502: transmission frequency;
602,608,804: frequency;
604,606: frequency offset;
702,706: time interval;
704,708: region;
802,806: data-signal string;
804: compensating frequency;
S902, S904, S906, S908: the step of signal processing method.
Embodiment
Generally speaking, memory storage apparatus (also claiming storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memory storage apparatus is to use together with host computer system, so that host computer system can write to data memory storage apparatus or reading out data from memory storage apparatus.
Figure 1A is according to host computer system and the memory storage apparatus shown in an exemplary embodiment.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output is designated hereinafter simply as I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, is designated hereinafter simply as RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is to be electrically connected by data transmission interface 1110 and other elements of host computer system 1000.By microprocessor 1102, random access memory 1104, data can be write to memory storage apparatus 100 or reading out data from memory storage apparatus 100 with the operation of input/output device 1106.For example, memory storage apparatus 100 can be flash disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, is designated hereinafter simply as SSD) 1216 memory storages such as nonvolatile memory such as duplicative such as grade as shown in Figure 1B.
Generally speaking, host computer system 1000 is for can coordinate to store substantially any system of data with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, in host computer system 1000, be digital camera (video camera) 1310 o'clock, duplicative nonvolatile memory memory storage is its safe digital using (Secure Digital Memory Card, be designated hereinafter simply as SD) card 1312, multimedia (Multimedia Card, be designated hereinafter simply as MMC) card 1314, memory stick (memory stick) 1316, compact flash (Compact Flash, is designated hereinafter simply as CF) card 1318 or embedded memory storage 1320 (as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, is designated hereinafter simply as eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.
Fig. 2 means the summary calcspar of the memory storage apparatus shown in Figure 1A.
Please refer to Fig. 2, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible with USB (universal serial bus) (Universal Serial Bus, is designated hereinafter simply as USB) standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can be also to meet advanced annex (the Serial Advanced Technology Attachment of serial, be designated hereinafter simply as SATA) standard, parallel advanced annex (Parallel Advanced Technology Attachment, be designated hereinafter simply as PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, be designated hereinafter simply as IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, be designated hereinafter simply as PCI Express) standard, safe digital (Secure Digital, be designated hereinafter simply as SD) interface standard, a hypervelocity generation (Ultra High Speed-I, be designated hereinafter simply as UHS-I) interface standard, hypervelocity two generations (Ultra High Speed-II, be designated hereinafter simply as UHS-II) interface standard, memory stick (Memory Stick, be designated hereinafter simply as MS) interface standard, multimedia storage card (Multi Media Card, be designated hereinafter simply as MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card, be designated hereinafter simply as eMMC) interface standard, general flash memory (Universal Flash Storage, be designated hereinafter simply as UFS) interface standard, compact flash (Compact Flash, be designated hereinafter simply as CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, be designated hereinafter simply as IDE) standard or other applicable standards.
A plurality of logic gates or steering order that Memory Controller 104 is done with example, in hardware or form of firmware in order to execution, and according to the instruction of host computer system 1000, in duplicative non-volatile memory module 106, carry out the operations such as writing, read and erase of data.
Duplicative non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.Duplicative non-volatile memory module 106 has the entity unit 108 (0)~108 (R) of erasing.For example, the entity unit 108 (0)~108 (R) of erasing can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity unit of erasing has respectively a plurality of entity sequencing unit, and belongs to the erase entity sequencing unit of unit of same entity and can be write independently and side by side be erased.For example, each entity unit of erasing is comprised of 128 entity sequencing unit.Yet, it must be appreciated, the invention is not restricted to this, each entity unit of erasing can be comprised of an entity sequencing unit arbitrarily 64 entity sequencing unit, 256 entity sequencing unit or other.
In more detail, the entity unit of erasing is the least unit of erasing.Also can say each entity memory cell of being erased in the lump that unit contains minimal amount of erasing.The minimum unit that entity sequencing unit is sequencing.That is the minimum unit that, entity sequencing unit is data writing.Each entity sequencing unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises a plurality of entities access address in order to store user's data, and redundancy ratio special zone for example, in order to the data (, control information and error correcting code) of storage system.In this exemplary embodiment, in the data bit district of each entity sequencing unit, can comprise 4 entity access addresses, and the size of an entity access address is 512 bytes (byte is designated hereinafter simply as B).Yet, in other exemplary embodiment, in data bit district, also can comprise 8,16 or the more or less entity access address of number, the present invention does not limit size and the number of entity access address.For example, the entity unit of erasing is solid block, and entity sequencing unit is physical page or entity sector.
In this exemplary embodiment, duplicative non-volatile memory module 106 is multistage memory cell (Multi Level Cell, is designated hereinafter simply as MLC) NAND type flash memory module, in a memory cell, can store at least 2 Bit datas.Yet, the invention is not restricted to this, duplicative non-volatile memory module 106 is single-order memory cell (Single Level Cell also, being designated hereinafter simply as SLC) NAND type flash memory module, multistage memory cell (Trinary Level Cell, is designated hereinafter simply as TLC) NAND type flash memory module, other flash memory module or other have the memory module of identical characteristics.
Fig. 3 is according to the part calcspar of connector shown in an exemplary embodiment.
Please refer to Fig. 3, connector 102 has at least comprised receiving circuit 310, frequency tracking circuit 320 and transfer circuit 330.Receiving circuit 310 can receive the first signal string 302 that comes from host computer system 1000, and detects the frequency of first signal string 302.Receiving circuit 310 also can send frequency tracking circuit 320 to the frequency information 304 relevant to first signal string 302.Frequency tracking circuit 320 can be followed the trail of a transmission frequency of first signal string 302, and for example, this transmission frequency is the average frequency of first signal string 302.Frequency tracking circuit 320 can send the clock pulse signal 306 that meets this transmission frequency to receiving circuit 310 and transfer circuit 330.Receiving circuit 310 can be obtained first signal string 302 with respect to a frequency offset of above-mentioned transmission frequency.For example, receiving circuit 310 be continue receive first signal string 302, and calculate the frequency of first signal string 302 and the difference between transmission frequency sometime, therefore produce frequency offset.Receiving circuit 310 also can judge that first signal string 302, whether through a spread spectrum operation, therefore produces a judged result 308 according to this frequency offset.If first signal string 302 has passed through spread spectrum operation, represent that the frequency of first signal string 302 can be along with time fluctuation.Therefore,, when the absolute value of this frequency offset is larger, represent that first signal string has more likely passed through spread spectrum operation.Receiving circuit 310 can send judged result 308 to transfer circuit 330, and transfer circuit 330 can be followed judged result and clock pulse signal 306 generation secondary signal strings 312 accordingly, and send secondary signal string 312 to host computer system 1000 or another electronic installation.Specifically, in connector 102, can't comprise quartz (controlled) oscillator (crystal oscillator).
Fig. 4 is according to the part calcspar of connector 102 shown in an exemplary embodiment.
Please refer to Fig. 4, in the exemplary embodiment of Fig. 4, receiving circuit 310 comprises frequency detector 410, time clock data recovery (clock data recovery, is designated hereinafter simply as CDR) circuit 420 and spread spectrum detecting device 430.And frequency tracking circuit 320 comprises frequency tracking device 440 and clock pulse generating circuit 450.Clock pulse generating circuit 450 also comprises phase-locked loop 452 and pulse reference clock generator 454.
Time clock data restoring circuit 420 is the data in order to recover wherein according to first signal string 302.Time clock data restoring circuit 420 is also in order to confirm whether first signal string 302 meets the standard of a transmission standard.For instance, in the standard of USB3.0, limited the scope (for example, minimum spread spectrum scope is 0~-4000ppm (Parts Per Million, 1,000,000/), and maximum spread spectrum scope is 0~-5000ppm) of spread spectrum operation.Time clock data restoring circuit 420 can judge whether the frequency of first signal string 302 has exceeded above-mentioned scope.
Frequency detector 410 is the frequencies that detect constantly first signal string 302, and detects the frequency of first signal string 302 and the difference between the frequency of clock pulse signal 306.In this exemplary embodiment, this difference is frequency information 304, and frequency detector 410 can send frequency information 304 to frequency tracking device 440.
Frequency tracking device 440 can detect according to frequency information 304 average frequency of first signal strings 302, and judgement is in a very first time interval, and whether this average frequency is all in the middle of a mobility scale.For example, this mobility scale is 300ppm, and very first time interval can be any number, and the present invention is also not subject to the limits.If in very first time interval, in the middle of all earthquake scopes of this average frequency, frequency tracking device 440 can this average frequency of setting be the transmission frequency of first signal string 302.Please refer to Fig. 5, transverse axis is the time, and its unit is microsecond (microsecond is designated hereinafter simply as μ s); The longitudinal axis is data transfer rate (data rate), also claims frequency, at this, with ppm, represents.In the exemplary embodiment shown in Fig. 5, first signal string 302 has passed through a spread spectrum operation, and its scope is 0~-5000ppm.And frequency tracking device 440 can track transmission frequency 502.Specifically, unit interval (unit interval, is designated hereinafter simply as UI) is the inverse of a standard frequency.For example, if the standard frequency of transmission is 5G Hz between host computer system 1000 and memory storage apparatus 100, UI is 1/5G second.At this, the scope of spread spectrum operation is 0~-5000ppm, so the scope of UI can be UI~UI+5000ppm.At this, with UI, represent the numerical value of frequency, therefore the frequency corresponding to UI can be greater than the frequency corresponding to UI+5000ppm, below repeats no more.In the exemplary embodiment of Fig. 5, transmission frequency 502 is UI+2500ppm.
Please refer to back Fig. 4, frequency tracking device 440 can produce a control code 402 to clock pulse generating circuit 450.Pulse reference clock generator 454 can produce a pulse reference clock 404 to phase-locked loop 452.This clock pulse generating circuit 450 can be hartley (Hartley) oscillator, Ke Bizi (Colpitts) oscillator, carat general (Clapp) oscillator, phase shift (phase-shift) oscillator, RC oscillator, LC oscillator or other are not the oscillator of quartz (controlled) oscillator.
Phase-locked loop 452 is the time clock in order to produce according to control code 402 position pulse-generating circuits 450, and to revise it be a more accurate clock pulse signal 306, and the frequency of this clock pulse signal 306 is transmission frequency.Yet this area has knows that the knowledgeable should understand the operation of phase-locked loop 452, just repeats no more at this conventionally.
Spread spectrum detecting device 430 is in order to judge according to clock pulse signal 306 whether first signal string 302 has passed through spread spectrum operation.In an exemplary embodiment, spread spectrum detecting device 430 can calculate the frequency of some time point first signal strings 302 and the difference between transmission frequency with as a frequency offset.Spread spectrum detecting device 430 can judge whether this frequency offset meets first critical value.If this frequency offset meets the first critical value, spread spectrum detecting device 430 can pass through spread spectrum operation by judgement first signal string 302.For instance, as shown in Figure 6, the first critical value is the difference (its value is positive number) of frequency 602 and transmission frequency 502, and frequency offset 604 can be greater than this first critical value.Therefore, spread spectrum detecting device 430 can pass through spread spectrum operation by judgement first signal string 302.It should be noted that, in fact spread spectrum detecting device 430 also can first deduct transmission frequency 502 the first critical value to obtain frequency 602, and can judge whether whether the frequency of first signal string 302 operate through spread spectrum with decision first signal string 302 lower than frequency 602.On the other hand, after determination frequency side-play amount 606 is greater than this first critical value, spread spectrum detecting device 430 also can judge that first signal string 302 has passed through spread spectrum operation.In the same manner, in implementation, spread spectrum detecting device 430 also can first add transmission frequency 502 that the first critical value is to calculate frequency 608, and judges whether the frequency of first signal string 302 is greater than frequency 608 to determine that whether first signal string 302 is through spread spectrum operation.At this, " whether determination frequency side-play amount meets the first critical value " can comprise above-mentioned various state, and the present invention is also not subject to the limits.In addition, the present invention does not limit the numerical value of the first critical value yet.
In another exemplary embodiment, spread spectrum detecting device 430 is maximum frequency (in this case UI) or the minimum frequencies (in this case UI+5000ppm) that first detect first signal string 302, whether the difference that judges again this maximum frequency and transmission frequency 502 is greater than the first critical value, or whether the difference of minimum frequency and transmission frequency 502 is less than the first negative critical value.Identical, in implementation, spread spectrum detecting device 430 also can judge whether maximum frequency is greater than frequency 608, or whether minimum frequency be less than frequency 602, therefore judges whether first signal string 302 has passed through spread spectrum operation.
Fig. 7 is according to the schematic diagram judging whether shown in an exemplary embodiment through spread spectrum operation.
Please refer to Fig. 7, in the exemplary embodiment of Fig. 7, spread spectrum detecting device 430 is in second time interval, to add up frequency offset to produce a cumulative frequency difference value.Spread spectrum detecting device 430 can judge whether this cumulative frequency difference value meets second critical value.If this cumulative frequency difference value meets the second critical value, spread spectrum detecting device 430 can pass through spread spectrum operation by judgement first signal string 302.For instance, 430 meetings of spread spectrum detecting device are at the interior cumulative frequency offset of time interval 702, and the cumulative frequency difference value calculating can be expressed as the area in region 704.If the area in region 704 is greater than the second critical value, spread spectrum detecting device 430 can pass through spread spectrum operation by judgement first signal string 302.Or spread spectrum detecting device 430 also can be at the interior cumulative frequency offset of time interval 706, and the cumulative frequency difference value calculating can be expressed as the area in region 708.Yet the present invention does not limit the scope of the second time interval, do not limit the numerical value of the second critical value yet.
Please refer to back Fig. 4, spread spectrum detecting device 430 has judged that first signal string 302 whether after spread spectrum operation, can transmit judged result 308 to transfer circuit 330.And, utilize first signal string 302 to come the clock pulse generating circuit 450 of calibration reference time clock can know that followed the trail of transmission frequency is corresponding to UI or UI+2500ppm.Thus, transfer circuit 330 can know how according to tracked transmission frequency, to produce secondary signal string 312.It should be noted that in another exemplary embodiment, secondary signal string 312 not necessarily can be through spread spectrum operation.Transfer circuit 330 can determine whether carrying out spread spectrum operation to secondary signal string 312 according to a control signal, and the interface of the destination that this control signal can will transmit according to secondary signal string 312, function or host computer system 1000 and determining.In other words, transfer circuit 330 also can judge whether transmitted secondary signal string 312 will carry out spread spectrum operation, therefore different in the situation that, produces secondary signal string 312.
Specifically, transfer circuit 330 is a data-signal string will be converted to secondary signal string 312, and sends secondary signal string 312 to host computer system 1000.If first signal string 302 is through spread spectrum operation, and secondary signal string 312 do not have to carry out spread spectrum operation, and transfer circuit 330 can be according to clock pulse signal 306 using the data-signal string that meets transmission frequency as secondary signal string 312.If first signal string 302 is not through spread spectrum operation, but secondary signal string 312 will carry out spread spectrum operation, transfer circuit 330 can be adjusted signal according to one and operate to produce secondary signal string 312 to meeting the data-signal string execution spread spectrum of transmission frequency.
Fig. 8 A and Fig. 8 B are according to the schematic diagram that produces secondary signal string shown in an exemplary embodiment.
Please refer to Fig. 8 A, if first signal string 302 has through spread spectrum operation, and secondary signal string 312 will carry out spread spectrum operation, and transfer circuit 330 can be converted to compensating frequency 804 from transmission frequency 502 by data-signal string 802.Transfer circuit 330 can be adjusted signal according to one and carry out downward spread spectrum operation to produce secondary signal string 312 to meeting the data-signal string 802 of compensating frequency 804.At this, compensating frequency 804 can be greater than transmission frequency 502, and the scope of spread spectrum operation is downwards 0~-5000ppm (corresponding to UI~UI+5000ppm).Yet in other exemplary embodiment, this downward spread spectrum operation can have other scopes, the present invention is also not subject to the limits.
If having through spread spectrum, first signal string 302 operates, but secondary signal string 312 does not carry out spread spectrum operation, transfer circuit 330 also can be after being converted to compensating frequency 804 by transmission frequency 502, using the data-signal string 802 that meets compensating frequency 804 as secondary signal string 312.
Please refer to Fig. 8 B, in another exemplary embodiment, if having through spread spectrum, first signal string 302 operates, and secondary signal string 312 will carry out spread spectrum operation, transfer circuit 330 can operate to produce secondary signal string to meeting the data-signal Chuan806 implementation center spread spectrum of transmission frequency 502 according to an adjustment signal.In this exemplary embodiment, the scope of center spread spectrum operation is-2500ppm~2500ppm, but the present invention not subject to the limits.Thus, even there is no quartz (controlled) oscillator in connector 102, connector 102 also can produce through spread spectrum operation or not have the secondary signal string 312 through spread spectrum operation according to transmission frequency 502.
Fig. 9 is according to the process flow diagram of signal processing method shown in an exemplary embodiment.
Please refer to Fig. 9, in step S902, receive the first signal string from host computer system.In step S904, follow the trail of a transmission frequency of first signal string, and obtain first signal string with respect to the frequency offset of this transmission frequency.In step S906, according to frequency offset, judge whether first signal string operates to produce a judged result through a spread spectrum.In step S908, according to this judged result and transmission frequency, produce a secondary signal string, and transmission secondary signal string is to host computer system or another electronic installation.Yet each step has described in detail as above in Fig. 9, at this, just do not repeating.It should be noted that in Fig. 9, each step can be used as a plurality of procedure codes or circuit, the present invention is also not subject to the limits.In addition, can arrange in pairs or groups above exemplary embodiment of the method for Fig. 9 is used, and also can use separately, and the present invention is also not subject to the limits.
In sum, signal processing method, connector and memory storage apparatus that exemplary embodiment of the present invention proposes, whether the train of signal that can judge from host computer system in the situation that there is no quartz (controlled) oscillator passes through spread-spectrum signal.And according to the result of judgement and the transmission frequency tracking, the train of signal that sends host computer system to can meet a transmission standard.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (21)

1. a signal processing method, for a connector, is characterized in that, this connector does not comprise a quartz (controlled) oscillator, and this signal processing method comprises:
Reception is from a first signal string of a host computer system;
Follow the trail of a transmission frequency of this first signal string, and obtain this first signal string with respect to a frequency offset of this transmission frequency;
According to this frequency offset, judge whether this first signal string operates to produce a judged result through a spread spectrum;
According to this judged result and this transmission frequency, produce a secondary signal string.
2. signal processing method according to claim 1, is characterized in that, the step of following the trail of this transmission frequency of this first signal string comprises:
Continue to detect an average frequency of this first signal string;
Judgement is in a very first time interval, and whether this average frequency is in a mobility scale; And
If this average frequency, all in this mobility scale, is set this average frequency for this transmission frequency in this very first time interval.
3. signal processing method according to claim 1, is characterized in that, according to this frequency offset, judges that the step whether this first signal string operates through this spread spectrum comprises:
Judge whether this frequency offset meets one first critical value; And
If this frequency offset meets this first critical value, judge that this first signal string is through this spread spectrum operation.
4. signal processing method according to claim 3, is characterized in that, this frequency offset is the poor of a maximum frequency of this first signal string and this transmission frequency, or is the poor of a minimum frequency of this first signal string and this transmission frequency.
5. signal processing method according to claim 1, is characterized in that, according to this frequency offset, judges that the step whether this first signal string operates through this spread spectrum comprises:
In one second time interval, cumulative this frequency offset is to produce a cumulative frequency difference value;
Judge whether this cumulative frequency difference value meets one second critical value; And
If this cumulative frequency difference value meets this second critical value, judge that this first signal string is through this spread spectrum operation.
6. signal processing method according to claim 1, is characterized in that, the step that produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is through the operation of this spread spectrum, according to an adjustment signal, to meeting a data-signal string of this transmission frequency, carries out a center spread spectrum and operate to produce this secondary signal string.
7. signal processing method according to claim 1, is characterized in that, the step that produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is through this spread spectrum operation, a data-signal string is converted to a compensating frequency from this transmission frequency, wherein this compensating frequency is greater than this transmission frequency;
According to an adjustment signal, to meeting this data-signal string of this compensating frequency, carry out a downward spread spectrum and operate to produce this secondary signal string.
8. a connector, this connector does not comprise a quartz (controlled) oscillator, it is characterized in that, this connector comprises:
One receiving circuit, in order to receive the first signal string from a host computer system;
One frequency tracking circuit, is electrically connected to this receiving circuit, in order to follow the trail of a transmission frequency of this first signal string; And
One transfer circuit, is electrically connected to this receiving circuit and this frequency tracking circuit,
Wherein, this receiving circuit is in order to obtain this first signal string with respect to a frequency offset of this transmission frequency, and judges according to this frequency offset whether this first signal string operates to produce a judged result through a spread spectrum,
Wherein, this transfer circuit is in order to produce a secondary signal string according to this judged result and this transmission frequency.
9. connector according to claim 8, is characterized in that, the operation that this frequency tracking circuit is followed the trail of this transmission frequency of this first signal string comprises:
This frequency tracking device continue to detect an average frequency of this first signal string, and judgement is in a very first time interval, and whether this average frequency is in a mobility scale; And
If this average frequency is all in this mobility scale in this very first time interval, this frequency tracking device is set this average frequency for this transmission frequency.
10. connector according to claim 8, is characterized in that, this receiving circuit comprises a spread spectrum detecting device, and this receiving circuit judges that according to this frequency offset the operation whether this first signal string operates through this spread spectrum comprises:
This spread spectrum detecting device judges whether this frequency offset meets one first critical value; And
If this frequency offset meets this first critical value, this spread spectrum detecting device judges that this first signal string is through this spread spectrum operation.
11. connectors according to claim 10, is characterized in that, this frequency offset is the poor of a maximum frequency of this first signal string and this transmission frequency, or are the poor of a minimum frequency of this first signal string and this transmission frequency.
12. connectors according to claim 8, is characterized in that, this receiving circuit comprises a spread spectrum detecting device, and this receiving circuit judges that according to this frequency offset the operation whether this first signal string operates through this spread spectrum comprises:
This spread spectrum detecting device adds up this frequency offset to produce a cumulative frequency difference value in one second time interval;
This spread spectrum detecting device judges whether this cumulative frequency difference value meets one second critical value; And
If this cumulative frequency difference value meets this second critical value, this spread spectrum detecting device judges that this first signal string is through this spread spectrum operation.
13. connectors according to claim 8, is characterized in that, the operation that this transfer circuit produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is through the operation of this spread spectrum, this transfer circuit is carried out a center spread spectrum and is operated to produce this secondary signal string meeting a data-signal string of this transmission frequency according to an adjustment signal.
14. connectors according to claim 8, is characterized in that, the operation that this transfer circuit produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is that this transfer circuit is converted to a compensating frequency by a data-signal string from this transmission frequency through this spread spectrum operation, wherein this compensating frequency is greater than this transmission frequency; And
This transfer circuit carries out a downward spread spectrum and operates to produce this secondary signal meeting this data-signal string of this compensating frequency according to an adjustment signal.
15. 1 kinds of memory storage apparatus, is characterized in that, comprising:
One duplicative non-volatile memory module, comprises a plurality of entities unit of erasing;
One Memory Controller, is electrically connected to this duplicative non-volatile memory module; And
A connector, is electrically connected to this Memory Controller, and in order to be electrically connected to a host computer system, wherein this connector does not comprise a quartz (controlled) oscillator, and this connector comprises:
One receiving circuit, in order to receive the first signal string from this host computer system;
One frequency tracking circuit, is electrically connected to this receiving circuit, in order to follow the trail of a transmission frequency of this first signal string; And
One transfer circuit, is electrically connected to this receiving circuit and this frequency tracking circuit,
Wherein, this receiving circuit is in order to obtain this first signal string with respect to a frequency offset of this transmission frequency, and judges according to this frequency offset whether this first signal string operates to produce a judged result through a spread spectrum,
Wherein, this transfer circuit is in order to produce a secondary signal string according to this judged result and this transmission frequency.
16. memory storage apparatus according to claim 15, is characterized in that, the operation that this frequency tracking circuit is followed the trail of this transmission frequency of this first signal string comprises:
This frequency tracking device continue to detect an average frequency of this first signal string, and judgement is in a very first time interval, and whether this average frequency is in a mobility scale; And
If this average frequency is all in this mobility scale in this very first time interval, this frequency tracking device is set this average frequency for this transmission frequency.
17. memory storage apparatus according to claim 15, is characterized in that, this receiving circuit comprises a spread spectrum detecting device, and this receiving circuit judges that according to this frequency offset the operation whether this first signal string operates through this spread spectrum comprises:
This spread spectrum detecting device judges whether this frequency offset meets one first critical value; And
If this frequency offset meets this first critical value, this spread spectrum detecting device judges that this first signal string is through this spread spectrum operation.
18. memory storage apparatus according to claim 17, is characterized in that, this frequency offset is the poor of a maximum frequency of this first signal string and this transmission frequency, or are the poor of a minimum frequency of this first signal string and this transmission frequency.
19. memory storage apparatus according to claim 15, is characterized in that, this receiving circuit comprises a spread spectrum detecting device, and this receiving circuit judges that according to this frequency offset the operation whether this first signal string operates through this spread spectrum comprises:
This spread spectrum detecting device adds up this frequency offset to produce a cumulative frequency difference value in one second time interval;
This spread spectrum detecting device judges whether this cumulative frequency difference value meets one second critical value; And
If this cumulative frequency difference value meets this second critical value, this spread spectrum detecting device judges that this first signal string is through this spread spectrum operation.
20. memory storage apparatus according to claim 15, is characterized in that, the operation that this transfer circuit produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is through the operation of this spread spectrum, this transfer circuit is carried out a center spread spectrum and is operated to produce this secondary signal string meeting a data-signal string of this transmission frequency according to an adjustment signal.
21. memory storage apparatus according to claim 15, is characterized in that, the operation that this transfer circuit produces this secondary signal string according to this judged result and this transmission frequency comprises:
If this first signal string is that this transfer circuit is converted to a compensating frequency by a data-signal string from this transmission frequency through this spread spectrum operation, wherein this compensating frequency is greater than this transmission frequency; And
This transfer circuit carries out a downward spread spectrum and operates to produce this secondary signal string meeting this data-signal string of this compensating frequency according to an adjustment signal.
CN201310056502.1A 2013-02-22 2013-02-22 Signal processing method, adapter and memory storage apparatus Active CN104008071B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310056502.1A CN104008071B (en) 2013-02-22 2013-02-22 Signal processing method, adapter and memory storage apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310056502.1A CN104008071B (en) 2013-02-22 2013-02-22 Signal processing method, adapter and memory storage apparatus

Publications (2)

Publication Number Publication Date
CN104008071A true CN104008071A (en) 2014-08-27
CN104008071B CN104008071B (en) 2017-03-01

Family

ID=51368731

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310056502.1A Active CN104008071B (en) 2013-02-22 2013-02-22 Signal processing method, adapter and memory storage apparatus

Country Status (1)

Country Link
CN (1) CN104008071B (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7738617B1 (en) * 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
JP4104624B2 (en) * 2005-11-25 2008-06-18 シャープ株式会社 Image processing apparatus, image reading apparatus, and image forming apparatus
TWI309836B (en) * 2006-08-21 2009-05-11 Realtek Semiconductor Corp A memory card reader controller with spread spectrum clock
TWI444823B (en) * 2011-03-31 2014-07-11 Phison Electronics Corp Reference frequency setting method, memory controller and flash memory storage apparatus

Also Published As

Publication number Publication date
CN104008071B (en) 2017-03-01

Similar Documents

Publication Publication Date Title
CN111445942B (en) Nonvolatile memory read threshold optimization based on retention drift history
US9036685B2 (en) Connecting interface unit and memory storage device
CN106155585B (en) Adaptive read disturb reclaim strategy
US9653176B2 (en) Read disturb reclaim policy
US9311231B2 (en) Connecting interface unit and memory storage device
KR101811298B1 (en) Seed controller which provide a randomizer with a seed and a memory controller having the seed controller
CN110349607B (en) Memory device, method of operating the same, and memory system including the same
US20140136925A1 (en) Method of operating a data storage device
KR101949987B1 (en) Data storage device and operating method thereof
CN110444240B (en) Encoder and decoder for memory system and method thereof
US10326622B2 (en) Equalizer tuning method, signal receiving circuit and a memory storage device
US10991409B2 (en) Encoder for memory system and method thereof
US20200119754A1 (en) Error correction circuit, and memory controller having the error correction circuit and memory system having the memory controller
KR20220142781A (en) Controller and operation method thereof
KR20160051328A (en) Data recovery method and nonvolatile memory system using the same
KR102350644B1 (en) Memory controller and memory system having the same
US10627851B2 (en) Reference clock signal generation method, memory storage device and connection interface unit
CN102831932A (en) Data read method, memory controller and memory storage apparatus
CN110780801A (en) Memory system, memory controller and operating method thereof
TWI497301B (en) Signal processing method, cennector, and memory storage device
CN104424987A (en) Connection interface unit and memory storage apparatus
CN104008071A (en) Signal processing method, connector and memory memorizing device
US8897093B2 (en) Controlling method of connector, connector, and memory storage device
KR102157672B1 (en) Semiconductor apparatus and method of operating the same
US20210303715A1 (en) Data scrambler for memory systems and method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant