CN103986467A - Multi-level parallel type ADC and DAC based on voltage following switch - Google Patents
Multi-level parallel type ADC and DAC based on voltage following switch Download PDFInfo
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- CN103986467A CN103986467A CN201310048568.6A CN201310048568A CN103986467A CN 103986467 A CN103986467 A CN 103986467A CN 201310048568 A CN201310048568 A CN 201310048568A CN 103986467 A CN103986467 A CN 103986467A
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Abstract
Provided are a multi-level parallel type ADC and DAC based on a voltage following switch. The voltage following switch serves as a signal switch to transmit or block signals. The voltage following switch is composed of a voltage follower and a power supply loop switch. The power supply loop switch is an electronic device placed on a follower working power supply loop and can be controlled to be turned on or off according to switch control signals, and accordingly a follower signal loop is controlled to be opened or closed. By utilizing the characteristics of the integration operational amplifier follower, the switch is close to ideal connection when signals are connected, and resistance is infinitely large when the signals are disconnected. The following switch is applied to the ADC and the DAC; and a m-level*q-position equal-resistance link type ADC, a m-level*q-position equal-resistance link type DAC, a two-level logarithmic resistance link type ADC, a two-level logarithmic resistance link type DAC, a multi-level logarithmic resistance link type ADC, a multi-level logarithmic resistance link type DAC, a digital type logarithm converter and a digital type anti-logarithm converter based on the following switch can be formed.
Description
Technical field: the invention belongs to digital communication, digital switch and analog to digital converter, digital to analog converter category.
Background technology: A/D converter has developed more than 30 year, experienced technological innovation repeatedly, from parallel, successive approximation, integrated AD C, the ∑-Δ type getting up to new development in recent years and pipelined ad C, they respectively have its pluses and minuses, can meet the use of different application scenarios.
Successive approximation, integral form, voltage to frequency conversion type etc., be mainly used in middling speed or compared with in the data acquisition of low speed, medium accuracy and intelligent instrument.Classification-type and pipelined ad C are mainly used in the fields such as the transient signal processing under high-speed case, quick waveform storage and record, high-speed data acquisition, vision signal quantification and high-speed figure mechanics of communication.In addition, adopt jerk type and the isostructural high-speed ADC of folded form, can be applicable to the aspects such as base band demodulating in broadcasting satellite.∑-Δ type ADC master is applied to the particularly electronic measurements field such as digital audio system, multimedia, seismic prospecting instrument, sonar of high-accuracy data acquisition.At a high speed high-order ADC is technology foremost, the present invention proposes a kind of ADC of a novel high speed high position.
DAC has a variety of, because the error of current source type DAC is less, so become current DAC, manufacture main flow, have: binary system current source weighting type, unit current source type, segmented current-steering type etc., yet which kind of DAC no matter at present, its basic principle is power current method in essence: digital signal is become to different power (2
0, 2
1, 2
2, 2
3...) and I
unitelectric current, and then superpose and pass through operational amplifier and convert analog voltage signal to.The present invention proposes the DAC without power electric current.
The present invention first makes some and illustrates in advance:
● the in-phase input end of integrated operational amplifier (abbreviation integrated transporting discharging) is called for short in-phase end, and inverting input is called for short end of oppisite phase.
● voltage follower (abbreviation follower) is the circuit being formed by connecting by integrated transporting discharging, by after the end of oppisite phase of integrated transporting discharging and output short circuit, become follower, known according to electronic technology knowledge, signal is inputted from in-phase end, input signal can accurately be followed and equal to the voltage of output, and the voltage drop of signal voltage from input to output is minimum (can be less than 10
-8v), from engineering viewpoint, say that zero voltage drop or conducting resistance equal zero; Meanwhile, input resistance greatly (can reach 10
9Ω), from engineering viewpoint, say that input resistance equals infinitely great.
● input, the output signal voltage of voltage follow switch (switch followed in abbreviation) exist valid interval, and all signal voltages are all in valid interval herein.
● critical switch S
λ gthe meaning of symbol is the critical switch in λ level g rank;
● simple and clear in order to describe, agreement positive logic, high potential represents with " 1 ", " 0 " expression for electronegative potential; Approximately fix in comparator, when measured signal is greater than reference voltage, be output as " 1 "; In fact, can be generalized to different agreements;
● the multistage parallel formula super high-speed A/D C of logarithmic companding law of the present invention and DAC, respectively referred to as logarithm ADC and logarithm DAC, are collectively referred to as to logarithm ADDA by logarithm ADC and logarithm DAC; By the sub level of logarithm ADC, logarithm DAC, logarithm ADDA, respectively referred to as sub level ADC, sub level DAC, sub level ADDA, the above sub level of two-stage or two-stage claims multistage; Logarithm ADDA consists of multistage sub level ADDA; The symbol of logarithm ADC, logarithm DAC, logarithm ADDA, sub level ADC, sub level DAC, sub level ADDA is respectively AD##, DA##, A##D, AD#, DA#, A#D;
● with λ wildcard α, β, γ Its α, β, γ ... in fact be exactly 1,2,3 ..., the method adopting for fear of numbering conflict; α level, β level, γ level ... represent the 1st grade, the 2nd grade, 3rd level ..., m level is final stage; λ level is changed figure place into q λ; μ=λ+1 expression λ's is secondary;
● α level is maximum level, and α level correspondence the highest q of N bit
αposition, β level, γ level ... corresponding figure place reduces successively; For example N=4 level * is 3=12, α level D
α 2d
α 1d
α 0three correspondences the highest D
11d
10d
9position, three D of β level
β 2d
β 1d
β 0corresponding time high D
8d
7d
6position,
● a level level switch JDWKG comprises variable connector DLKG and critical switches set U KGZ two classes, and this two classes switch can equivalent replacement, so if described somewhere a class switch wherein, namely described another kind of switch.
● for logarithm ADC, U
λ ybe the forward wave dynamic simulated voltage signal of λ level input, hereinafter to be referred as input voltage U
λ y, and before AC analogue voltage signal only appears at the front end circuit of α level, with the u α y of small letter, represent; The level current potential V λ G of take is bridge, input voltage U
λ ybe converted to a grade current potential V
λ Gand then be converted to digital signal D
λ (q-1)d
λ 0;
● for logarithm DAC, λ stages of digital signal D
λ (q-1)d
λ 0be converted to a grade current potential, level current potential is exactly to export forward analog voltage signal after ratio reduction, is called for short output voltage;
● input voltage and output voltage are collectively referred to as analog voltage;
● a full parallel model ADC of sub level is hereinafter to be referred as deserializer, and sampling holder is called for short to adopt protects device CB.
● physical circuit is too numerous to enumerate, and the circuit implementation procedure in the present invention is just for example;
● subscript is the character of reindexing not, as CB adopts guarantor's device, CB
βremain and adopt guarantor's device, subscript
βit is rank footnote; Subscript (Q-1)～0 represents (Q-1) rank, rank～0; Subscript (T-1)～0 represents (T-1) rank, rank～0; Subscript (q-1)～0 expression (q-1) position～0; Subscript (t-1)～0 expression (t-1) position～0; Subscript α, β, γ represent level;
● the circuit that dotted line circle is lived is a module, has a module name on dotted line frame angle.
If ● a symbol being defined is as V
1somewhere has re-started definition in the back, from this, carries out new definition;
Invention application content:
A kind of multistage parallel formula ADC and DAC based on voltage follow switch, it is characterized in that with voltage follow switch as signaling switch, transmission of signal or disabling signal, voltage follow switch is comprised of voltage follower (abbreviation follower) and the large module of electric power loop switch (abbreviation mains switch) two, mains switch is the electronic installation being placed on this follower working power loop (abbreviation electric power loop), can control by switch controlling signal (abbreviation control word) break-make of this follower electric power loop.
This follower is switched in working power under the state of (be called for short power supply logical) in voltage follow state, signal is inputted from in-phase end, the voltage of its output can accurately equal the voltage of its in-phase end, make the signal of input be sent to output (being called for short signal logical), when signal is logical, voltage drop is minimum (can be less than 10
-8v), from electronic technology angle, say and can be considered zero voltage drop or conducting resistance equals zero, close to Utopian short circuit conducting; Follower is cut off in working power under the state of (being called for short power supply disconnected), and its output is just signal blocker state (being called for short signal disconnected) with its in-phase end, and when signal is disconnected, output and its non-inverting resistance value greatly (can reach 10
9Ω), from electronic technology angle, say that can be considered resistance equals infinitely great, close to Utopian shutoff,
Follow switch signal when power supply is logical logical, when power supply is disconnected, signal is disconnected, so, follow switch and can control by control word the break-make of its follower electric power loop, thereby control the break-make in its follower signal loop.
By the design to mains switch control logic, can become critical switch S by following switch structure
λ g, critical switch S
λ glogical relation be: work as I
λ g=0 or I λ (g+1)=1 o'clock, critical switch S
λ gsignal is disconnected; Only when critical condition, that is, work as I
λ g=1 and I
λ (g+1)=0 o'clock, critical switch S
λ gsignal is logical; S
λ gcomprise S described later
λ g1, S
λ g2and S
λ g3critical switch etc. multiple structure.
One group of critical switch forms level level switch, level level switch JDWKG
λcomprise critical switches set (UKGZ
λ) and the critical switch of multichannel (abbreviation variable connector DLKG
λ), critical switches set is by the output of one group of critical switch and is unified into common port, all inputs of these critical switches form the input group of critical switches set, by one of them input of the direct gating of control word, are gating end; Variable connector is to consist of a decoder and a critical switches set, first by decoder, digital signal decoding is become after control word, then is gating end by one of them input of control word gating;
Follow switch application in ADC and DAC, can form m level * q position constant resistance chain type ADC, m level * q position constant resistance chain type DAC, two-stage logarithmic resistance chain type ADC, two-stage logarithmic resistance chain type DAC, multistage logarithmic resistance chain type ADC, multistage logarithmic resistance chain type DAC, digital logarithmic converter, digital antilogarithm transducer based on following switch.
Embodiment (its numbering is corresponding with accompanying drawing explanation numbering)
Embodiment 1.1----critical switch.Work as I
λ g=0 or I
λ (g+1)=1 o'clock, critical switch S
λ gsignal is disconnected; Only has the I of working as
λ g=1 and I
λ (g+1)=0 o'clock, critical switch S
λ gsignal is logical; S
λ gcomprise S described later
λ g1, S
λ g2and S
λ g3critical switch etc. multiple structure.Gating point S
λ Gcurrent potential be λ level G rank current potential V
λ G, be called the level current potential V of λ level
λ G.
Embodiment 1.2.1----S
λ g1class can't harm critical switch.Integrated transporting discharging wherein, end of oppisite phase and output short circuit and become follower.Triode VT1, VT3, VT0 and VT2 are arranged on to A
λ gelectric power loop on, only have the I of working as
λ g=1 and I
λ (g+1)=0 o'clock, A
λ gpower supply is logical (to be explained: work as I
λ g=1 makes VT1 and VT3 saturation conduction, and I
λ (g+1)=0 while making VT0 and VT2 saturation conduction, makes A
λ gpower supply is logical), make A
λ gsignal is logical; Otherwise, as long as I
λ g=0 or I
λ (g+1)=1, all can there is A
λ gpower supply is disconnected (to be explained: as long as I
λ g=0 will make VT1 and VT3 cut-off, same, as long as I
λ (g+1)=1 will make VT0 and VT2 cut-off), A at this moment
λ gwithout amplification, again because in-phase end input resistance is very big, so A
λ gsignal is disconnected.
In order to simplify circuit, VT0 and VT2 one of short circuit arbitrarily, VT1 and VT3 be one of short circuit arbitrarily also.
Embodiment 1.2.2---S
λ g2class can't harm critical switch.A wherein
λ gfor voltage follower, triode VT4, VT5, VT6, VT7, VT8, VT9 are arranged on to A
λ gelectric power loop on, only have equally the I of working as
λ g=1 and I
λ (g+1)=0 o'clock, A
λ gpower supply is logical (to be explained: work as I
λ g=1 makes VT6 and VT9 saturation conduction, has I simultaneously
λ (g+1)=0 makes VT5 and VT8 cut-off, thereby makes VT4 and VT7 saturation conduction), make A
λ gsignal is logical; Otherwise, as long as I
λ g=0 or I
λ (g+1)=1, A
λ gcapital power supply is disconnected (to be explained: as long as I
λ g=0 will make VT6 and VT9 cut-off, same, as long as I
λ (g+1)=1 will make VT5 and VT8 saturation conduction, collector potential V
5Cand V
8Cfor low, thereby make VT4 and VT7 cut-off), make A
λ gsignal is disconnected.
In order to simplify circuit, VT6 and VT9 one of short circuit arbitrarily, VT4 and VT7 be one of short circuit arbitrarily also.
The harmless critical switch (S of embodiment 1.2.3---broad sense
λ g3class).Because control A
λ gthe mains switch of on/off can have multiple design, so the definition of broad sense, KS1 and KS3 are high potential turn-on power switch, and KS0 and KS2 are electronegative potential turn-on power switch, only have the I of working as
λ g=1 and I
λ (g+1)=0 o'clock, make KS1 and KS3 conducting, and make KS0 and KS2 conducting, just can make A
λ gpower supply is logical, makes A
λ gsignal is logical; Otherwise, as long as I
λ g=0 or I
λ (g+1)=1, all can make KS1 and KS3 cut-off or make KS0 and KS2 cut-off, can make A
λ gpower supply is disconnected, so A
λ gsignal is disconnected.
Embodiment 1.2.4q position variable connector.S wherein
λ 0～S
λ (Q-1)be the critical switches in rank of λ level 0 rank～(Q-1), the square frame that frame is lived these critical switches is labeled as the critical switches set UKGZ λ of λ level; V
λ 0～V
λ (Q-1)be the rank input current potentials of λ level 0 rank～(Q-1); I
λ 0～I
λ (Q-1)be the rank control words of λ level 0 rank～(Q-1); d
λ 0～d
λ (q-1)it is the control end of λ level variable connector.Decoder JM
λby the digital signal decoding of control end, be the rank control word I of λ level 0 rank～(Q-1)
λ 0～I λ (Q-1), obtains the rank input current potential V of the 0th rank～(Q-1)
λ 0～V
λ (Q-1)gating end.
Embodiment 2.1---the m level * q position constant resistance formula logarithm ADC based on following switch.Interpretation principle for the sake of simplicity, in this example and embodiment 3.1, all sub levels all adopt q position, and at different levels in theory can be different figure places; Original input exchange signal u
α yafter front end circuit QZDL processes, become α level input voltage U
α y; λ level input voltage U
λ yscope be 0～V
p, λ level sub level AD#
λto λ level input voltage U
λ ycarry out AD conversion, by four module and process, completed:
1, level current potential V
λ Gform module; Q=2
q, the divider resistance chain R of λ level deserializer
λ (Q-1)～R
λ 0form λ level potential reference point V
λ (Q-1)～V
λ 0, correspondence is received comparator C in deserializer
λ (Q-1)～C
λ 1end of oppisite phase, λ level input voltage U
λ yreceive comparator C in deserializer
λ (Q-1)～C
λ 1in-phase end, with potential reference point V
λ (Q-1)～V
λ 0compare, obtain λ level comparison value I
λ (Q-1)～I
λ 1for I
λ (Q-1)～I
λ (G+1)=0, I
λ G～I
λ 1=1, I
λ Qfor permanent 0 value, I
λ 0for permanent 1 value, learn V
λ (G+1)> U
λ y> V
λ G, forming level current potential is V
λ Gmake comparison value I
λ (Q-1)～I
λ 1by encoder BM
λafter encoding, obtain a grade current potential V
λ Gdigital output value be D
λ (q-1)～D
λ 0; So far, with level current potential V
λ Gfor bridge, input voltage U
λ ybe converted to a grade current potential V
λ Gand then be converted to digital signal D
λ (q-1)d
λ 0;
2, level current potential V
λ Gtake out module; In AD##, except final stage, all need level current potential V
λ Gtake out as carrying out subordinate's conversion and prepare; The module that completes this work is exactly level level switch, comprises critical switches set UKGZ
λwith variable connector DLKG
λtwo classes, reference point of potential V
λ (Q-1)～V
λ 0one by one with switching point S
λ (Q-1)～S
λ 0carry out arithmetic connection; AD#
αin dotted line frame UKGZ
αwhat frame was lived is critical switches set graphical diagram, by the gating of aforesaid critical switch, controls, and determines gating point S
λ G; AD#
βin solid box DLKG
βwhat frame was lived is variable connector graphical diagram, by the gating of aforesaid variable connector, controls, and determines gating point S
λ G; AD#
γin solid box JDWKG
γthe device group that frame is lived has comprised variable connector and two kinds of graphical diagrams of critical switches set, and wildcard two class switches, control by the gating of aforesaid two class switches, determine gating point S
λ G; Gating point S
λ Gcorresponding to level current potential V
λ G.
3, inter-stage computing module.The input voltage U of λ level
λ ythrough λ level, adopt and protect device CB
λafter become steady state voltage U '
λ y, inter-stage is adopted and is protected device CB
λeffect be to make the input voltage of each sub level independent and stable within a sampling period, thereby make m the sub level can parallel running, form pipeline system conversion.The object of taking out level current potential is to carry out the conversion of next stage, establishes each sub level and changes figure place into q position, Q=2
q, resistance chain is by voltage V
pbe divided into Q decile, the component voltage Δ V such as every is fixed value Δ V=V
p/ Q; Level current potential V
λ Gto be less than and close to input voltage U
λ yreference point of potential, in the certainty of measurement of λ level, think V
λ G=U
λ y, by summer ∑
λcomplete and ask the voltage operational U of mantissa
λ x=U
λ y-V
λ G, mantissa's voltage U
λ xscope be 0～Δ V, then by amplifier FD
λmantissa's voltage signal is amplified to Q doubly, obtain U
(λ+1) y=U
μ y=Q*U
λ xso, U
μ yexpanded range to full scale 0～V
p, become the input voltage of μ level, enter μ level ADC
μcarry out measurement and the conversion of high extra fine grade.
4, logarithm modular converter, this routine logarithm modular converter has two kinds of analog conversion and digital conversions, and the prerequisite of digital conversion is by total input voltage U
α yconvert the digital signal of the quantization steps such as seniority top digit to, then by logarithm table look-up device, converted this high-order digit signal the digital signal of lower-order digit logarithmic quantization spacing to; Analog conversion is before α level input, with analog logarithmic converter, converts linear input voltage to logarithm input voltage, and ADC is actually and has converted logarithm input voltage to logarithmic quantization spacing digital signal;
Embodiment 2.2---and the T of front end circuit QZDL makes principle: when sampling executive signal arrives, order is adopted and protected device CB to original input exchange signal u
α yadopt guarantor, obtain an interchange that keeps fixing and adopt guarantor's signal u within the sampling period
g; Positive and negative arbiter ZFP
xto u
gcarry out polarity discriminating and processing, work as u
gduring > 0, make polarity register D
x=0, ZFP
xdifferentiation output signal U
g=u
g, work as u
gduring < 0, make D
x=1, U
g=-u
gso,, U
gonly has positive polarity U
g=| u
g|, claim positive input voltage U
g; Simulation logarithmic compression law module LOG is option, (LOG module has mature technology when adopting analog compress technique, to need LOG module, do not repeat, mention herein log law when compression comprise as A compression rule and the μ compression of logarithmic approximation compression rule restrain), α level input voltage U at this moment
α yequal the logarithmic compression law of Ug, what after the conversion of AD uniformly-spaced, obtain is the digital signal of logarithmic compression law; U when not adopting LOG module
α y=U
g, AD is converted to linear;
Embodiment 2.3---the positive and negative arbiter operation principle of signal
Work as u
gfor timing, YF
afor electronegative potential, D
x=0, S
xupper dialling makes u
gdirectly export U to
g; R
c5=R
c6make YF
bmultiplication factor equals to bear 1, works as u
gwhen negative, YF
afor high potential, D
x=1, S
xset aside and make u
gpass through YF
bthe anti-phase U that exports to
g;
Embodiment 3.1---the m level * q position constant resistance formula logarithm DAC based on following switch.
N position digital signal is allocated as follows by m level * q position:
(D (
n-1) ..., D
0)=(D
α (q-1)..., D
α 0), (D
β (q-1)..., D
β 0) ..., (D
m (q-1)..., D
m0), D is transported to corresponding level level switch control end to d: (d
α (q-1)..., d
α 0), (d β
(q-1)..., d
β 0) ..., (d
m(
q-1)..., d
m0),
λ level sub level DAC
λto λ stages of digital signal (D
λ (q-1)..., D
λ 0) carry out DA conversion and completed by four module:
1, level current potential V
λ Gform module.Q=2
q, the divider resistance chain R of λ level deserializer
λ (Q-1)～R
λ 0(first do not comprise half rank resistance R
λ Δ) formation λ level potential reference point V
λ (Q-1)～V
λ 0, receive digital signal (D
λ (q-1)..., D
λ 0) after, corresponding to the reference point of potential V of digital signal
λ Gfor level current potential;
2, level current potential V
λ Gtake out module.Need to be by the level current potential V of each grade
λ Gtake out, for asking for the output voltage V of every grade
Φ ψprepare; With the level current potential V in embodiment 2.1
λ Gtake out module and process identical;
3, inter-stage computing module.Level current potential V
λ Gwith output voltage V
Φ ψand reduction multiple ψ
λtriadic relation is: V
Φ ψ=V
λ G/ Ψ
λ, (notice Q=2
q), ψ wherein
λ=Q
(Φ-1), i.e. λ level reducer ψ
Φreduction multiple be ψ
Φ=Q
(Φ-1), Φ wildcard α, β, γ ..., m, and α, β, γ ... with numeric representation be α=1, β=2, γ=3 ... so,, with Φ, be expressed as which level, for example, γ level is 3rd level, Φ=3, Ψ
γ=Q
2; Compensator ∑
Φwith reducer ψ
Φalso can be with addition-ratio circuit ∑ ψ
Φcomplete; By all other V of level
Φ Ψwith total summer ∑
ψsummation, obtains always exporting analog voltage V
ψ;
4, logarithm modular converter.This routine logarithm modular converter is also to have two kinds of analog conversion and digital conversions, digital conversion is after receiving the digital signal of lower-order digit logarithmic quantization spacing, by antilogarithm table look-up device, convert this logarithm digital signal to the high-order quantization step digital signal that waits, in order to improve signal to noise ratio, can make half rankization to reference point of potential processes, antilogarithm table look-up device is changed into the antilogarithm table look-up device that improves half rank quantization step, this logarithm digital signal converts the high-order quantization step digital signal that waits to by this table look-up device, with the DAC of the quantization steps such as seniority top digit, convert analog signal to again, analog conversion is to have completed after digital-to-analogue conversion at DAC, then with analog antilogarithm transducer, converts this logarithmic mode analog signal to linear output voltage, linear DAC, in order to improve signal to noise ratio, also can make half rankization to reference point of potential and process, minimum quantization separation delta V=V
p/ Q
m, reference point of potential at different levels is all raised to Δ V/2, for this reason, as long as increase by one and half rank resistance R on zero potentials at different levels
λ Δ, be respectively: R
α Δ=R
α 1/ (Q
m-α *2), R
β Δ=R
β 1/ (Q
m-β *2) ..., R
m Δ=R
α 1/ (Q
m-m*2),
Embodiment 4---the two-stage logarithm chain ADC based on following switch.This logarithm chain ADC comprises two sub level: LAD#
αand LAD#
β, LAD#
αfor chopped-off head logarithm chain ADC, LAD#
βfor secondary logarithm chain ADC; Front end circuit is without Log module;
Chopped-off head LAD#
αcomplete the conversion of q position, log law resistance chain R
q～R
1and R
θby voltage 0～V
pbe divided into large section of Q+1, Q+2 potential point, excludes and V at 0 altogether
pafter, remaining V
q-1～V
θfor reference point of potential (claiming again point of quantification), be Q=2
qrank, with reference to current potential chain V
q-1～V
θbe designed to log law, V
q-1～V
1access corresponding chopped-off head comparator C
q-1～C
1end of oppisite phase, chopped-off head input voltage U
α yaccess the in-phase end of each chopped-off head comparator, obtain chopped-off head comparison value I
q-1～I
1, then after chopped-off head encoder BM coding, produce chopped-off head log law digital output signal D
q-1～D
0; By chopped-off head comparison value I
q-1～I
1or digital output signal D
q-1～D
0, controlled stage level switch JDWKG and obtaining corresponding to input voltage U
α ylevel current potential V
g, first measure input voltage U
α ybe which large section that belongs in chopped-off head current potential chain, obtain U
α ybigness scale result; Input voltage U
α yaccess chopped-off head summer ∑
q-1～∑
0serve as minuend, reference point of potential V
q-1～V
θcorrespondence is received ∑
q-1～∑
0serve as subtrahend, obtain difference voltage U
x (Q-1)～U
x0, difference voltage U
x (Q-1)～U
x0again by chopped-off head amplifier F
q-1～F
0, obtain computing voltage U
y (Q-1)～U
y0, corresponding to level current potential V
gdifference voltage be called mantissa's voltage U
xG(because of U
xGposition be random, cannot mark), corresponding to level current potential V
gcomputing voltage be called computing step voltage U
yG; Summer is obtained mantissa's voltage U
xG=U
α y-V
g, U
xGexcursion be (0～Δ V
g), Δ V
gthe quantization step that is called grade current potential, Δ V
g=(V
(G+1)-V
g), make amplifier F
gmultiplication factor be V
p/ Δ V
g, through amplifier F
gafter obtain computing step voltage U
yG, U
yG=U
xG *v
p/ Δ V
g, zoom into U
yGafter, change in voltage expanded range is to full scale 0～V
p, level level switch is by computing step voltage U
yGbus switches S is delivered in taking-up
αto secondary output.U
yGthrough adopting, protect device CB
βafter adopting guarantor, become secondary input voltage U
β y, then give the secondary accurate measurement that carries out, inter-stage is adopted and is protected device CB
βeffect be to make the input voltage of two-stage independent and stable within a sampling period, thereby make two sub levels can parallel running, form pipeline system conversion;
Secondary LAD#
βmajor part is secondary logarithm chain deserializer LBXQ
β, secondary to numerical expression resistance chain R '
t～R '
1form potential point V
pand V '
t-1～V '
0, get rid of V
pafter, V '
t-1～V '
0for secondary to numerical expression reference point of potential, V '
t-1～V '
1receive secondary comparator C '
t-1～C '
1corresponding end of oppisite phase, secondary input voltage U
β yreceive each secondary comparator in-phase end, obtain secondary comparison value I '
t-1～I '
1, through secondary encoder BM coding, obtain secondary log law digital output signal D '
t-1～D '
0; LAD#
αand LAD#
βtwo-stage completes the digital signal conversion of q+t position log law, D altogether
q-1～D
0for a high position, D '
t-1～D '
0for low level;
In order to improve signal to noise ratio and dynamic range of signals value, intend adopting the resistance chain of log law, make the resistance chain of two sub level LAD# α and LAD# β adopt log law design; The logarithmetics design analysis of chopped-off head and secondary resistance chain:
The logarithmetics design of chopped-off head resistance chain: LAD#
αresistance chain resistance be constant, so chain electric current I
αbe constant, make basic current potential V
θequal the minimum value that transducer is effectively surveyed, make basic resistance R
θ=V
θ/ I
α, R
a/ R
θ=η-1, R
afor and non-existent virtual starting resistance, chopped-off head chain resistance is all with R
afor rising, press large ratio η
tincrease progressively, claim large ratio resistance chain: R
1=R
a* η
t, R
2=R
a* η
2*T..., R
q-3=R
a* η
(Q-3) * T, R
q-2=R
a* η
(Q-2) * T, R
q-1=R
a* η
(Q-1) * T, large ratio resistance chain R
θ～R
qproduced large ratio current potential chain (V
j+1/ V
j=η
t) be: ground, V
θ, V
1=V
θ* η
t, V
2=V
θ* η 2
* T, V
3=V
θ* η
3*T..., V
q-2=V
θ* η
(Q-2) * T, V
q-1=V
θ* η
(Q-1) * T, V
q=V
θ* η
q*T=V
p, get rid of V
q=V
pafter point, Q reference point of potential (claiming again point of quantification) is altogether: V
θ, V
1..., V
q-1, because be less than V
θregion be that transducer is surveyed inactive area, so (V
1～V
θ～0) with V
θfor point of quantification, be labeled as (V
1～V
θ～0) → V
θ, the quantized interval of other point of quantification is: (V
2～V
1] → V
1, (V
3～V
2] → V
2..., (V
q-1～V
q-2] → V
q-2,, (V
q～V
q-1] → V
q-1; The point of quantification of chopped-off head is large ratio η
trough type, so the middle secondary meticulous type point of quantification that will insert T little ratio η;
The logarithmetics design of secondary resistance chain: LAD#
βresistance chain have T=2
tindividual resistance R '
1～R '
t, in chopped-off head, obtained mantissa's voltage U
xG=U
α y-V
g, U
xGexcursion be (0～Δ V
g), Δ V
g=(V
(G+1)-V
g), V
g=V
θ* η
g*T, V
(G+1)=V
θ* η
(G+1) * T, Δ V
gfor chopped-off head level current potential V
gquantization step; V in theory
g～V
(G+1)in to insert T fine quantization point in secondary, V
g～V
(G+1)fine quantization point be: V "
0=V
g=V
θ* η
g*T, V "
1=V
g* η
1, V "
2=V
g* η
2, V "
3=V
g* η
3..., V "
t-2=V
g* η
(T-2), V "
t-1=V
g* η
(T-1), according to ratio η geometric ratio, increase progressively, (V "
t=V
g* η
t=V
g+1for lower single order point of quantification in chopped-off head, get rid of outside insertion point), as long as this explanation secondary resistance chain meets geometric ratio, be related to η and take advantage of a coefficient, just can realize to mantissa's voltage to number conversion; In fact secondary conversion is not that fine quantization point is inserted into V
g～V
(G+1)in, but mantissa's voltage U of chopped-off head
xGtake out U
xGexcursion be (0～Δ V
g), through corresponding amplifier F
gchopped-off head mantissa voltage U after amplifying
xGbe expanded into chopped-off head computing step voltage U
yG, the multiplication factor that makes amplifier FG is V
p/ Δ V
g, U
yG=U
xG* V
p/ Δ V
g, change in voltage expanded range is to secondary full scale 0～V
p; Computing step voltage U
yGthrough adopting, protect device CB
βafter adopting guarantor, become secondary input voltage U
β y; And construct log law point of quantification in secondary resistance chain, be crucial, in secondary resistance chain, R
bfor the virtual resistance of setting arbitrarily, T chain resistance increases progressively according to ratio η geometric ratio: R '
1=R
b* η
1, R '
2=R
b* η
2, R '
3=R
b* η
3..., R '
t-2=RB* η
(T-2), R '
t-1=R
b* η
(T-1), R '
t=R
b* η
t, self-assembling formation T the current potential point of quantification increasing progressively according to ratio η geometric ratio: 0, V '
1=V
b* η
1, V '
2=V
b* η
2, V '
3=V
b* η
3..., V '
t-2=V
b* η
(T-2), V '
t-1=V
b* η
(T-1), its quantized interval is: (V '
1～0] → 0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1; And V '
t=V
pbe excluded outside this group point of quantification;
So far, this two-stage logarithm chain ADC has converted analog signal to numerical expression digital signal to, and signal to noise ratio is curve 3, and signal to noise ratio is constant; If on this basis, by basic resistance R
θbe adjusted into adjusting resistance R*
θ, R*
θ=R
θ～R
θ/ 15, and make R*
θthe minimum useful signal of=detector, by adjusting resistance R*
θreduce, some declines at small-signal end can to make signal to noise ratio curve, but dynamic range is increased, and signal to noise ratio is curve 4;
Embodiment 5.1---the two-stage logarithm chain DAC based on following switch, and the resistance chain of this DAC and reference potential chain are all logarithmic relationships; The log law digital signal receiving is: high-order D
q-1～D
0, low level D '
t-1～D '
0; High-order D
q-1～D
0correspondence is delivered to chopped-off head variable connector control end d
q-1～d
0, obtain chopped-off head level current potential V
g; Low level D '
t-1～D '
0correspondence is delivered to secondary variable connector control end d '
t-1～d '
0, obtain secondary level current potential V '
b, make b equal certain point in (0～T-1), V ' b is called secondary b rank reference point of potential, and the potential point being wherein strobed is secondary level current potential V '
b;
LDA#
βcomprise three parts: DZL
β, JDWKG ' and ∑
β U; DZL
βfor secondary logarithmic resistance chain, comprising: secondary to numerical expression. resistance chain R '
t～R '
1, secondary to numerical expression reference point of potential V '
t-1～V '
0, the logarithmetics design of secondary resistance chain is with embodiment 4.1;
Secondary resistance chain forms T reference point of potential V '
t-1, V '
t-2... V '
1, V '
0, its quantized interval is: (V '
1～0] → V '
0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1; The quantization step of known V ' b or title jump Δ V '
b=V '
b+1v '
b; Secondary level level switch JDWKG ' control end d '
t-1～d '
0receive low order digit signal D '
t-1～D '
0after, at secondary switch point S '
t-1～S '
0in determine a gating point S '
b, this gating point signalment is S '
b, gating point S '
bcorresponding potential point V '
bfor secondary level current potential V
β B, secondary level current potential V
β Bexcursion be T potential point V '
0, V '
1..., V '
t-2, V '
t-1, the quantized interval of each point is respectively: (V '
1～V '
0] → V '
0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1so, secondary level current potential V
β Bcorresponding analog voltage excursion is 0～V
p;
LDA#
αcomprise four parts: DZL
α, SJQH, J DWKG and ∑
aU; DZL
αfor chopped-off head logarithmic resistance chain, comprise that chopped-off head is to numerical expression resistance chain R
q～R
1and R
θ, chopped-off head is to numerical expression reference point of potential V
q-1～V
θ, the logarithmetics design and implementation example 4.1 of chopped-off head resistance chain is identical; Make g equal 0～(Q-1) in Arbitrary Digit, each chopped-off head potential point V
gcorrespondence connects three devices: summer ∑
g, reducer ψ
gwith switching point S
g, be called g branch road, potential point V
gwith potential point V
g+1voltage be called potential point V
gjump Δ V
g, triadic relation is Δ V
g=V
g+1-V
g;
With chopped-off head level current potential V
gduring addition, secondary level current potential V
β Bshould be with level current potential V
gmantissa voltage identity occur, notice secondary level current potential V
β Hcorresponding analog voltage excursion is 0～V
p, and change in voltage scope should be 0～Δ V
gjust reasonable, so corresponding to g rank current potential, should be by V
β Bexcursion by 0～V
preduce into 0～Δ V
g, just need to complete this task with a reducer ψ X, also be appreciated that the Δ V on every rank
gunequal, but geometric ratio variation, so every rank reducer Ψ
gthe reduction ratio ψ of (ψ capitalization)
g(ψ small letter) is also that geometric ratio changes, and makes ψ
g=Δ V
g/ V
p, secondary level current potential V
β Bbecome reduction value V
Ψ g, reduction is calculated as: V
ψ g=V
β B* Ψ
g=V
β B* Δ V
g/ V
pso change in voltage scope is by V
β B0～V
preduced into V
ψ g0～Δ V
g, reduction voltage V
ψ gbe exactly chopped-off head reference point of potential V
q-1～V
θin mantissa's voltage on g rank, wait for gating; Chopped-off head reference potential V
gas the rough analogue value, and corresponding reduction voltage V
Ψ gas V
gmantissa's voltage be the meticulous analogue value, V
gwith V
ψ gby summer ∑
gbe added, obtain the rough analogue value V of chopped-off head
gwith secondary meticulous analogue value V
ψ gsum, claims reference potential summing value V
∑ g, each examines current potential V chopped-off head
gthere is a reference potential summing value V in correspondence all
∑ gwait for output; As chopped-off head level level switch JDWKG control end d
q-1～d
0receive high-order digit signal D
q-1～D
0after, determined chopped-off head gating point S
g, by corresponding reference potential summing value V
∑ gas level current potential summing value U
∑ Goutput to summary device ∑
α U, summary device ∑
α Uin fact receive only unique level current potential summing value U
∑ G, as dac value U
α βoutput; So far, two-stage logarithm chain DAC converts.
Perplexingly be, why does the logarithm of negating also use logarithm chain? in fact imagine, analog signal enters to become digital signal from logarithm chain, and then intactly from the logarithm chain of same configuration out, nature can be reduced into original analog signal to digital signal.Such as U
α y=V '
3through logarithm chain, AD converts D to
2d
1d
0=000 and D '
3d '
2d '
1d '
0=0011; And D
2d
1d
0and D '
3d '
2d '
1d '
0after logarithm chain DA conversion reduction or V '
3; In fact the inverse process of logarithm-antilogarithm is that inverse process by AD-DA completes.
Embodiment 5.2---the two-stage logarithm chain DAC based on following half stepwise point of quantification of switch, the basic principle of this DAC is identical with embodiment 5.1, difference is that the setting of reference point of potential carried out half rankization and processed, (the 2nd page of the half stepwise point of quantification of narrating in the reference point of potential employing theory analysis of this DAC, the 15th row), make reference point of potential move half rank on all and be called for short half rank reference point, resistance moves half rank on all and is called for short half rank resistance; Use U
grepresent chopped-off head half rank reference point, P
grepresent chopped-off head half rank resistance, U '
brepresent secondary half rank reference point, P '
brepresent secondary half rank resistance; With the corresponding relation of former resistance chain be: U
g→ V
g, P
g→ R
g, U '
b→ V '
b, P '
b→ R '
b; So-called half rank make reference point of potential move half rank on the original basis exactly, and computational methods are:
Reference point of potential all raises half rank, becomes: chopped-off head half rank reference point U
g=(V
g+ V
g* η)/2, chopped-off head half rank resistance P
g=(R
g+ R
g* η)/2; Secondary half rank reference point U '
b=(V '
b+ V '
b* η)/2, secondary half rank resistance: P '
b=(R '
b+ R '
b* η)/2; Like this, reference point of potential and resistance all raise half rank;
Behind two-stage logarithm chain DAC half rank, the two-stage logarithm chain DAC of half stepwise point of quantification, behind reference potential rank thirty, quantization step is original half, can make quantization error be reduced to original 1/4, [S
j/ N
j]
dBimprove 10log4=6.02dB.
Embodiment 6.1---the digital logarithmic converter based on following switch.
For a linear analogue signal, the two-stage of first describing with the embodiment 4.1 altogether logarithm chain ADC of N position converts N position log law digital signal to, linear DAC by a N position converts outputting analog signal to again, and this outputting analog signal is exactly the analog signal of log law.
Embodiment 6.2---the digital antilogarithm transducer based on following switch.
For a log law analog signal, first with the linear ADC of a N position, convert N position log law digital signal to, then convert outputting analog signal to a N position two-stage logarithm chain DAC, this outputting analog signal is exactly linear analogue signal.It is identical that N position two-stage logarithm chain DAC describes with embodiment 5.1.
Embodiment 7.1---based on three grades that follow switch above logarithm chain ADC.Identical with two-stage logarithm chain ADC principle, just by the secondary final stage that transforms into, and increase by one or several intergrade identical with chopped-off head structure, as secondary, the third level, the fourth stage etc.
Embodiment 7.2---based on three grades that follow switch above logarithm chain DAC.Identical with two-stage logarithm chain DAC principle, newly-increased level, with secondary identical, comprises resistance chain, level level switch and corresponding reducer group; A plurality of newly-increased levels are also like this.
Accompanying drawing explanation
Convenient in order to check, have a mind to embodiment is corresponding with the numbering of accompanying drawing.Explaining in a place of same numeral is rear until effective before this label being appended to explanation; In figure, all subscript λ g are called λ level g rank;
Fig. 1 .1 is the graphical diagram of critical switch, and wherein subscript λ g is λ level g rank, rectangular block S
λ gbe the critical switch in λ level g rank, V
λ gbe λ level g rank signaling points, I
λ gbe λ level g rank controlling values, I
λ (g+1)be λ level g+1 rank controlling values, S
λit is λ level bus switches; V
λ Git is λ level bus potential.
Fig. 1 .2.1 is S
λ g1class can't harm critical on-off principle figure, wherein A
λ gfor follower; V
λ g,i
λ g,i
λ (g+1), S
λ,v
λ Gidentical with Fig. 1 .1; VT1 and VT3 are NPN type triode, and VT0 and VT2 are positive-negative-positive triode; + V
pfor positive source ,-V
nfor power cathode; Circuit in dotted line frame has formed S
λ g1class can't harm critical switch.
Fig. 1 .2.2 is S
λ g2class can't harm critical on-off principle figure, wherein A
λ g, V
λ g, I
λ g, I
λ (g+1), S
λ,+V
p,-V
nidentical with Fig. 1 .2.1; VT4 to VT9 is NPN type triode, V
5Cand V
8Cbe respectively the collector potential of VT5 and VT8; R
λfor resistance; Circuit in dotted line frame has formed S
λ g2class can't harm critical switch.
Fig. 1 .2.3 is the harmless critical switch (S of broad sense
λ g3class) schematic diagram, wherein A
λ gfor follower; V
λ g, I
λ g, I
λ (g+1), S
λ, V
λ Gidentical with Fig. 1 .1; KS1 and KS3 are high potential turn-on power switch, and KS0 and KS2 are electronegative potential turn-on power switch.
Fig. 1 .2.4 is q position variable connector schematic diagram.S wherein
λ 0～S
λ (Q-1)be the critical switches in rank of λ level 0 rank～(Q-1), the square frame that frame is lived these critical switches is labeled as the critical switches set LJKGZ of λ level
λ; V
λ 0～V
λ (Q-1)be the rank input current potentials of λ level 0 rank～(Q-1); I
λ 0～I
λ (Q-1)be the rank control words of λ level 0 rank～(Q-1); d
λ 0～d
λ (q-1)it is the control end of λ level variable connector.Frame lives in these critical switches set UKGZ
λwith decoder JM
λdotted line collimation mark be designated as λ level variable connector DLKG
λ;
Fig. 2 .1 is 4 grades * 3 the constant resistance formula logarithm ADC schematic diagrams based on following switch.In this explanation with α, the β, γ, δ and the m that have occurred in λ wildcard figure; u
α yfor original input exchange signal; QZDL is front end circuit; U
λ yit is λ level input voltage; R
λ 7～R
λ 0it is λ level divider resistance chain; V
λ 7～V
λ 0it is λ level potential reference point; C
λ 7～C
λ 1it is λ level comparator; I
λ 7～I
λ 1it is λ level comparison value; I
λ 8for permanent 0 value, I
λ 0for permanent 1 value, D
λ 2～D
λ 0it is λ stages of digital output valve; V
pfor positive source; BM
λit is λ level encoder; S
α 7～S
α 0be the critical switch switching point of α level, frame lives in S
α 7～S
α 0with controlling value I
α 8～I
α 0dotted line frame UKGZ
αfor critical switches set, (I
λ gthere are two names, in comparator, claim comparison value, and be control action in level level switch, claim controlling value, allly appear at two local I
λ gjust name is different, but both are the same values that are communicated with wire, I ' below
λ g, I
g, I '
galso be like this); S
β 7～S
β 0be β level variable connector switching point, d
λ 2～d
λ 0be the control end of λ level variable connector, frame lives in S
β 7～S
β 0and d
β 2～d
β 0solid box DLKG
βfor variable connector; S
γ 7～S
γ 0be γ level level level switch point, frame lives in S
γ 7～S
γ 0and I
γ 8～I
γ 0and d
γ 2～d
γ 0solid box JDWKG
γfor level level switch, can the critical switches set of wildcard and variable connector; S
λit is λ level level level switch bus; V
λ G. be λ level level current potential; ∑
λit is λ level summer; U
λ xbe mantissa's voltage of λ level, FD
λit is λ level amplifier; U
μ yfor amplifying signal is mantissa's voltage U
λ xvalue of magnification, CB
λfor λ level is adopted guarantor's device; Dotted line frame AD#
λλ level sub level for logarithm ADC; GS is voltage follower; α level input voltage U
α yit is again total input voltage;
Fig. 2 .2 is front end circuit QZDL block diagram, original input exchange signal u
α y; Adopt and protect device CB; Interchange is adopted and is protected signal u
g; Positive and negative arbiter ZFP
x; Positive input voltage U
g; Property register D
x; Simulation logarithmic compression law module LOG; α level input voltage U
α y;
Fig. 2 .3 is the positive and negative arbiter schematic diagram of signal, and dotted line frame ZFP is positive and negative arbiter; u
g, U
g, D
xthe same; Operational amplifier YF comprises: positive and negative comparator YF
awith inverter YF
b; Inverter input resistance and feedback resistance R
c5, R
c6; Phase-veversal switch S
x;
Fig. 3 .1 is 3 the constant resistance formula logarithm DAC schematic diagrams of m level * based on following switch.That had explained has: UKGZ
α; DLKG
β; V
λ G; V '
λ G; V
r; R
λ 7～R
λ 0; V
λ 7～V
λ 0; I
λ 8～I
λ 0; S
λ; CB
λ; GS; By Fig. 2 .1 middle rank level switch JDWKG
γthe subscript of all symbols changes m into by γ, has just become level level switch JDWKG
m; What need new interpretation has: DA#
λbe λ sub level logarithm DAC; Solid box JM
αbe α level decoder, d
α 2～d
α 0for JM
αinput, the controlling value I obtaining after decoding
α 7～I
α 1determined level current potential gating point S
α G, JM
α+ UKGZ
α=DLKG
αso, d
α 2～d
α 0be JM
αinput, be again variable connector DLKG
αcontrol end; ψ
Φit is λ level reducer; V
Φ ψbe λ level analog output signal voltage, be called for short output voltage V
Φ ψ; ∑
ψfor total summer; V
ψfor total output analog voltage; Dotted line resistance R
λ Δbe half rank resistance;
Fig. 3 .2.1 is that triangle GS is voltage follower graphical diagram, and output voltage equals input voltage, is all U
x2, but improved load capacity, with triangle, in institute's drawings attached, represent this device, because implication is simple, without mark GS;
Fig. 3 .2.2 is ratio reducer ψ
xgraphical diagram; ψ is reducer symbol (Ψ capitalization), and subscript X is asterisk wildcard, and reduction ratio is ψ
x(ψ small letter is not marked in figure), input signal U
x1, output signal U
x2with reduction ratio ψ
xtriadic relation is: U
x2=U
x1/ ψ
x;
Fig. 3 .2.3 is ratio reducer ψ X schematic diagram; Wherein integrated transporting discharging GS is Fig. 3 .2.1 voltage follower, R
x1and R
x2form bleeder circuit, because voltage follower GS be take in-phase end as input, disconnected for void, electric current is considered as 0, so R
x1and R
x2middle electric current is equal, obtains dividing potential drop pass to be: U
x2=U
x1* R
x2/(R
x1+ R
x2), make ψ
x=(R
x1+ R
x2)/R
x2so, U
x2=U
x1/ ψ
x;
Fig. 4 is the two-stage logarithm chain ADC schematic diagram based on following switch, and the resistance chain of this ADC and reference potential chain are all logarithmic relationships, so claim logarithm chain ADC, logarithm chain ADC symbolically is LAD##, and it comprises two sub level: LAD#
αand LAD#
β, LAD#
αfor chopped-off head logarithm chain ADC, LAD#
βfor secondary logarithm chain ADC; The label single quotation marks of secondary i.e. β level ' represent, and do not have in label ' for chopped-off head be the label of α level;
LAD#
αcomprise three parts: LBXQ
α, JDWKG and QHFD; LBXQ
αfor chopped-off head logarithm chain deserializer, comprising: chopped-off head is to numerical expression resistance chain R
q～R
1and R
θ, chopped-off head is to numerical expression reference point of potential V
q-1～V
θ, chopped-off head comparator C
q-1～C
1, chopped-off head comparison value I
q-1～I
1, chopped-off head encoder BM, chopped-off head log law digital output signal D
q-1～D
0; QHFD amplifies computing circuit for summation, comprising: chopped-off head summer ∑
q-1～∑
0, difference voltage U
x (Q-1)～U
x0, amplifier F
q-1～F
0, computing voltage U
y (Q-1)～U
γ 0; Accurate computing step voltage U '
yG; Computing step voltage U
yG; JDWKG is level level switch, comprising: switching point S
(Q-1)～S
0; Variable connector control end d
q-1～d
0; Chopped-off head controlling value I
q-1～I
1, permanent 0 value I
q, permanent 1 value I
0; Bus switches S
α;
LAD#
βmajor part is secondary logarithm chain deserializer LBXQ
β, comprising: secondary to numerical expression resistance chain R '
t～R '
1, secondary to numerical expression reference point of potential V '
t-1～V '
0with secondary input voltage U
β yreceive respectively secondary comparator C '
t-1～C '
1end of oppisite phase and in-phase end, obtain secondary comparison value I '
t-1～I '
1, through secondary encoder BM ' coding, obtain secondary digital output signal D '
t-1～D '
0; Adopt and protect device CB
β; Accurate computing step voltage U '
yG, computing step voltage U
yG, secondary input voltage U
β y;
Fig. 5 is the two-stage logarithm chain DAC schematic diagram based on following switch, and the resistance chain of this DAC and reference potential chain are all logarithmic relationships, so claim logarithm chain DAC, logarithm chain DAC symbolically is LDA##, and it comprises two sub level: LDA#
αand LDA#
β, LDA#
αfor chopped-off head logarithm chain DAC, LDA#
βfor secondary logarithm chain DAC; The label single quotation marks of the secondary i.e. β level of this figure ' represent, and do not have in label ' for chopped-off head be the label of α level;
LDA#
αcomprise four parts: DZL
α, SJQH, JDWKG and ∑
aU; DZL
αfor chopped-off head logarithmic resistance chain, comprising: chopped-off head is to numerical expression resistance chain R
q～R
1and R
θ, chopped-off head is to numerical expression reference point of potential V
q-1～V
θ; SJQH, for reduction summation module, comprising: reducer ψ
q-1～ψ
0, secondary level current potential reduction value V
Ψ (Q-1)～V
Ψ 0, summer ∑ Q
-1～∑
0, reference potential summing value V
∑ (Q-1)～V
∑ 0, follower GS; J DWKG is chopped-off head level level switch, comprising: chopped-off head controlling value I
q-1～I
1, the permanent 0 value I of chopped-off head
q, the permanent 1 value I of chopped-off head
0, chopped-off head switching point S
(Q-1)～S
0, chopped-off head variable connector control end d
q-1～d
0; ∑
aUfor summarizing module, comprising: summary device ∑
α U, level current potential summing value U
∑ (Q-1)～U
∑ 0, gating point pressure drop offset V
r; Analog voltage output valve U
α β,
LDA#
βcomprise three parts: DZL
β, JDWKG ' and ∑
β U; DZL
βfor secondary logarithmic resistance chain, comprising: secondary to numerical expression resistance chain R
t～R
1, secondary to numerical expression reference point of potential V
t-1～V
0; Level level switch JDWKG ' comprising: secondary controlling value I '
t-1～I '
1, secondary permanent 0 value I '
t, secondary permanent 1 value I '
0, secondary switch point S '
(T-1)～S '
0, secondary variable connector control end d '
t-1～d '
0.
Claims (10)
1. multistage parallel formula ADC and the DAC based on voltage follow switch, it is characterized in that: use voltage follow switch as signaling switch, transmission of signal or disabling signal, voltage follow switch is comprised of the large module of follower mains switch two, mains switch is the electronic installation being placed on this follower electric power loop, can control by control word the break-make of this follower electric power loop, this follower under the logical state of power supply in voltage follow state, signal is inputted from in-phase end, the voltage of its output can accurately equal the voltage of its in-phase end, make the signal of input be sent to output, for signal leads to, when signal is logical, voltage drop is minimum, close to Utopian short circuit conducting, follower is under the disconnected state of power supply, and its output is just signal blocker state with its in-phase end, and disconnected for signal, when signal is disconnected, output and its non-inverting resistance value are very big, close to Utopian shutoff,
Follow switch signal when power supply is logical logical, when power supply is disconnected, signal is disconnected, so, follow switch and can control by control word the break-make of its follower electric power loop, thereby control the break-make in its follower signal loop.
2. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: by the design to mains switch control logic, can become critical switch S by following switch structure
λ g, critical switch S
λ glogical relation be: work as I
λ g=0 or I
λ (g+1)=1 o'clock, critical switch S
λ gsignal is disconnected; Only when critical condition, that is, work as I
λ g=1 and I λ
(g+1)=0 o'clock, critical switch S
λ gsignal is logical.
3. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the harmless critical switch of broad sense, only has the I of working as
λ g=1 and I
λ (g+1)=0 o'clock, make high potential turn-on power K switch S1 and KS3 conducting, and make electronegative potential turn-on power K switch S0 and KS2 conducting, just can make A
λ gpower supply is logical, makes A
λ gsignal is logical; Otherwise, as long as I
λ g=0 or I
λ (g+1)=1, all can make KS1 and KS3 cut-off or make KS0 and KS2 cut-off, can make A
λ gpower supply is disconnected, so A
λ gsignal is disconnected, in order to simplify circuit, and KS0 and KS2 one of short circuit arbitrarily, KS1 and KS3 be one of short circuit arbitrarily also.
4. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: one group of critical switch forms a level level switch, level level switch JDWKG
λcomprise critical switches set LJKGZ
λwith variable connector DLKG
λ, critical switches set is by the output of one group of critical switch and is unified into common port, all inputs of these critical switches form the input group of critical switches set, by one of them input of the direct gating of control word, are gating end; Variable connector is to consist of a decoder and a critical switches set, first by decoder, digital signal decoding is become after control word, then is that gating end is communicated with common port by an input in the critical switches set of control word gating.
5. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: q position variable connector, wherein S
λ 0～S
λ (Q-1)be the critical switches in rank of λ level 0 rank～(Q-1), decoder JM
λby control end d
λ 0～d
λ (q-1)digital signal decoding be the rank control word I of λ level 0 rank～(Q-1)
λ 0～I
λ (Q-1), obtain the rank input current potential V of the 0th rank～(Q-1)
λ 0～V
λ (Q-1)gating end.
6. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the m level * q position constant resistance formula logarithm ADC based on following switch, original input exchange signal u
α yafter front end circuit QZDL processes, become α level input voltage U
α y; λ level input voltage U
λ yscope be 0～V
p, λ level sub level AD#
λto λ level input voltage U
λ ycarry out AD conversion, by four module and process, completed:
(1), level current potential V
λ Gform module, Q=2
q, the divider resistance chain R of λ level deserializer
λ (Q-1)～R
λ 0form λ level potential reference point V
λ (Q-1)～V
λ 0, correspondence is received comparator C in deserializer
λ (Q-1)～C
λ 1end of oppisite phase, λ level input voltage U
λ yreceive comparator C in deserializer
λ (Q-1)～C
λ 1in-phase end, with potential reference point V
λ (Q-1)～V
λ 0compare, obtain λ level comparison value I
λ (Q-1)～I
λ 1for I
λ (Q-1)～I
λ (G+1)=0, I
λ G～I
λ 1=1, I
λ Qfor permanent 0 value, I
λ 0for permanent 1 value, learn V
λ (G+1)> U
λ y> V
λ G, forming level current potential is V
λ G; Make comparison value I
λ (Q-1)～I
λ 1by encoder BM
λafter encoding, obtain a grade current potential V
λ Gdigital output value be D
λ (q-1)～D
λ 0; So far, with level current potential V
λ Gfor bridge, input voltage U
λ ybe converted to a grade current potential V
λ Gand then be converted to digital signal D
λ (q-1)d
λ 0;
(2), level current potential V
λ Gtake out module, in AD##, except final stage, all need level current potential V
λ Gtake out as carrying out subordinate's conversion and prepare; The module that completes this work is exactly level level switch, comprises critical switches set LJKGZ
λwith variable connector DLKG
λtwo classes, reference point of potential V
λ(
q-1)～V
λ 0one by one with switching point S
λ (Q-1)～S
λ 0carry out arithmetic connection; AD#
αin dotted line frame LJKGZ
αwhat frame was lived is critical switches set graphical diagram, by the gating of aforesaid critical switch, controls, and determines gating point S
λ G; AD#
βin solid box DLKG
βwhat frame was lived is variable connector graphical diagram, by the gating of aforesaid variable connector, controls, and determines gating point S
λ G; AD#
γin solid box JDWKG
γthe device group that frame is lived has comprised variable connector and two kinds of graphical diagrams of critical switches set, and wildcard two class switches, control by the gating of aforesaid two class switches, determine gating point S
λ G; Gating point S
λ Gcorresponding to level current potential V
λ G.
(3), inter-stage computing module, the input voltage U of λ level
λ ythrough λ level, adopt and protect device CB
λafter become steady state voltage U '
λ Yinter-stage is adopted and is protected device CB
λeffect be to make the input voltage of each sub level independent and stable within a sampling period, thereby make m the sub level can parallel running, form pipeline system conversion.The object of taking out level current potential is to carry out the conversion of next stage, establishes each sub level and changes figure place into q position, Q=2
q, resistance chain is by voltage V
pbe divided into Q decile, the component voltage Δ V such as every is fixed value Δ V=V
p/ Q; Level current potential V
λ Gto be less than and close to input voltage U
λ yreference point of potential, in the certainty of measurement of λ level, think V
λ G=U
λ y, by summer ∑
λcomplete and ask the voltage operational U of mantissa
λ x=U
λ y-V
λ G, mantissa's voltage U
λ xscope be 0～Δ V, then by amplifier FD
λmantissa's voltage signal is amplified to Q doubly, obtain U
(λ+1)γ=U
μ y=Q*U
λ xso, U
μ yexpanded range to full scale 0～V
p, become the input voltage of μ level, enter μ level ADC
μcarry out measurement and the conversion of high extra fine grade.
(4), logarithm modular converter, this routine logarithm modular converter has two kinds of analog conversion and digital conversions, the prerequisite of digital conversion is by total input voltage U
α yconvert the digital signal of the quantization steps such as seniority top digit to, then by logarithm table look-up device, converted this high-order digit signal the digital signal of lower-order digit logarithmic quantization spacing to; Analog conversion is before α level input, with analog logarithmic converter, converts linear input voltage to logarithm input voltage, and ADC is actually and has converted logarithm input voltage to logarithmic quantization spacing digital signal.
7. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the m level * q position constant resistance formula logarithm DAC based on following switch, N position digital signal is allocated as follows by m level * q position:
(D
(N-1)..., D
0)=(D
α (q-1)..., D
α 0), (D
β (q-1)..., D
β 0) ..., (D
m (q-1)..., D
m0), D is transported to corresponding level level switch control end to d: (d
α (q-1)..., d
α 0), (d
β (q-1)..., d
β 0) ..., (d
m (q-1)..., d
m0), λ level sub level DAC
λto λ stages of digital signal (D
λ (q-1)..., D
λ 0) carry out DA conversion and completed by four module and process:
(1), level current potential V
λ Gform module, Q=2
q, the divider resistance chain R of λ level deserializer
λ (q-1)～R
λ 0, form λ level potential reference point V
λ (Q-1)～V
λ 0, receive digital signal (D
λ (Q-1)..., D
λ 0) after, corresponding to the reference point of potential V of digital signal
λ Gfor level current potential;
(2), level current potential V
λ Gtake out module, need to be by the level current potential V of each grade
λ Gtake out, for asking for the output voltage V of every grade
Φ Ψprepare; With the level current potential V in embodiment 2.1
λ Gtake out module and process identical;
(3), inter-stage computing module, level current potential V
λ Gwith output voltage V
φ Ψand reduction multiple ψ
λtriadic relation is: V
Φ ψ=V
λ G/ ψ
λ, ψ λ=Q wherein
(Φ-1), i.e. λ level reducer ψ
Φreduction multiple be ψ
Φ=Q
(Φ-1), Φ wildcard α, β, γ ..., m, and α, β, γ ... with numeric representation be α=1, β=2, γ=3 ... so,, with Φ, be expressed as which level, for example, γ level is 3rd level, Φ=3, Ψ
γ=Q
2; Compensator ∑
Φ γwith reducer ψ
Φalso can be with addition-ratio circuit ∑ ψ
Φcomplete; By all other V of level
Φ ψwith total summer ∑
ψsummation, obtains always exporting analog voltage V
ψ;
(4), logarithm modular converter, this routine logarithm modular converter is also to have two kinds of analog conversion and digital conversions, digital conversion is after receiving the digital signal of lower-order digit logarithmic quantization spacing, by antilogarithm table look-up device, convert this logarithm digital signal to the high-order quantization step digital signal that waits, in order to improve signal to noise ratio, can make half rankization to reference point of potential processes, antilogarithm table look-up device is changed into the antilogarithm table look-up device that improves half rank quantization step, this logarithm digital signal converts the high-order quantization step digital signal that waits to by this table look-up device, with the DAC of the quantization steps such as seniority top digit, convert analog signal to again, analog conversion is to have completed after digital-to-analogue conversion at DAC, then with analog antilogarithm transducer, converts this logarithmic mode analog signal to linear output voltage, linear DAC, in order to improve signal to noise ratio, also can make half rankization to reference point of potential and process, minimum quantization separation delta V=V
p/ Q
m, reference point of potential at different levels is all raised to Δ V/2, for this reason, as long as increase by one and half rank resistance R on zero potentials at different levels
λ Δ, be respectively: R
α Δ=R
α1/ (Q
m-α *2), R
β Δ=R
β 1/ (Q
m-β *2) ..., R
m Δ=R
α 1/ (Q
m-m*2).
8. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the two-stage logarithm chain ADC based on following switch, this logarithm chain ADC comprises two sub level: LAD#
αand LAD#
β, LAD#
αfor chopped-off head logarithm chain ADC, LAD#
βfor secondary logarithm chain ADC; Front end circuit is without Log module;
Chopped-off head LAD#
αcomplete the conversion of q position, log law resistance chain R
q～R
1and R
θby voltage 0～V
pbe divided into large section of Q+1, Q+2 potential point altogether, excludes after 0 and VP, is left V
q-1～V
θfor reference point of potential, be Q=2
qrank, with reference to current potential chain V
q-1～V
θbe designed to log law, V
q-1～V
1access corresponding chopped-off head comparator C
q-1～C
1end of oppisite phase, chopped-off head input voltage U
α yaccess the in-phase end of each chopped-off head comparator, obtain chopped-off head comparison value I
q-1～I
1, then after chopped-off head encoder BM coding, produce chopped-off head log law digital output signal D
q-1～D
0; By chopped-off head comparison value I
q-1～I
1or digital output signal D
q-1～D
0, controlled stage level switch JDWKG and obtaining corresponding to input voltage U
α ylevel current potential V
g, first measure input voltage U
α ybe which large section that belongs in chopped-off head current potential chain, obtain U
α ybigness scale result; Input voltage U
α yaccess chopped-off head summer ∑
q-1～∑
0serve as minuend, reference point of potential V
q-1～V
θcorrespondence is received ∑
q-1～∑
0serve as subtrahend, obtain difference voltage U
x (Q-1)～U
x0, difference voltage U
x (Q-1)～U
x0again by chopped-off head amplifier F
q-1～F
0, obtain computing voltage U
y (Q-1)～U
y0, corresponding to level current potential V
gdifference voltage be called mantissa's voltage U
xG, corresponding to level current potential V
gcomputing voltage be called computing step voltage U
yG; Summer is obtained mantissa's voltage U
xG=U
α y-V
g, U
xGexcursion be (0～Δ V
g), Δ V
gthe quantization step that is called grade current potential, Δ V
g=(V
(G+1)-V
g), make amplifier F
gmultiplication factor be V
p/ Δ V
g, through amplifier F
gafter obtain computing step voltage U
γ G, U
yG=U
xG* V
p/ Δ V
g, zoom into U
yGafter, change in voltage expanded range is to full scale 0～V
p, level level switch is by computing step voltage U
yGbus switches S is delivered in taking-up
αto secondary output.U
yGthrough adopting, protect device CB
βafter adopting guarantor, become secondary input voltage U
β y, then give the secondary accurate measurement that carries out, inter-stage is adopted and is protected device CB
βeffect be to make the input voltage of two-stage independent and stable within a sampling period, thereby make two sub levels can parallel running, form pipeline system conversion;
Secondary LAD#
βmajor part is secondary logarithm chain deserializer LBXQ
β, secondary to numerical expression resistance chain R '
t～R '
1form potential point V
pand V '
t-1～V '
0, get rid of V
pafter, V '
t-1～V '
0for secondary to numerical expression reference point of potential, V '
t-1～V '
1receive secondary comparator C '
t-1～C '
1corresponding end of oppisite phase, secondary input voltage U
β yreceive each secondary comparator in-phase end, obtain secondary comparison value I '
t-1～I '
1, through secondary encoder BM ' coding, obtain secondary log law digital output signal D '
t-1～D '
0; LAD#
αand LAD#
βtwo-stage completes the digital signal conversion of q+t position log law, D altogether
q-1～D
0for a high position, D '
t-1～D '
0for low level;
In order to improve signal to noise ratio and dynamic range of signals value, intend adopting the resistance chain of log law, make two sub level LAD#
αand LAD#
βresistance chain adopt log law design; The logarithmetics design analysis of chopped-off head and secondary resistance chain:
The logarithmetics design of chopped-off head resistance chain: LAD#
αresistance chain resistance be constant, so chain electric current I
αbe constant, make basic current potential V
θequal the minimum value that transducer is effectively surveyed, make basic resistance R
θ=V
θ/ I
α, R
a/ R
θ=η-1, R
afor and non-existent virtual starting resistance, chopped-off head chain resistance is all with R
afor rising, press large ratio η
tincrease progressively, claim large ratio resistance chain: R
1=R
a* η
t, R
2=R
a* η 2
* T..., R
q-3=R
a* η
(Q-3) * T, R
q-2=R
a* η
(Q-2)
* T, R
q-1=R
a* η
(Q-1) * T, large ratio resistance chain R
θ～R
qproduced large ratio current potential chain (V
j+1/ V
j=η
t) be: ground, V
θ, V
1=V
θ* η
t, V
2=V
θ* η
2*T, V
3=V
θ* η
3*T..., V
q-2=V
θ* η
(Q-2) * T, V
q-1=V
θ* η
(Q-1) * T, V
q=V
θ*
η Q*T=V
p, get rid of V
q=V
pafter point, Q reference point of potential (claiming again point of quantification) is altogether: V
θ, V
1..., V
q-1, because be less than V
θregion be that transducer is surveyed inactive area, so (V
1～V
θ～0) with V
θfor point of quantification, be labeled as (V
1～V
θ～0) → V
θ, the quantized interval of other point of quantification is: (V
2～V
1] → V
1, (V
3～V
2] → V
2..., (V
q-1～V
q-2] → V
q-2,, (V
q～V
q-1] → V
q-1; The point of quantification of chopped-off head is large ratio η
trough type, so the middle secondary meticulous type point of quantification that will insert T little ratio η;
The logarithmetics design of secondary resistance chain: LAD#
βresistance chain have T=2
tindividual resistance R '
1～R '
t, in chopped-off head, obtained mantissa's voltage U
xG=U
α y-V
g, U
xGexcursion be (0～Δ V
g), Δ V
g=(V
(G+1)-V
g), V
g=V
θ* η
g*T, V
(G+1)=V
θ* η
(G+1) * T, Δ V
gfor chopped-off head level current potential V
gquantization step; V in theory
g～V
(G+1)in to insert T fine quantization point in secondary, V
g～V
(G+1)fine quantization point be: V "
0=V
g=V
θ* η
g*T, V "
1=V
g* η
1, V "
2=V
g* η
2, V "
3=V
g* η
3..., V "
t-2=VG* η
(T-2), V "
t-1=V
g* η
(T-1), according to ratio η geometric ratio, increase progressively, (V "
t=VG* η
t=V
g+1for lower single order point of quantification in chopped-off head, get rid of outside insertion point), as long as this explanation secondary resistance chain meets geometric ratio, be related to η and take advantage of a coefficient, just can realize to mantissa's voltage to number conversion; In fact secondary conversion is not that fine quantization point is inserted into V
g～V
(G+1)in, but mantissa's voltage U of chopped-off head
xGtake out U
xGexcursion be (0～Δ V
g), chopped-off head mantissa voltage U after corresponding amplifier FG amplifies
xGbe expanded into chopped-off head computing step voltage U
yG, make amplifier F
gmultiplication factor be Vp/ Δ V
g, U
yG=U
xG* V
p/ Δ V
g, change in voltage expanded range is to secondary full scale 0～V
p; Computing step voltage U
yGthrough adopting, protect device CB
βafter adopting guarantor, become secondary input voltage U
β y; And construct log law point of quantification in secondary resistance chain, be crucial, in secondary resistance chain, R
bfor the virtual resistance of setting arbitrarily, T chain resistance increases progressively according to ratio η geometric ratio: R '
1=R
b* η
1, R '
2=R
b* η
2, R '
3=R
b* η
3..., R '
t-2=R
b* η
(T-2), R '
t-1=R
b* η
(T-1), R '
t=R
b* η
t, self-assembling formation T the current potential point of quantification increasing progressively according to ratio η geometric ratio: 0, V '
1=V
b* η
1, V '
2=V
b* η
2, V '
3=V
b* η
3..., V '
t-2=V
b* η
(T-2), V '
t-1=V
b* η
(T-1), its quantized interval is: (V '
1～0] → 0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1; And V '
t=V
pbe excluded outside this group point of quantification;
So far, this two-stage logarithm chain ADC has converted analog signal to numerical expression digital signal to, if on this basis, by basic resistance R
θbe adjusted into adjusting resistance R*
θ, R*
θ=R
θ～R
θ/ 15, and make R*
θthe minimum useful signal of=detector, by adjusting resistance R*
θreduce, some declines at small-signal end can to make signal to noise ratio curve, but dynamic range is increased.
9. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the two-stage logarithm chain DAC based on following switch, the resistance chain of this DAC and reference potential chain are all logarithmic relationships; The log law digital signal receiving is: high-order D
q-1～D
0, low level D '
t-1～D '
0; High-order D
q-1～D
0correspondence is delivered to chopped-off head variable connector control end d
q-1～d
0, obtain chopped-off head level current potential V
g; Low level D '
t-1～D '
0correspondence is delivered to secondary variable connector control end d '
t-1～d '
0, obtain secondary level current potential V '
b, make b equal certain point in (0～T-1), V '
bbe called secondary b rank reference point of potential, the potential point being wherein strobed is secondary level current potential V '
b;
LDA#
βcomprise three parts: DZL
β, JDWKG ' and ∑
β U; DZL
βfor secondary logarithmic resistance chain, comprising: secondary to numerical expression resistance chain R '
t～R '
1, secondary to numerical expression reference point of potential V ' '
t-
1～V '
0, the logarithmetics design of secondary resistance chain is with embodiment 4.1;
Secondary resistance chain forms T reference point of potential V '
t-1, V '
t-2... V '
1, V '
0, its quantized interval is: (V '
1～0] → V '
0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1; Known V '
bquantization step or claim jump Δ V '
b=V '
b+1-V '
b; Secondary level level switch JDWKG ' control end d '
t-1～d '
0receive low order digit signal D '
t-1～D '
0after, at secondary switch point S '
t-1～S '
0in determine a gating point S '
b, this gating point signalment is S '
b, gating point S '
bcorresponding potential point V '
bfor secondary level current potential V
β B, secondary level current potential V
β Bexcursion be T potential point V '
0, V '
1..., V '
t-2, V '
t-1, the quantized interval of each point is respectively: (V '
1～V '
0] → V '
0, (V '
2～V '
1] → V '
1, (V '
3～V '
2] → V '
2..., (V '
t-1～V '
t-2] → V '
t-2,, (V '
t～V '
t-1] → V '
t-1so, secondary level current potential V
β Bcorresponding analog voltage excursion is 0～V
p;
LDA#
αcomprise four parts: DZL
α, SJQH, JDWKG and ∑
aU; DZL
αfor chopped-off head logarithmic resistance chain, comprise that chopped-off head is to numerical expression resistance chain R
q～R
1and R
θ, chopped-off head is to numerical expression reference point of potential V
q-1～V
θ, the logarithmetics design and implementation example 4.1 of chopped-off head resistance chain is identical; Make g equal 0～(Q-1) in Arbitrary Digit, each chopped-off head potential point V
gcorrespondence connects three devices: summer ∑
g, reducer ψ
gwith switching point S
g, be called g branch road, potential point V
gwith potential point V
g+1voltage be called potential point V
gjump Δ V
g, triadic relation is Δ V
g=V
g+
1-V
g;
With chopped-off head level current potential V
gduring addition, secondary level current potential V
β Bshould be with level current potential V
gmantissa voltage identity occur, notice secondary level current potential V
β Hcorresponding analog voltage excursion is 0～V
p, and change in voltage scope should be 0～Δ V
gjust reasonable, so corresponding to g rank current potential, should be by V
β Bexcursion by 0～V
preduce into 0～Δ V
g, just need to be with a reducer ψ
gcomplete this task, also be appreciated that the Δ V on every rank
gunequal, but geometric ratio variation, so every rank reducer Ψ
greduction ratio ψ
galso be that geometric ratio changes, make ψ
g=Δ V
g/ V
p, secondary level current potential V
β Bbecome reduction value V
ψ g, reduction is calculated as: V
ψ g=V
β B* ψ
g=V
β B* Δ V
g/ V
pso change in voltage scope is by V
β B0～V
preduced into V
ψ g0～Δ V
g, reduction voltage V
ψ gbe exactly chopped-off head reference point of potential V
q-1～V
θin mantissa's voltage on g rank, wait for gating; Chopped-off head reference potential V
gas the rough analogue value, and corresponding reduction voltage V
ψ gas V
gmantissa's voltage be the meticulous analogue value, V
gwith V
ψ gby summer ∑
gbe added, obtain the rough analogue value V of chopped-off head
gwith secondary meticulous analogue value V
ψ gsum, claims reference potential summing value V
∑ g, each examines current potential V chopped-off head
gthere is a reference potential summing value V in correspondence all
∑ gwait for output; As chopped-off head level level switch JDWKG control end d
q-1～d
0receive high-order digit signal D
q-1～D
0after, determined chopped-off head gating point S
g, by corresponding reference potential summing value V
∑ gas level current potential summing value U
∑ Goutput to summary device ∑
α U, summary device ∑
α Uin fact receive only unique level current potential summing value U
∑ G, as dac value U
α βoutput; So far, two-stage logarithm chain DAC converts.
10. multistage parallel formula ADC and the DAC based on voltage follow switch according to claim 1, its further feature is: the two-stage logarithm chain DAC based on following half stepwise point of quantification of switch, half rankization processing, chopped-off head half rank reference point U have been carried out in the setting that is reference point of potential
g, chopped-off head half rank resistance P
g, secondary half rank reference point U '
b, secondary half rank resistance P '
b; With the corresponding relation of former resistance chain be: U
g→ V
g, P
g→ R
g, U '
b→ V '
b, P '
b→ R '
b; So-called half rank make reference point of potential move half rank on the original basis exactly, and computational methods are:
Reference point of potential all raises half rank, becomes: chopped-off head half rank reference point U
g=(V
g+ V
g* η)/2, chopped-off head half rank resistance P
g=(R
g+ R
g* η)/2; Secondary half rank reference point U '
b=(V '
b+ V '
b* η)/2, secondary half rank resistance: P '
b=(R '
b+ R '
b* η)/2; Like this, reference point of potential and resistance all raise half rank.
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| CN201310048568.6A CN103986467A (en) | 2013-02-07 | 2013-02-07 | Multi-level parallel type ADC and DAC based on voltage following switch |
| JP2014549348A JP6073920B2 (en) | 2012-05-30 | 2013-02-22 | Logarithmic companding ratio Multiple simultaneous execution ultra-fast ADC and DAC class potential architecture (stage-potential architecture) |
| EP13731648.5A EP2800276A4 (en) | 2011-12-26 | 2013-02-22 | Multi-level parallel super-high speed adc and dac using logarithmic companding law |
| US14/366,254 US9136852B2 (en) | 2011-12-26 | 2013-02-22 | Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law |
| PCT/CN2013/000173 WO2013097831A2 (en) | 2011-12-26 | 2013-02-22 | Multi-level parallel super-high speed adc and dac using logarithmic companding law |
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| CN107251439A (en) * | 2015-02-11 | 2017-10-13 | 三菱电机株式会社 | Method and AMC controllers for adaptive modulation and coding AMC |
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| US20080204291A1 (en) * | 2007-02-27 | 2008-08-28 | Infineon Technologies | Digital-to-analog converter with logarithmic selectable response and methods |
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| CN107251439A (en) * | 2015-02-11 | 2017-10-13 | 三菱电机株式会社 | Method and AMC controllers for adaptive modulation and coding AMC |
| CN107251439B (en) * | 2015-02-11 | 2021-01-05 | 三菱电机株式会社 | Method and AMC controller for adaptive modulation and coding of AMC |
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