CN103986455B - Scanning holding register - Google Patents
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- CN103986455B CN103986455B CN201410193399.XA CN201410193399A CN103986455B CN 103986455 B CN103986455 B CN 103986455B CN 201410193399 A CN201410193399 A CN 201410193399A CN 103986455 B CN103986455 B CN 103986455B
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Abstract
The invention provides a scanning holding register. The scanning holding register comprises a power circuit, a holding control circuit, a scanning selection circuit, a main latch and an auxiliary latch. The power circuit provides a power supply. The holding control circuit responds to external clock signals and holding and control signals received from the external and outputs internal clock signals and internal holding control signals. The scanning selection circuit selects scanning signals or working signals received from the external as internal signals according to scanning control signals received from the external and outputs the internal signals. The main latch responds to the internal clock signals, receives the internal signals from the scanning selection circuit, inverses the internal signals and outputs the inverted internal signals or latches the internal signals and outputs the inverted internal signals. The auxiliary latch responds to internal holding control signals, receives the inverted internal signals from the main latch, inverses the inverted internal signals and outputs the internal signals, or latches the inverted internal signals and outputs the internal signals or stores the received inverted internal signals.
Description
Technical field
The present invention relates to a kind of register, more particularly, is related to a kind of scanning holding register.
Background technology
As electronic product (for example, desktop computer, notebook computer, mobile phone, panel computer etc.) is sent out to lightening direction
Exhibition, has higher requirement to the area shared by the circuit unit of each functional module.
Scanning holding register is scanned due to the functional module that both can realize being connected to scanning holding register
The function of test, the peration data that user can be preserved again (for example, when electronic equipment is in sleep state, preserves user's
Using data), in being widely used in electronic product.
However, it is existing scanning holding register circuit unit shared by Area comparison it is big, it is difficult to adapt to electronic product to
The requirement that lightening direction is developed.
Accordingly, it would be desirable to a kind of little scanning holding register of circuit unit area.
The content of the invention
The present invention provides a kind of scanning holding register, so as to effectively reduce scanning holding register circuit unit in chip
In shared area, the power consumption of scanning holding register is reduced, while can be when electronic product is in normal mode of operation pair
Latch is kept to be scanned test.
The present invention provides a kind of scanning holding register, it is characterised in that include：Power circuit, keeps control circuit, sweeps
Retouch selection circuit, main latch, from latch, wherein, power circuit is to keeping control circuit, scan selection circuit, main latch
Device and power from latch, keep control circuit in response to the external timing signal from external reception and keep control signal output
Internal clock signal and it is internal keep control signal, scan selection circuit according to the scan control signal selection from external reception from
One of scanning signal and working signal of external reception are as internal signal and export internal signal, and main latch is series at scanning
Selection circuit and between latch, in response to from the internal clock signal for keeping control circuit to receive, receiving scanning electricity is selected
The internal signal of road output, exports reverse internal signal by the internal signal for receiving reversely, or latches the inside letter for receiving
Number and export reverse internal signal, from responsive in control signal is kept from the inside for keeping control circuit to receive, connect
The reverse internal signal of main latch output is received, internal signal is exported by the reverse internal signal for receiving again reversely, or
The reverse internal signal that receives of latch simultaneously exports internal signal, or preserves the reverse internal signal for receiving.
Alternatively, control circuit is kept to include：Internal clock signal generation circuit, in response to from the outside of external reception when
Clock signal output internal clock signal, wherein, internal clock signal includes clock signal and reverse clock signal；Inside keeps
Control signal produces circuit, receives in response to the holding control signal from external reception and from internal clock signal generation circuit
Reverse clock signal, output is internal to keep control signal.
Alternatively, power circuit provides the first power supply and second source, and second source is to from latch and internal holding control
Signal generating circuit processed is powered, and the first power supply is powered to scan selection circuit, main latch and internal clock signal generation circuit,
Wherein, second source continued power, the first power supply from the holding control signal of external reception in response to powering or disconnecting power supply.
Alternatively, from the holding control signal of external reception to keep signal or non-holding signal, the first power supply in response to
Non- holding signal is powered to scan selection circuit, main latch and internal clock signal generation circuit, in response to keeping signal to break
Open the power supply to scan selection circuit, main latch and internal clock signal generation circuit.
It is alternatively, internal to keep control signal to include that clock keeps control signal and reverse clock to keep control signal,
Wherein, it is that clock triggering keeps control signal or clock non-toggle to keep control signal that clock keeps control signal, when reverse
It is that reverse clock triggering keeps control signal or reverse clock non-toggle to keep control signal that clock keeps control signal.
Alternatively, it is internal to keep control signal to produce circuit in response to the non-holding signal from external reception and during from inside
The reverse clock signal that clock signal generating circuit is received, output is internal to keep control signal, wherein, from responsive in from
Inside keeps the clock triggering that control signal produces circuit reception to keep control signal and reverse clock triggering to keep controlling letter
Number, the reverse internal signal of main latch output is received, by the reverse internal signal for receiving again reversely, the internal letter of output
Number.
Alternatively, from responsive in from the internal clock non-toggle holding control for keeping control signal to produce circuit reception
Signal processed and reverse clock non-toggle keep control signal, the reverse internal signal that latch is received simultaneously to export internal letter
Number.
Alternatively, it is internal to keep control signal to produce circuit in response to the holding signal from external reception and from internal clocking
The reverse clock signal that signal generating circuit is received, output clock non-toggle keeps control signal and reverse clock non-toggle
Control signal is kept, wherein, protect in the clock non-toggle for producing circuit reception from internal holding control signal from responsive
Hold control signal and reverse clock non-toggle keeps control signal, preserve the reverse internal signal for receiving.
Alternatively, the scan control signal from external reception is scan pattern signal or mode of operation signal, when sweeping
Retouch selection circuit from the scan control signal of external reception be scan pattern signal when, select from the scanning signal of external reception to make
For internal signal and internal signal is exported, when the scan control signal from external reception is mode of operation signal, selected from outer
The working signal that portion receives is as internal signal and exports internal signal.
Alternatively, clock signal is that clock trigger signal or clock non-touch are signaled, and reverse clock signal is reverse
Clock trigger signal or reverse clock non-touch are signaled.
Alternatively, main latch signals and reversely in response to the clock non-touch that receives from internal clock signal generation circuit
Clock non-touch signal, receive the internal signal of scan selection circuit output, output is reverse by the internal signal for receiving reversely
Internal signal.
Alternatively, main latch is in response to the clock trigger signal that receives from internal clock signal generation circuit and reverse
Clock trigger signal, the internal signal that latch is received simultaneously exports reverse internal signal.
Alternatively, the internal clock signal generation circuit includes：First reverser, from external reception external clock letter
Number, export reverse clock signal by the external timing signal for receiving reversely；Second reverser, receives the output of the first reverser
Reverse clock signal, by reverse clock signal again reversely, export clock signal.
Alternatively, the internal holding control signal produces circuit includes：3rd reverser, keeps controlling from external reception
Signal, by the holding control signal for receiving reversely, exports reverse holding control signal；First OR gate, receives the first reverser
The reverse holding control signal of reverse clock signal and the 3rd reverser output of output, to the reverse clock letter for receiving
Number and reverse holding control signal carry out or computing, export reverse clock and keep control signal；4th reverser, receives the
The reverse clock of one OR gate output keeps control signal, the reverse clock for receiving is kept into control signal reversely, during output
Clock keeps control signal.
Alternatively, it is described to include from latch：First transmission gate, in response to keeping control signal generation circuit to connect from internal
The clock triggering of receipts keeps control signal and reverse clock triggering to keep control signal, receives the reverse of main latch output
Internal signal, exports the reverse internal signal for receiving；5th reverser, receives the reverse inside letter of the first transmission gate output
Number, export internal signal by the reverse internal signal for receiving again reversely；First controllable reverser, in response to from internal holding
Control signal produces clock non-toggle holding control signal and the reverse clock non-toggle holding control signal that circuit is received, and connects
The internal signal of the 5th reverser output is received, reverse internal signal is exported by the internal signal for receiving reversely.
Scanning holding register of the invention, can make from latch to realize simultaneously from latch and keep latch
Function, save the scanning shared in the chips area of holding register circuit, reduce power consumption.Additionally, according to the present invention,
Device in can making scanning holding register in the normal mode of operation to keeping latch is scanned test.
The other aspect of the present invention and/or advantage will be partly illustrated in following description, some is by retouching
State and will be apparent, or the enforcement of the present invention can be passed through and be learnt.
Description of the drawings
By the detailed description for carrying out below in conjunction with the accompanying drawings, above and other objects of the present invention, feature and advantage will
Become more fully apparent, wherein：
Fig. 1 illustrates the block diagram of the scanning holding register of exemplary embodiment of the invention.
Fig. 2A illustrates that the internal clock signal in the holding control circuit of Fig. 1 of exemplary embodiment of the invention is produced
The circuit diagram of raw circuit.
Fig. 2 B illustrate that the inside in the holding control circuit of Fig. 1 of exemplary embodiment of the invention keeps control letter
Number produce circuit circuit diagram.
Fig. 3 illustrates the electricity from latch in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Lu Tu.
Fig. 4 illustrates the scan selection circuit in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Circuit diagram.
Fig. 5 illustrates the electricity of the main latch in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Lu Tu.
Specific embodiment
Now, different example embodiments are more fully described with reference to the accompanying drawings, wherein, some exemplary embodiments are attached
Illustrate in figure, wherein, identical label represents all the time identical part.
Fig. 1 illustrates the block diagram of scanning holding register of the invention.
As shown in figure 1, scanning holding register 100 of the invention includes：Keep control circuit 110, power circuit
120th, scan selection circuit 130, main latch 140, from latch 150.
Control circuit 110 is kept in response to the external timing signal (CK) from external reception and control signal (RETN) is kept
Output internal clock signal (c and cn) and internal holding control signal (ret_c and ret_cn).
Control circuit 110 is kept to include：Internal clock signal generation circuit 111 and internal holding control signal produce circuit
112。
Internal clock signal generation circuit 111 is in response to external timing signal (CK) the output internal clocking from external reception
Signal (c and cn).
The internal clock signal of the output of internal clock signal generation circuit 111 may include clock signal (c) and it is reverse when
Clock signal (cn).Specifically, internal clock signal generation circuit 111 will be anti-from the external timing signal of external reception (CK)
To the reverse clock signal (cn) of output.By reverse clock signal (cn) again reversely, output clock signal (c).
Here, clock signal (c) can be clock trigger signal (c=first is worth, and the first value is 0 and one of 1) or clock
Non-touch signal (c=second values, second value be different from the first value 0 and 1 another value), reverse clock signal can be
Reverse clock trigger signal (cn=second values) or reverse clock non-touch signals (cn=first is worth).
Inside keeps control signal to produce circuit 112 in response to the holding control signal (RETN) from external reception and from interior
The reverse clock signal (cn) that portion's clock signal generating circuit 111 is received, output is internal keep control signal (ret_c and
ret_cn)。
Inside keeps the inside that control signal produces the output of circuit 112 to keep control signal to may include that clock keeps control letter
Number (ret_c) and reverse clock keep control signal (ret_cn).Specifically, it is internal to keep control signal to produce circuit
112 will be from the holding control signal (RETN) of external reception reversely, to reverse holding control signal (ret) and from internal clocking
The reverse clock signal (cn) that signal generating circuit 111 is received is carried out or computing, is exported reverse clock and is kept control signal
(ret_cn).Reverse clock is kept into control signal (ret_cn) reversely, output clock keeps control signal (ret_c).
Here, clock keep control signal (ret_c) can for clock triggering keep control signal (ret_c=the 3rd be worth,
3rd value be 0 and one of 1) or clock non-toggle keep control signal (ret_c=the 4th be worth, the 4th value is different from the 3rd value
0 and 1 another value), it can be that reverse clock triggering keeps control letter that reverse clock keeps control signal (ret_cn)
Number (values of ret_cn=the 4th) or reverse clock non-toggle keep control signal (values of ret_cn=the 3rd).
For example, it is internal to keep control signal to produce circuit 112 in response to the holding signal (RETN=the 5th from external reception
Value, the 5th value is 0 and one of 1) and from the reverse clock signal (cn) of the reception of internal clock signal generation circuit 111, output
Clock non-toggle keeps control signal (values of ret_c=the 4th) and reverse clock non-toggle to keep control signal (ret_cn=
3rd value).
Power circuit 120 is used for keeping control circuit 110, scan selection circuit 130, main latch 140 and from latch
Device 150 is powered.
Power circuit 120 includes the first power supply 121 and second source 122.Specifically, 121 pairs of scanning choosings of the first power supply
Select circuit 130, main latch 140 and internal clock signal generation circuit 111 to power, second source 122 pairs is from the He of latch 150
Inside keeps control signal generation circuit 112 to power.
Here, the continued power of second source 122, the first power supply 121 is in response to the holding control signal from external reception
(RETN) power or disconnect power supply.For example, the first power supply 121 is in response to the non-holding signal (RETN=the 6th from external reception
Value, the 6th value be different from the 5th value 0 and 1 another value) to scan selection circuit 130, main latch 140 and internal clocking
Signal generating circuit 111 is powered, and is disconnected in response to the holding signal (values of RETN=the 5th) from external reception and is selected electricity to scanning
The power supply on road 130, main latch 140 and internal clock signal generation circuit 111.
In one example, the first power supply 121 can be realized by gating device.Gating device is powered from external reception, and
And in response to being turned on or off from the holding control signal (RETN) of external reception, so as to control the first power supply 121 power or
Disconnect power supply.For example, gating device may be in response to non-holding signal (values of RETN=the 6th) unlatching, and the first power supply 121 is powered, rung
Should be in keeping signal (values of RETN=the 5th) to close, the first power supply 121 disconnects power supply.Power gating device can be it is any can be with
Realize circuit, the device of switching function, for example it is, metal oxide layer semiconductcor field effect transisto (MOSFET), triode, controllable
Silicon etc..
Scan selection circuit 130 selects from the scanning of external reception to believe according to the scan control signal (SE) from external reception
Number one of (SI) and working signal (D) are as internal signal and export internal signal (SI or D).
For example, can be scan pattern signal (values of SE=the 7th, the 7th value from the scan control signal (SE) of external reception
For 0 and one of 1) or mode of operation signal (SE=the 8th be worth, the 8th value be different from the 7th value 0 and 1 another value).
In one example, when scan selection circuit 130 is scan pattern from the scan control signal (SE) of external reception
During signal (values of SE=the 7th), scan selection circuit 130 select from the scanning signal (SI) of external reception as internal signal simultaneously
Output internal signal (SI).
In another example, when scan selection circuit 130 is Working mould from the scan control signal (SE) of external reception
During formula signal (values of SE=the 8th), select as internal signal and to export internal signal from the working signal (D) of external reception
(D)。
Main latch 140 is series at scan selection circuit 130 and between latch 150, in response to believing from internal clocking
Number produce circuit 111 receive internal clock signal (c and cn), receive scan selection circuit 130 output internal signal (SI
Or D), export reverse internal signal by the internal signal (SI or D) for receiving reversely, or latch the internal signal (SI for receiving
Or D) and export reverse internal signal.
For example, the clock non-touch that main latch 140 may be in response to be received from internal clock signal generation circuit 111 is signaled
(c=second values) and reverse clock non-touch are signaled (cn=first is worth), receive the inside letter of the output of scan selection circuit 130
Number (SI or D), exports reverse internal signal by the internal signal (SI or D) for receiving reversely.Additionally, main latch 140 can ring
Clock trigger signal (c=first is worth) and reverse clock triggering letter that Ying Yucong internal clock signal generation circuits 111 are received
Number (cn=second values), latches the internal signal (SI or D) for receiving and simultaneously exports reverse internal signal.
From latch 150 in response to keeping control signal to produce the inside holding control signal that circuit 112 is received from internal
(ret_c and ret_cn), receives the reverse internal signal of the output of main latch 140, by the reverse internal signal for receiving again
Reversely, and export internal signal (SI or D), or latch the reverse internal signal for receiving and export internal signal (SI or
D), or the reverse internal signal that receives is preserved.
In one example, control signal is kept to produce circuit 112 in response to the non-holding letter from external reception when internal
Number (values of RETN=the 6th) and the reverse clock signal (cn) received from internal clock signal generation circuit 111, output is internal
When keeping control signal (ret_c=c and ret_cn=cn), may be in response to keep control signal to produce from internal from latch 150
The clock triggering that raw circuit 112 is received keeps control signal (values of ret_c=the 3rd) and reverse clock triggering to keep control letter
Number (values of ret_cn=the 4th), receives the reverse internal signal of the output of main latch 140, the reverse internal signal that will be received
Again reversely, output internal signal (SI or D).Additionally, may be in response to keep control signal to produce circuit from internal from latch 150
The 112 clock non-toggle for receiving keep control signal (values of ret_c=the 4th) and reverse clock non-toggle to keep control signal
(values of ret_cn=the 3rd), the reverse internal signal that latch is received simultaneously exports internal signal (SI or D).
In another example, control signal is kept to produce circuit 112 in response to the holding letter from external reception when internal
Number (values of RETN=the 5th) and the reverse clock signal (cn) received from internal clock signal generation circuit 111, exports clock
Non-toggle keeps control signal (values of ret_c=the 4th) and reverse clock non-toggle to keep control signal (ret_cn=the 3rd
Value) when, may be in response to keep control from the internal clock non-toggle for keeping control signal to produce the reception of circuit 112 from latch 150
Signal (values of ret_c=the 4th) processed and reverse clock non-toggle keep control signal (values of ret_cn=the 3rd), preserve and receive
The reverse internal signal for arriving.Now, realize keeping the function of latch from latch.
Can be seen that by above-mentioned two example can be while realizing from latch and keeping latch from latch 150
Function.
Fig. 2A illustrates that the internal clock signal in the holding control circuit of Fig. 1 of exemplary embodiment of the invention is produced
The circuit diagram of raw circuit.
As shown in Figure 2 A, the circuit of the internal clock signal generation circuit 111 in control circuit 110 is kept to include：First
The reverser 1112 of reverser 1111 and second.
First reverser 1111 is anti-by the external timing signal (CK) for receiving from external reception external timing signal (CK)
To the reverse clock signal (cn) of output.
The input of the second reverser 1112 is connected to the output end of the first reverser 1111, and the second reverser 1112 is received
The reverse clock signal (cn) of the output of the first reverser 1111, by the reverse clock signal (cn) for receiving again reversely, output
Clock signal (c).
It should be understood that the internal clock signal generation circuit of the present invention is not limited to the internal clock signal shown by Fig. 2A producing
Raw circuit, others may also be employed can realize the circuit of identical function.
Fig. 2 B illustrate that the inside in the holding control circuit of Fig. 1 of exemplary embodiment of the invention keeps control letter
Number produce circuit circuit diagram.
As shown in Figure 2 B, keeping the inside in control circuit 110 to keep control signal to produce circuit 112 includes that the 3rd is reverse
Device 1121, the first OR gate 1122 and the 4th reverser 1123.
3rd reverser 1121 keeps control signal (RETN) from external reception, the holding control signal (RETN) that will be received
Reversely, reverse holding control signal (ret) is exported.
The first input end of the first OR gate 1122 is connected to the output end of internal clock signal generation circuit 111 (for example, schemes
The output end of the first reverser 1111 in 4), receive the reverse clock signal (cn) of the output of the first reverser 1111.First or
Second input of door 1122 is connected to the output end of the 3rd reverser 1121, receives the reverse of the output of the 3rd reverser 1121
Keep control signal (ret).Reverse clock signal (cn) and reverse holding control signal that first OR gate 1122 pairs is received
(ret) carry out or computing, export reverse clock and keep control signal (ret_cn).
The input of the 4th reverser 1123 is connected to the output end of the first OR gate 1122, and the 4th reverser 1123 receives the
The reverse clock of the output of one OR gate 1122 keeps control signal (ret_cn), and the reverse clock for receiving is kept into control signal
(ret_cn) reversely, output clock keeps control signal (ret_c).
It should be understood that the inside of the present invention keeps the inside that control signal generation circuit is not limited to shown by Fig. 2 B to keep control
Signal generating circuit processed, others may also be employed can realize the circuit of identical function.
Fig. 3 illustrates the electricity from latch in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Lu Tu.
As shown in figure 3, including from latch 150：First transmission gate 151, the 5th reverser 152, the first controllable reverser
153。
The input of the first transmission gate 151 is connected to the output end of main latch 140, the first transmission gate 151 in response to from
Inside keeps the clock triggering that control signal produces the reception of circuit 112 to keep control signal (ret_c=1, i.e. the 3rd value is for 1)
Control signal (ret_cn=0, i.e. the 4th value is 0), to receive the anti-of the output of main latch 140 is kept with reverse clock triggering
To internal signal, and export the reverse internal signal of reception.
The input of the 5th reverser 152 is connected to the output end of the first transmission gate 151, and the 5th reverser 152 receives the
The reverse internal signal of the output of one transmission gate 151, and exports internal signal by the reverse internal signal for receiving again reversely
(SI or D).
The input of the first controllable reverser 153 is connected to the output end of the 5th reverser 152, the first controllable reverser
153 from internal in response to keeping control signal to produce clock non-toggle holding control signal (ret_c=0) that circuit 112 is received
Control signal (ret_cn=1) is kept with reverse clock non-toggle, the internal signal (SI of the output of the 5th reverser 152 is received
Or D), and export reverse internal signal by the internal signal for receiving (SI or D) reversely.
In one example, when scanning holding register 100 is holding from the holding control signal (RETN) of external reception
(RETN=0, i.e. when 0) the 5th value is, scanning holding register 100 is in hold mode to signal, and inside keeps control signal product
The raw output clock of circuit 112 non-toggle keeps control signal (ret_c=0) and reverse clock non-toggle to keep control signal
(ret_cn=1), high-impedance state is in from the first transmission gate 151 of latch 150, it is controllable anti-by the 5th reverser 152 and first
The reverse internal signal having been received by is preserved to the closed-loop path of the composition of device 153.Now, realize keeping latching from latch
The function of device.
In another example, when scanning holding register 100 is non-from the holding control signal (RETN) of external reception
Keep signal (RETN=1, i.e. the 6th value is for 1), it is scan pattern signal to keep control signal (SE) from the scanning of external reception
(SE=1, i.e. when 1) the 7th value is, scanning holding register 100 is in non-maintained status, and internal signal is scanning signal
(SI).It is that clock triggering keeps control letter when the internal inside for keeping control signal to produce the output of circuit 112 keeps control signal
When number (ret_c=1) and reverse clock triggering keep control signal (ret_cn=0), from latch 150 by the first transmission gate
151 receive the reverse scanning signal of the output of main latch 140, and export scanning signal (SI) (this by the 5th reverser 152
When, the first controllable reverser 153 is in high-impedance state).When the internal inside for keeping control signal to produce the output of circuit 112 keeps
Control signal is that clock non-toggle keeps control signal (ret_c=0) and reverse clock non-toggle to keep control signal (ret_
When cn=1), high-impedance state is in from the first transmission gate 151 of latch 150, by the 5th reverser 152 and the first controllable reverser
The reverse scanning signal having been received by is latched in the closed-loop path of 153 compositions, and exports scanning signal by the 5th reverser 152
(SI).Above-mentioned example can realize scan holding register 100 be in non-maintained status when to from latch 150 (namely
Keep latch) in device be scanned test.For example, the scanning signal (SE) of the input of scan selection circuit 130 is served as reasons " 0 "
The specific encoded signal of " 1 " composition, according to above-mentioned main latch 140, from the operation principle of latch 150, by detection
Main latch 140, the signal from the output of the output end of latch 150 may determine that from the whether normal work of latch 150, so as to
May determine that when holding register 100 is scanned in hold mode, keep latch (that is, from latch) correctly to preserve
The information for receiving.
It should be understood that the input mode of control signal from latch of the present invention is not limited to input side illustrated in fig. 3
Formula, others may also be employed can realize the input mode of identical function.For example, can by the first transmission gate 151 and first in Fig. 3
The control signal of control reverser 153 reversely, makes the first transmission gate 151 in response to keeping control signal to produce circuit 112 from internal
The clock triggering of reception keeps control signal (ret_c=0, i.e. the 3rd value is 0) and reverse clock triggering keeps control signal
(ret_cn=1, i.e. the 4th value exports the anti-of reception 1), to receive the reverse internal signal of the output of main latch 140
To internal signal.The first controllable reverser 153 is made in response to keeping control signal to produce the clock that circuit 112 is received from internal
Non-toggle keeps control signal (ret_c=1) and reverse clock non-toggle keeps control signal (ret_cn=0), reception the
The internal signal (SI or D) of the output of five reverser 152, and exports reverse by the internal signal for receiving (SI or D) reversely
Internal signal.The input mode of the control signal in above-mentioned example can make above-mentioned to realize identical function from latch.
It should be understood that being not limited to from latch for the present invention is illustrated in fig. 3 from latch, others may also be employed can
Realize the circuit of identical function.
Scan selection circuit 130 can be that any multiple signals that can be realized to being input into carry out selecting the circuit of output.
Below, an example of scan selection circuit is described with reference to Fig. 4.
Fig. 4 illustrates the scan selection circuit in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Circuit diagram.
As shown in figure 4, the scan selection circuit 130 in scanning holding register includes：First is reverse with door the 131, the 6th
Device 132, second and door 133, the second OR gate 134.
First with two inputs of door 131 respectively from external reception scanning signal (SI) and scan control signal (SE),
First is carried out and computing with the scanning signal (SI) and scan control signal (SE) of 131 pairs of receptions of door, exports first with signal (SI
×SE)。
6th reverser 132 is anti-by the scan control signal for receiving (SE) from external reception scan control signal (SE)
To, and export reverse scan control signal。
Second output end that the 6th reverser 132 is connected to the first input end of door 133, receives the 6th reverser 132
The reverse scan control signal of output, second with the second input of door 133 from external reception working signal (D).The
Two with the reverse scan control signals of 133 pairs, door receptionCarry out and computing with working signal (D), export second with letter
Number。
The first input end of the second OR gate 134 is connected to the output end of first and door 131, receives first and exports with door 131
First with signal (SI × SE), the second input of the second OR gate 134 is connected to the output end of second and door 133, reception the
Two second and the signals exported with door 133.Second OR gate 134 pairs receive first with signal (SI × SE) and the
Two and signalCarry out or computing, output scanning signal (SI) and one of working signal (D) as internal signal (, i.e. SI or D).
It should be understood that the input mode of signal is not limited to input side illustrated in fig. 4 in the scan selection circuit of the present invention
Formula, others may also be employed can realize the input mode of identical function.For example, two inputs point of first and door 131 are made
Not from external reception working signal (D) and scan control signal (SE), make second and door 133 the second input from external reception
Scanning signal (SI), scan selection circuit output scanning signal (SI) and one of working signal (D) as internal signal (, i.e. SI or D).Input pattern signal in above-mentioned example can make above-mentioned scan selection circuit realize phase
Same function.
It should be understood that the scan selection circuit of the present invention is not limited to scan selection circuit illustrated in fig. 4, it may also be employed
His circuit that can realize identical function.
Main latch 140 can be any circuit with latch signal and output signal function.Below, retouch with reference to Fig. 5
State an example of main latch.
Fig. 5 illustrates the electricity of the main latch in the scanning holding register of Fig. 1 of exemplary embodiment of the invention
Lu Tu.
As shown in figure 5, main latch 140 includes：Second transmission gate 141, the 7th reverser 142, the second controllable reverser
143。
The input of the second transmission gate 141 is connected to the output end of scan selection circuit 130 (for example, the second OR gate in Fig. 4
134 output end).Second transmission gate 141 is transmitted in response to the clock non-touch received from internal clock signal generation circuit 111
Number (c=0, i.e. second value is 0) to signal (cn=1, i.e. the first value is selected 1), to receive scanning with reverse clock non-touch
The internal signal of the output of circuit 130And export the internal signal of reception
The input of the 7th reverser 142 is connected to the output end of the second transmission gate 141, and the 7th reverser 142 receives the
The internal signal of the output of two transmission gate 141The internal signal for receiving is reverseAnd export reverse internal signal
The input of the second controllable reverser 143 is connected to the output end of the 7th reverser 142, the second controllable reverser
143 in response to the clock trigger signal (c=1) that receives from internal clock signal generation circuit 111 and reverse clock triggering letter
Number (cn=0), receives the reverse internal signal of the output of the 7th reverser 142By reverse inside
SignalIt is reverse again, and export internal signalHere, second is controllable anti-
Realize latching the function of the internal signal for receiving in the closed-loop path constituted to device 143 and the 7th reverser 142.
It should be understood that the input mode of control signal is not limited to input side illustrated in fig. 5 in the main latch of the present invention
Formula, others may also be employed can realize the input mode of identical function.For example, can by the second transmission gate 141 and second in Fig. 5
The control signal of control reverser 143 reversely, makes the second transmission gate 151 in response to receiving from internal clock signal generation circuit 111
Clock non-touch signal (c=1, i.e. second value is 1) to signal (cn=0, i.e. the first value is with reverse clock non-touch
0) internal signal of the output of scan selection circuit 130, is receivedAnd export the internal signal of receptionThe second controllable reverser 143 is made in response to when internal clock signal generation circuit 111 is received
Clock trigger (c=0) and reverse clock trigger signal (cn=1), receive the reverse inside of the output of the 7th reverser 142
SignalBy reverse internal signalIt is reverse again, and export internal letter
NumberIt is identical that the input mode of the control signal in above-mentioned example realizes can above-mentioned main latch
Function.
It should be understood that the main latch of the present invention is not limited to main latch illustrated in fig. 5, others may also be employed can
Realize the circuit of identical function.
When existing scanning holding register is in hold mode, signal is stored in into holding and is latched wherein.When scanning is protected
When holding the connected functional module of register pair and being scanned test, by will input scanning signal and each functional module
The signal of output is compared, and can learn each functional module whether normal work.But when scanning holding register is scanned
During test, keep latch to be in idle state, do not receive scanning signal, thus the electricity kept in latch cannot be learnt
The state of circuit component.So, when the component cisco unity malfunction in keeping latch, will cause to scan holding register
The operation information of user cannot be correctly preserved, is made troubles to user.
Scanning holding register of the invention, can make from latch to realize keeping latch and from latch multiplexing
Function, save the circuit area of a holding latch, reduce the shared in the chips space of scanning holding register,
And reduce power consumption.Additionally, when scanning holding register and being scanned test, the scanning holding register of the present invention can be with
The function to keeping latch to be scanned test is realized, so as to ensure that the energy when scanning holding register and being in hold mode
Enough correct operation informations for preserving user.
Although the present invention, those skilled in the art are particularly shown and described with reference to its exemplary embodiment
It should be understood that in the case of the spirit and scope of the present invention limited without departing from claim, form can be carried out to it
With the various changes in details.
Claims (10)
1. it is a kind of to scan holding register, it is characterised in that to include：
Power circuit, holding control circuit, scan selection circuit, main latch, from latch,
Wherein, power circuit is to keeping control circuit, scan selection circuit, main latch and powering from latch,
Control circuit is kept in response to the external timing signal from external reception and control signal output internal clock signal is kept
Control signal is kept with internal,
Scan selection circuit selects the scanning signal and work letter from external reception according to the scan control signal from external reception
Number one of as internal signal and export internal signal,
Main latch is series at scan selection circuit and between latch, in response to from the inside for keeping control circuit to receive when
Clock signal, receives the internal signal of scan selection circuit output, exports reverse inside letter by the internal signal for receiving reversely
Number, or latch the internal signal for receiving and export reverse internal signal,
From responsive in control signal is kept from the inside for keeping control circuit to receive, the reverse of main latch output is received
Internal signal, export internal signal, or latch the reverse inside for receiving by the reverse internal signal for receiving again reversely
Signal simultaneously exports internal signal, or preserves the reverse internal signal for receiving,
Wherein, internal signal is exported by the output end from latch from latch, also, is described from the output end of latch
The output end of scanning holding register.
2. it is as claimed in claim 1 to scan holding register, wherein, keep control circuit to include：
Internal clock signal generation circuit, in response to the external timing signal output internal clock signal from external reception, wherein,
Internal clock signal includes clock signal and reverse clock signal；
Inside keeps control signal to produce circuit, produces in response to the holding control signal from external reception and from internal clock signal
The reverse clock signal that raw circuit is received, output is internal to keep control signal.
3. it is as claimed in claim 2 to scan holding register, wherein, power circuit provides the first power supply and second source,
Second source to from latch and it is internal keep control signal to produce circuit powering, the first power supply to scan selection circuit,
Main latch and internal clock signal generation circuit are powered,
Wherein, second source continued power, the first power supply from the holding control signal of external reception in response to powering or disconnecting confession
Electricity.
4. it is as claimed in claim 3 to scan holding register, wherein,
It is to keep signal or non-holding signal from the holding control signal of external reception,
First power supply is supplied scan selection circuit, main latch and internal clock signal generation circuit in response to non-holding signal
Electricity, in response to keeping signal to disconnect the power supply to scan selection circuit, main latch and internal clock signal generation circuit.
5. it is as claimed in claim 4 to scan holding register, wherein,
Inside keeps control signal to include that clock keeps control signal and reverse clock to keep control signal, wherein,
It is that clock triggering keeps control signal or clock non-toggle to keep control signal that clock keeps control signal,
It is that reverse clock triggering keeps control signal or reverse clock non-toggle to keep that reverse clock keeps control signal
Control signal.
6. it is as claimed in claim 5 to scan holding register, wherein,
Inside keeps control signal to produce circuit in response to the non-holding signal from external reception and from internal clock signal generation
The reverse clock signal that circuit is received, output is internal to keep control signal, wherein,
From responsive in keeping control signal to produce the clock triggering that circuit receives keeping control signal and reversely from internal
Clock triggering keep control signal, the reverse internal signal of main latch output is received, by the reverse inside letter for receiving
Number again reversely, internal signal is exported.
7. it is as claimed in claim 6 to scan holding register, wherein, from responsive in from internal holding control signal product
The clock non-toggle that raw circuit is received keeps control signal and reverse clock non-toggle keeps control signal, what latch was received
Reverse internal signal simultaneously exports internal signal.
8. it is as claimed in claim 5 to scan holding register, wherein,
Inside keeps control signal to produce circuit and produces electricity in response to the holding signal from external reception and from internal clock signal
The reverse clock signal that road receives, exports clock non-toggle and keeps control signal and reverse clock non-toggle to keep control letter
Number, wherein,
From responsive in keeping control signal to produce the clock non-toggle that circuit receives keeping control signal and anti-from internal
To clock non-toggle keep control signal, preserve the reverse internal signal that receives.
9. it is as claimed in claim 1 to scan holding register, wherein,
The scan control signal from external reception is scan pattern signal or mode of operation signal,
When scan selection circuit from the scan control signal of external reception be scan pattern signal when, select sweeping from external reception
Signal is retouched as internal signal and internal signal is exported, when the scan control signal from external reception is mode of operation signal,
Select as internal signal and to export internal signal from the working signal of external reception.
10. it is as claimed in claim 4 to scan holding register, wherein,
Clock signal is that clock trigger signal or clock non-touch are signaled,
Reverse clock signal is that reverse clock trigger signal or reverse clock non-touch are signaled, wherein,
Main latch signals and reverse clock non-touch in response to the clock non-touch received from internal clock signal generation circuit
Signal, receive the internal signal of scan selection circuit output, export reverse inside letter by the internal signal for receiving reversely
Number, or the clock trigger signal in response to receiving from internal clock signal generation circuit and reverse clock trigger signal, latch
The internal signal that receives simultaneously exports reverse internal signal.
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|---|---|---|---|
| CN201410193399.XA CN103986455B (en) | 2014-05-09 | 2014-05-09 | Scanning holding register |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410193399.XA CN103986455B (en) | 2014-05-09 | 2014-05-09 | Scanning holding register |
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| CN103986455A CN103986455A (en) | 2014-08-13 |
| CN103986455B true CN103986455B (en) | 2017-04-12 |
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| CN113131929A (en) * | 2020-01-15 | 2021-07-16 | 夏泰鑫半导体(青岛)有限公司 | Frequency dividing circuit and ring oscillator with same |
| CN112164371B (en) * | 2020-10-14 | 2022-02-22 | 武汉华星光电半导体显示技术有限公司 | Drive circuit and display panel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102780471A (en) * | 2011-05-12 | 2012-11-14 | 株式会社日立显示器 | Latch circuit and display device using the latch circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7154317B2 (en) * | 2005-01-11 | 2006-12-26 | Arm Limited | Latch circuit including a data retention latch |
| US20070085585A1 (en) * | 2005-10-13 | 2007-04-19 | Arm Limited | Data retention in operational and sleep modes |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102780471A (en) * | 2011-05-12 | 2012-11-14 | 株式会社日立显示器 | Latch circuit and display device using the latch circuit |
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