CN103972278A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN103972278A CN103972278A CN201310037707.5A CN201310037707A CN103972278A CN 103972278 A CN103972278 A CN 103972278A CN 201310037707 A CN201310037707 A CN 201310037707A CN 103972278 A CN103972278 A CN 103972278A
- Authority
- CN
- China
- Prior art keywords
- work function
- function material
- material portion
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 157
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 230000008859 change Effects 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 abstract description 128
- 230000000694 effects Effects 0.000 abstract description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 238000005240 physical vapour deposition Methods 0.000 description 14
- 239000003989 dielectric material Substances 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910017121 AlSiO Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- -1 LaSiO Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate and a grid electrode structure, the grid electrode structure is provided with a work function changing layer which comprises first work function material portions and second work function material portions, the first work function material portions are transversely arranged in the work function changing layer at intervals, and the second work function material portions are arranged among the first work function material portions. By adjusting and controlling different work function materials or different deposition thicknesses, a central area and an edge area of the grid electrode structure are enabled to have different work functions, so that a grid electrode in the semiconductor device is enabled to have sufficient electric control capability, and short channel effect of the semiconductor device is improved.
Description
Technical field
The application relates to semiconductor and field of semiconductor fabrication processes, relates in particular to metal oxide layer semiconductor field-effect transistor (MOSFET) and manufacturing process thereof.
Background technology
Along with reducing gradually of MOSFTE device, especially the reducing gradually of gate electrode size in MOSFTE device, some new problems are following.What in these problems, be subject to people's extensive concern is short-channel effect.The harmful effect that short channel produces is as follows:
(1) affect short ditch, the narrow channel effect of threshold voltage
After channel length is reduced to a certain degree, the depletion region of source, drain junction shared proportion in whole raceway groove increases, and the silicon face below grid forms the required quantity of electric charge of inversion layer and reduces, thereby threshold voltage reduces.In substrate, depletion region increases threshold voltage along the electric charge of channel width side direction dwell portion simultaneously.In the time that channel width is reduced to the same magnitude of depletion width, it is very remarkable that threshold voltage increase becomes.Short channel device threshold voltage is very responsive to the variation of channel length.
(2) mobility field correlation effect and carrier velocity saturation effect
Low mobility is after the match constant, and carrier velocity increases with electric field is linear.Under High-Field, mobility declines, and carrier velocity reaches capacity, no longer relevant with electric field.Speed saturated on device to affect one be that drain terminal saturation current is reduced greatly, another is that to make the relation of saturation current and grid voltage be no longer the nearly quadratic relationship in long channel device, but linear relationship.
(3) affect the hot carrier's effect of device lifetime
Device size enters the long scope of deep-submicron ditch, and the electric field strength of device inside reduces and strengthens with device size, has especially highfield near drain junction, and charge carrier obtains higher energy in this highfield, becomes hot carrier.Hot carrier affects device performance aspect two: 1) cross Si-SiO
2potential barrier, is injected in oxide layer, and constantly accumulation, changes threshold voltage, affects device lifetime; 2) near depletion region drain junction, produce electron hole pair with lattice collisions, to NMOS pipe, the electronics that collision produces forms additional leakage current, and hole is collected by substrate, forms substrate current, makes total current become drain saturation current and substrate current sum.Substrate current is larger, illustrates that the collision frequency occurring in raceway groove is more, and corresponding hot carrier's effect is more serious.Hot carrier's effect is one of Fundamentals of limiting device maximum operating voltage.
(4) subthreshold performance degradation, device folder constantly
Subthreshold region leakage current makes MOSFET device close step response variation, and it is large that quiescent dissipation becomes.In dynamic circuit and memory cell, it is chaotic that it also may cause logic state to occur.Thereby the leakage induced barrier being caused by short channel reduction (DIBL) effect becomes a basic physical effect that determines Short Channel MOS Devices dimension limit.
In view of the harmful effect that short-channel effect produces, how to improve short-channel effect and become the problem that people are inquiring into all the time.At metal-oxide layer-semiconductor-field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), in manufacture field, people once attempted by non-impurity-doped is set in semiconductor device, thinner passage reduces the impact of short-channel effect on device performance.But along with the application of this technology, although people find to adopt this non-impurity-doped, thinner channel design can reduce the impact of short-channel effect, but other performances of MOSFET device have also been brought to adverse effect.Therefore, the series of problems such as short channel, connection of semiconductor device, has become the bottleneck problem that hinders MOSFET device size further to dwindle.
Summary of the invention
The application provides a kind of semiconductor device, comprises substrate and grid structure, and grid structure has Work function Change layer, and this Work function Change layer comprises: the first work function material portion, is arranged on to lateral separation in described Work function Change layer; And be arranged on the second work function material portion between the first work function material portion being horizontally arranged at interval.
The application also provides a kind of manufacture method of semiconductor device, and the method comprises: step S1 deposits successively gate dielectric layer, the first workfunction material, polysilicon layer and hard mask layer on substrate; Step S2, this hard mask layer of patterning, and form pseudo-side wall layer on the hard mask sidewall of patterning; Step S3, etching forms pseudo-grid structure, and forms side wall layer on the sidewall of pseudo-grid structure; Step S4, insulation dielectric layer between sedimentary deposit, and carry out planarization; Step S5, removes hard mask layer, part polysilicon layer and the first workfunction material in pseudo-grid; Step S6, returns and carves layer insulation dielectric layer, and remove pseudo-side wall layer and remaining polysilicon layer, forms the first work function material portion; Step S7, deposition the second work function material, forms the second work function material portion and step S8, and deposition gate material forms semiconductor device.
Semiconductor device providing by the application and preparation method thereof, has obtained having in a kind of grid structure the semiconductor device of Work function Change layer.By the regulation and control of different work functions material or different deposit thickness, make the central area of grid structure there is different work functions from fringe region, and then make the grid in semiconductor device there is enough automatically controlled abilities, improve the short-channel effect of semiconductor device.
Brief description of the drawings
Fig. 1-3 show the semiconductor device cross-section schematic diagram of the embodiment that the application provides;
Fig. 4 shows the schematic flow sheet of the method, semi-conductor device manufacturing method that the application provides;
Fig. 5-12 show the cross-sectional view of semiconductor device in the semiconductor device preparation method different step that the application provides.
Embodiment
Below in conjunction with the embodiment of the present application, technical scheme to the application is described in detail, but following embodiment understands the application, and can not limit the application, feature in embodiment and embodiment in the application can combine mutually, and the multitude of different ways that the application can be defined by the claims and cover is implemented.
" the Work function Change layer " of the application's indication refers to that this structure makes grid structure have variable work function along the horizontal direction of grid inwall, and such structure is referred to as Work function Change layer in this application.The application's so-called " laterally " refers to perpendicular to the upwards direction of Direction of superposition of each parts in semiconductor device, in other words, should " laterally " refer to the direction that is parallel to substrate bearing of trend.
Fig. 1 shows the semiconductor device cross-section schematic diagram in the embodiment that the application provides.This semiconductor device comprises substrate 100, gate dielectric layer 110,120(is optional on TiN barrier layer), side wall layer 130, Work function Change layer 140 and gate electrode 150.Work function Change layer 140 is arranged on grid structure inwall bottom, comprising: the first work function material portion 142, is spaced apart and arranged in Work function Change layer 140; The second work function material portion 144, is arranged between the first work function material portion 142.Wherein, the first work function material portion 142 has height H 1, the second work function material portion 144 and has height H 2.When the first work function material that forms the first work function material portion is with the second work function material of formation the second work function material portion when identical, H1>H2 or H1<H2.By controlling the height of the first work function material portion and the second work function material portion, on the horizontal or longitudinal direction of grid structure, there is different work functions thereby realize Work function Change layer; In the time that the first work function material of formation the first work function material portion is not identical with the second work function material of formation the second work function material portion, H1 >=H2 or H1≤H2.In this Work function Change layer structure, owing to having different work functions between the first work function material and the second work function material, therefore grid structure can have different work functions in a lateral direction.Further, by regulating the height of H1 and H2, make the first work function material portion 142 there is different height from the second work function material portion 144, also can make grid structure there is in a lateral direction different work functions.
Fig. 2 shows the semiconductor device cross-section schematic diagram in another embodiment that the application provides.From different shown in Fig. 1, the second work function material portion 144 stretches out near the part of the first work function material portion 142, is covered to the upper surface of small part the first work function material portion 142.In this Work function Change layer structure, the first work function material that forms the first work function material portion and the second work function material of formation the second work function material portion can be identical can be not identical yet, H1 >=H2 or H1≤H2.Owing to thering is different work functions between the first work function material and the second work function material, and the first work function material portion that is coated with the second work function material from do not cover between the first work function material portion of the second work function material, be coated with between the first work function material portion of the second work function material and the second work function material portion and do not cover the first work function material portion of the second work function material and the second work function material portion between there is different work functions, therefore grid structure has different work functions in a lateral direction.
Fig. 3 shows the semiconductor device cross-section schematic diagram in another embodiment that the application provides.From different shown in Fig. 2, the second work function material portion 144 stretches out near the part of the first work function material portion 142, covers the upper surface of whole the first work function material portions 142, and upwards extends along the sidewall of grid structure.In this Work function Change layer structure, owing to thering is different work functions between the first work function material and the second work function material, and the gate lateral wall that is coated with the second work function material from be coated with between the first work function material portion of the second work function material, be coated with between the first work function material portion of the second work function material and the second work function material portion and there is different work functions, therefore gate electrode has different work functions in a lateral direction.
In said structure, the first work function material portion 142 and the second work function material portion 144 are formed by the first work function material and the second work function material respectively.The first work function material and the second work function material can be dopants, or in particular, are counter doping agent (counter-dopant), conventional dopant includes but not limited to: contain arsenic, the dopant of boron and phosphorus, and the dopant that contains indium and antimony, or Ni, Pt, Pd.Typically, every III-th family (being P type) and the dopant of V family (being N-type) all can be applied in the application.The first work function material can be identical with the second work function material, also can be different.If the first work function material is identical with the second work function material, H1 is different from H2, and different by the first work function material portion and the second work function material portion height regulate the horizontal work function of grid structure; If the first work function material is different from the second work function material, H1 and H2 can be the same or different, by the regulation and control of material and/or height, make the central area of above-mentioned grid structure there is different work functions from fringe region, and then make the grid in semiconductor device there is enough automatically controlled abilities, improve semiconductor device, for example the short-channel effect of MOSFET device.
The semiconductor device substrates 100 providing in the application can be silicon substrate, also can have doped region, for example P well and N well area; Substrate 100 can also comprise SOI(semiconductor-on-insulator) structure, or there is the structures such as dielectric layer, the suitable structures that other those skilled in the art can expect is all in the scope of the application's protection.On substrate, also comprise that multiple insulating groove structures (STI) are with the multiple active areas on isolation of semiconductor.The formation step of STI comprises: etching groove on substrate, use SiO
2or Si
3n
4deng material filling groove, finally form sti structure.Method and the packing material of this formation sti structure are prior art, do not repeat them here.
The gate dielectric layer 110 providing in the application can be selected from silicon dioxide, silicon nitride, high-k dielectric material or other applicable materials; High-k dielectric material can be LaO, AlO, ZrO, TiO, Ta
2o
5, Y
2o
3, SrTiO
3, BaTiO
3, BaZrO, Hf
3zrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al
2o
3, Si
3n
4and other applicable materials.The method that forms gate dielectric layer comprises the combination of ald, chemical vapour deposition (CVD), physical vapour deposition (PVD), thermal oxidation, UV-ozone oxidation (UV-ozone oxidation) or said method.
The gate electrode 150 that the application provides can be metal, metal alloy, metal nitride or metal silicide, polysilicon, and other applicable materials.The method that forms gate electrode comprises ald, chemical vapour deposition (CVD); the conventional methods such as the combination of physical vapour deposition (PVD) or said method; said method, by conventionally known to one of skill in the art, in the scope that it is conventional or distortion is all protected in the application, does not repeat them here.
The side wall layer 130 that the application provides can be some dielectric materials, preferably adopts the dielectric material of some low-ks, for example, and the dielectric material that dielectric constant is less than 4.The method that forms side wall layer comprises chemical vapour deposition (CVD), the combination of physical vapour deposition (PVD) or said method, and said method, by conventionally known to one of skill in the art, in the scope that it is conventional or distortion is all protected in the application, does not repeat them here.
Fig. 4 shows the schematic flow sheet of the method, semi-conductor device manufacturing method that the application provides.First carry out step S1, on substrate, deposit successively gate dielectric layer, the first workfunction material, polysilicon layer and hard mask layer; Then carry out step S2, this hard mask layer of patterning, and form pseudo-side wall layer on the hard mask sidewall of patterning; Carry out subsequently step S3, etching forms pseudo-grid structure, and forms side wall layer on the sidewall of pseudo-grid structure; Then carry out step S4, insulation dielectric layer between sedimentary deposit, and carry out planarization; Then carry out step S5, remove hard mask layer, part polysilicon layer and part the first workfunction material in pseudo-grid; Next carry out step S6, return and carve layer insulation dielectric layer, and remove pseudo-side wall layer and remaining polysilicon layer, form the first work function material portion being horizontally arranged at interval; Carry out subsequently step S7, between the first work function material portion being horizontally arranged at interval, deposit the second work function material, form the second work function material portion, thus the Work function Change layer being formed by the first work function material portion and two work function material portions; Then carry out step S8, deposition gate material forms semiconductor device.
As shown in Figure 5, on substrate 100, deposit successively gate dielectric layer 110, the first workfunction material 142, polysilicon layer 160 and hard mask layer 170.Gate dielectric layer 110 can be selected from silicon dioxide, silicon nitride, high-k dielectric material or other applicable materials; High-k dielectric material can be LaO, AlO, ZrO, TiO, Ta
2o
5, Y
2o
3, SrTiO
3, BaTiO
3, BaZrO, Hf
3zrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al
2o
3, Si
3n
4and other applicable materials.The method that forms gate dielectric layer comprises the combination of ald, chemical vapour deposition (CVD), physical vapour deposition (PVD), thermal oxidation, UV-ozone oxidation (UV-ozoneoxidation) or said method.The first work function material can be dopant, conventional dopant includes but not limited to: contain arsenic, the dopant of boron and phosphorus, and the dopant that contains indium and antimony, typically, every III-th family (being P type) and the dopant of V family (being N-type) all can be applied in the application.The method of this deposition work function material (for example dopant) is prior art, does not repeat them here.In another embodiment as the application, can be before the first work function material be deposited to gate dielectric layer, depositing TiN barrier layer 120 on gate dielectric layer, the method on depositing TiN barrier layer 120 comprises the conventional method such as chemical vapour deposition (CVD), physical vapour deposition (PVD).
Complete after above-mentioned steps, deposit spathic silicon layer 160 in the first workfunction material 142, and on polysilicon layer 160, deposit hard mask layer 170; Hard mask layer 170 can be silicon nitride layer, and the method for deposition comprises ald, chemical vapour deposition (CVD), physical vapour deposition (PVD) or other applicable methods.The thickness of silicon nitride layer can be at 20-30nm.Because the method for deposit spathic silicon layer 160 and hard mask layer 170 is by conventionally known to one of skill in the art, so in the scope that it is conventional or distortion is all protected in the application, do not repeat them here.
As shown in Figure 6, complete after above-mentioned steps, by hard mask layer 170 patternings, and forming pseudo-side wall layer 180 on the hard mask sidewall of patterning; The manufacture method of mask pattern and pseudo-side wall layer 180, by conventionally known to one of skill in the art, in the scope that it is conventional or distortion is all protected in the application, does not repeat them here.
As shown in Figure 7, complete after above-mentioned steps, to polysilicon layer 160, the first workfunction material 142, gate dielectric layer 110 carries out etching until substrate top surface forms pseudo-grid structure.On the sidewall of pseudo-grid structure, form side wall layer 130.In the embodiment providing in the application, adopt dry etching method to carry out etching, etching gas is CH
xfy/O
2or SF
6/ CH
xfy/He(is x=1 to 3 wherein, y=4-x), or other applicable gases.Gas pressure in dry etching is 1mT to 1000mT, and power is 500W to 3000W, and bias-voltage is 100V to 500V, CH
xthe air velocity of Fy is 10sccm to 500sccm, and the air velocity of He is 10sccm to 1000sccm.The side wall layer 130 that the application provides can be some dielectric materials, preferably adopts the dielectric material of some low-ks, the dielectric material that for example dielectric constant is less than 4.The method that forms side wall layer comprises the combination of chemical vapour deposition (CVD), physical vapour deposition (PVD) or said method, and said method, by conventionally known to one of skill in the art, in the scope that it is conventional or distortion is all protected in the application, does not repeat them here.
As shown in Figure 8, complete after above-mentioned steps, need to be between the sedimentary deposit of the both sides of pseudo-grid insulation dielectric layer 200, and carry out planarization.The material that can form layer insulation dielectric layer 200 includes but not limited to the dielectric material that dielectric constant is less than 4; form layer insulation dielectric layer 200 and the method for its planarization is to prior art; for example flattening method includes but not limited to chemical-mechanical planarization; because said method is by conventionally known to one of skill in the art; in the scope that it is conventional or distortion is all protected in the application, do not repeat them here.
As shown in Figure 9, complete after above-mentioned steps, need further to remove hard mask layer, part polysilicon layer and part the first workfunction material in pseudo-grid.In the embodiment providing in the application, what remove that hard mask layer in pseudo-grid, part polysilicon and the first workfunction material adopt is dry etching, and etching gas is HBr/Cl
2/ O
2/ He, air pressure is 1mT to 1000mT, and power is 50W to 1000W, and bias-voltage is 100V to 500V, and the air velocity of HBr is 10sccm to 500sccm, Cl
2air velocity be 0sccm to 500sccm, O
2air velocity be 0sccm to 100sccm, the air velocity of He is 0sccm to 1000sccm.After etching, due to the existence of pseudo-side wall layer 180, the polysilicon layer 160 and the first work function material portion 142 that are arranged in pseudo-side wall layer 180 belows are still retained in grid structure.
As shown in figure 10, by the polysilicon portion etching remaining in grid structure, layer insulation dielectric layer is returned to quarter, and etching is removed polysilicon for further.Returning and carving the method adopting is dry etching, and concrete method, for those skilled in the art know, does not repeat them here; Can adopt the method for dry etching to polysilicon, etching gas can be CH
xfy/O
2or SF
6/ CH
xfy/He(is x=1 to 3 wherein, y=4-x), or other applicable gases.After above-mentioned etching, pseudo-side wall layer 180 and remaining polysilicon layer 160 are all removed.
As shown in figure 11, removing after pseudo-side wall layer 180 and polysilicon layer 160, on layer insulation dielectric layer 200 and grid structure, deposit the second work function material, form the second work function material portion 144.The first work function material portion 142 between the second work function material portion 144 cover layers in insulation dielectric layer 200 and grid structure and gate dielectric layer 110 or TiN barrier layer 120.
As shown in figure 12, metal ion is deposited in grid structure, form gate electrode 150, obtain a kind of semiconductor device that the application provides.In an embodiment provided by the invention, forming after gate electrode 150, further comprise the step of planarization.The material that forms gate electrode can be metal, metal alloy, metal nitride or metal silicide, polysilicon, and other applicable materials.Form the step of gate electrode and planarization all by conventionally known to one of skill in the art, in the scope that it is conventional or distortion is all protected in the application, do not repeat them here.
Preferably, in the technical scheme that the application provides, can between step S7 and step S8, further comprise step S7 ': selective etch is removed part the second work function material portion.In the embodiment providing in the application, step S7 ' further comprises step S71 ', in the upper base surface of the second work function material portion, deposit hard mask layer, this hard mask layer at least covers the upper surface of the second work function material portion between the first work function material portion; Step S72 ', etching is removed the second work function material portion being exposed to outside hard mask layer; And step S73 ', remove hard mask layer.The material that can form hard mask layer is the materials such as oxide, polysilicon; as long as can make the structure of hard mask layer protection not be subject to the impact of etching; and be exposed to the second workfunction material outside hard mask layer material of removing that is etched, all can be used for forming hard mask layer.The etching condition that this step adopts can be wet etching, can be also dry etching, and those skilled in the art can select concrete etching condition according to the material of the second work function material and formation hard mask layer completely.Through above-mentioned steps, can obtain the Work function Change layer that Fig. 1 and Fig. 2 form.
The semiconductor device providing in the application is only the application's preferred embodiment, and this semiconductor device can be digital circuit, image sensing apparatus, heterogeneous semiconductor device, dynamic random access storage unit, single-electronic transistor or other microelectronic devices.Certainly the preparation method that the application provides also may be used on other transistors, and for example, single gate transistor, double-gated transistor or multiple-gate transistor, also can be applied in sensing unit, mnemon or logical block.
The preferred embodiment that the foregoing is only the application, is not limited to the application, and for a person skilled in the art, the application can have various modifications and variations.All within the application's spirit and principle, any amendment of doing, be equal to replacement, improvement etc., within all should being included in the application's protection range.
Claims (13)
1. a semiconductor device, comprises substrate and grid structure, it is characterized in that, has Work function Change layer in described grid structure, and described Work function Change layer comprises:
The first work function material portion, is arranged on to lateral separation in described Work function Change layer; And
The second work function material portion, between the first work function material portion being horizontally arranged at interval described in being arranged on.
2. semiconductor device according to claim 1, is characterized in that, the height of described the first work function material portion is H
1, the height of described the second work function material portion is H
2, wherein, when the first work function material that forms described the first work function material portion is with the second work function material of described the second work function material portion of formation when identical, described H
1>H
2or H
1<H
2.
3. semiconductor device according to claim 1, is characterized in that, the height of described the first work function material portion is H
1, the height of described the second work function material portion is H
2, wherein, in the time that the first work function material of described the first work function material portion of formation is not identical with the second work function material of described the second work function material portion of formation, described H
1>=H
2or H
1≤ H
2.
4. according to the semiconductor device described in any one in claims 1 to 3, it is characterized in that, described the second work function material portion stretches out near the part of described the first work function material portion, is covered to the upper surface of the first work function material portion described in small part.
5. semiconductor device according to claim 4, is characterized in that, described the second work function material portion covers all upper surfaces of described the first work function material portion, and upwards extends along the inwall of described grid structure.
6. according to the semiconductor device described in any one in claim 1 to 5, it is characterized in that, described Work function Change layer is arranged on the bottom of described grid structure.
7. semiconductor device according to claim 1, is characterized in that, described grid structure further comprises:
Gate dielectric layer, is arranged on described substrate;
Gate electrode, is arranged on described Work function Change layer; And
Side wall layer, is arranged on the lateral wall of described grid structure.
8. semiconductor device according to claim 7, is characterized in that, is further provided with TiN barrier layer on described gate dielectric layer.
9. according to the semiconductor device described in any one in claim 1 to 8, it is characterized in that, described the first work function material portion and described the second work function material portion comprise dopant.
10. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S1 deposits successively gate dielectric layer, the first workfunction material, polysilicon layer and hard mask layer on substrate;
Step S2, hard mask layer described in patterning, and form pseudo-side wall layer on the hard mask sidewall of patterning;
Step S3, etching forms pseudo-grid structure, and forms side wall layer on the sidewall of described pseudo-grid structure;
Step S4, insulation dielectric layer between sedimentary deposit, and carry out planarization;
Step S5, removes hard mask layer, part polysilicon layer and the first workfunction material in described pseudo-grid;
Step S6, returns and carves described layer insulation dielectric layer, and remove described pseudo-side wall layer and remaining polysilicon layer, forms the first work function material portion;
Step S7 deposits the second work function material between described the first work function material portion, forms the second work function material portion; And
Step S8, deposition gate material, forms described semiconductor device.
11. manufacture methods according to claim 10, is characterized in that, in described step S1, deposit the step that further comprises depositing TiN barrier layer after gate dielectric layer on substrate.
12. manufacture methods according to claim 10, is characterized in that, between described step S7 and described step S8, enter one
Step comprises step S7 ': selective etch is removed described the second work function material portion of part.
13. manufacture methods according to claim 12, is characterized in that, described step S7 ' comprising:
Step S71 ' deposits hard mask layer in the upper base surface of described the second work function material portion, and described hard mask layer at least covers the upper surface of the second work function material portion between described the first work function material portion;
Step S72 ', etching is removed the second work function material portion being exposed to outside described hard mask layer; And
Step S73 ', removes described hard mask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310037707.5A CN103972278B (en) | 2013-01-30 | 2013-01-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310037707.5A CN103972278B (en) | 2013-01-30 | 2013-01-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103972278A true CN103972278A (en) | 2014-08-06 |
| CN103972278B CN103972278B (en) | 2017-05-10 |
Family
ID=51241579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310037707.5A Active CN103972278B (en) | 2013-01-30 | 2013-01-30 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103972278B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022035A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN109216353A (en) * | 2017-07-07 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Input and output device sum aggregate is at circuit and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6097070A (en) * | 1999-02-16 | 2000-08-01 | International Business Machines Corporation | MOSFET structure and process for low gate induced drain leakage (GILD) |
| CN102349133A (en) * | 2009-01-12 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing a semiconductor device |
| CN102386217A (en) * | 2010-09-01 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Grid stack structure and manufacturing method thereof |
-
2013
- 2013-01-30 CN CN201310037707.5A patent/CN103972278B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6097070A (en) * | 1999-02-16 | 2000-08-01 | International Business Machines Corporation | MOSFET structure and process for low gate induced drain leakage (GILD) |
| CN102349133A (en) * | 2009-01-12 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing a semiconductor device |
| CN102386217A (en) * | 2010-09-01 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Grid stack structure and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022035A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN104022035B (en) * | 2013-02-28 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN109216353A (en) * | 2017-07-07 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Input and output device sum aggregate is at circuit and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103972278B (en) | 2017-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10522419B2 (en) | Stacked field-effect transistors (FETs) with shared and non-shared gates | |
| US20190189766A1 (en) | Protection of high-k dielectric during reliability anneal on nanosheet structures | |
| US8889500B1 (en) | Methods of forming stressed fin channel structures for FinFET semiconductor devices | |
| US10892328B2 (en) | Source/drain extension regions and air spacers for nanosheet field-effect transistor structures | |
| US11804484B2 (en) | FinFet isolation structure and method for fabricating the same | |
| US10141263B2 (en) | Method for fabricating semiconductor device | |
| CN104576735A (en) | FinFET with Buried Insulator Layer and Method for Forming | |
| KR20150021448A (en) | Silicon and silicon germanium nanowire formation | |
| CN103378155A (en) | Dummy finfet structure and method of making same | |
| CN104701310A (en) | Semiconductor device with profiled work-function metal gate electrode and method of making | |
| CN104821296A (en) | Semiconductor device and forming method thereof | |
| CN103858215A (en) | Non-planar transistors and methods of fabrication thereof | |
| CN105261651A (en) | Semiconductor device with a plurality of transistors | |
| US7579282B2 (en) | Method for removing metal foot during high-k dielectric/metal gate etching | |
| CN104183487A (en) | FinTFET semiconductor device and manufacturing method thereof | |
| CN104637818A (en) | Method for manufacturing fin field-effect transistor, and fin field-effect transistor thereof | |
| CN102097382B (en) | Method for manufacturing semiconductor device | |
| US20170133501A1 (en) | Finfet isolation structure and method for fabricating the same | |
| CN104425594A (en) | Fin field effect transistor and forming method thereof | |
| CN103972278B (en) | Semiconductor device and manufacturing method thereof | |
| US9117930B2 (en) | Methods of forming stressed fin channel structures for FinFET semiconductor devices | |
| US9159567B1 (en) | Replacement low-K spacer | |
| CN104217948B (en) | Semiconductor manufacturing method | |
| CN103915387B (en) | The forming method of CMOS transistor | |
| CN107591368B (en) | Multi-threshold voltage fin field effect transistor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |