CN103972275B - Semiconductor device and the method to manufacture semiconductor device - Google Patents
Semiconductor device and the method to manufacture semiconductor device Download PDFInfo
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- CN103972275B CN103972275B CN201310037498.4A CN201310037498A CN103972275B CN 103972275 B CN103972275 B CN 103972275B CN 201310037498 A CN201310037498 A CN 201310037498A CN 103972275 B CN103972275 B CN 103972275B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 191
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 72
- 239000007943 implant Substances 0.000 claims abstract description 39
- 239000002019 doping agent Substances 0.000 claims abstract description 34
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 123
- 229920005591 polysilicon Polymers 0.000 claims description 121
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 14
- 229910052796 boron Inorganic materials 0.000 claims description 14
- 230000008595 infiltration Effects 0.000 claims description 13
- 238000001764 infiltration Methods 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000035699 permeability Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000012466 permeate Substances 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 239000010410 layer Substances 0.000 description 165
- 239000004020 conductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002365 multiple layer Substances 0.000 description 3
- 229910007264 Si2H6 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- SVXHDONHRAZOCP-UHFFFAOYSA-N ethane;silicon Chemical compound [Si].CC SVXHDONHRAZOCP-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of method the invention relates to semiconductor device and to manufacture semiconductor device.Wherein semiconductor device has barrier semiconductor layer, and the amount of the semiconductor layer implant is infiltrated through below barrier semiconductor layer is minimized.The crystal grain and/or the dopant of low concentration of relatively thin or reduced size can be had by obstructing semiconductor layer, and the amount for the semiconductor layer that implant is infiltrated through below barrier semiconductor layer is minimized.
Description
Technical field
The present invention relates to a kind of semiconductor device, more particularly to a kind of mul-tiple layers of polysilicon to suppress implant infiltration
Semiconductor device and method to manufacture semiconductor device.
Background technology
Implant is used in the manufacture of semiconductor device, and is used as dopant.For example, boron is typically implanted semiconductor
The different layers of device are used as dopant.Boron generally infiltrates into the floating gate of semiconductor device, as a result causes series of questions, including
But it is not limited to critical voltage to be offset from the element of semiconductor device, and reduces device reliability.Therefore, implant infiltration is suppressed
Floating gate to semiconductor device is desirable.
As can be seen here, above-mentioned existing semiconductor device and to manufacture the method for semiconductor device in product structure, system
Make method upper with using, it is clear that still suffered from inconvenience and defect, and be urgently further improved.It is above-mentioned in order to solve
Problem, relevant manufactures there's no one who doesn't or isn't painstakingly seek solution, but have no that applicable design has been developed always for a long time
Into, and common product and method can solve the problem that above mentioned problem without appropriate structure and method, this is clearly that related dealer is anxious
The problem of to be solved.Therefore a kind of new semiconductor device and the method to manufacture semiconductor device, real category how to be founded
One of current important research and development problem, also needs improved target as current industry pole.
The content of the invention
It is an object of the present invention to overcome existing semiconductor device and to manufacture semiconductor device method exist
Defect, and a kind of new semiconductor device and the method to manufacture semiconductor device are provided, technical problem to be solved is
It is suppressed the floating gate that implant infiltrates into semiconductor device, be very suitable for practicality.
The object of the invention to solve the technical problems is realized using following technical scheme.According to present invention proposition
A kind of semiconductor device, a barrier semiconductor layer and one first polysilicon layer can be included.Obstructing semiconductor layer has first
The first dopant and the second dopant of concentration.First polysilicon layer is arranged on barrier semiconductor layer.First polysilicon layer can
With the first dopant including the second concentration, and the first concentration is less than the second concentration.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing semiconductor device, wherein first concentration are less than 1E17atom/cm3, and wherein second concentration essence
On between 1E17 to 1E22atom/cm3In the range of.
Foregoing semiconductor device, wherein the barrier semiconductor layer substantially haveDepth, and this more than first
Crystal silicon layer substantially hasDepth.
Foregoing semiconductor device, in addition to：One second polysilicon layer；And a dielectric layer, the dielectric layer is arranged at this
On second polysilicon layer, wherein the barrier semiconductor layer is arranged on the dielectric layer.
Foregoing semiconductor device, the concentration that wherein first dopant is infiltrated into second polysilicon layer is between 1E15
~1E18atom/cm3In the range of.
Foregoing semiconductor device, wherein first polysilicon layer are a control gate, and second polysilicon layer is a floating
Grid.
Foregoing semiconductor device, wherein first dopant are boron (boron) and second dopant is carbon
(carbon)。
Foregoing semiconductor device, the wherein dielectric layer are an oxide layer.
Foregoing semiconductor device, the wherein dielectric layer are monoxide-nitride oxide layer (oxide-
nitride-oxide layer)。
The object of the invention to solve the technical problems is also realized using following technical scheme.According to proposed by the present invention
A kind of semiconductor device, can include a barrier semiconductor layer.Barrier semiconductor layer has the crystal grain of first size scope.Partly lead
Body device can also include one first polysilicon layer, and the first polysilicon layer is arranged on barrier semiconductor layer.First polysilicon layer
There can be the crystal grain of the second size range.The crystal grain of first size scope is less than the crystal grain of the second size range.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
Foregoing semiconductor device, wherein the first size scope are less than 5 nanometers.
Foregoing semiconductor device, wherein second size range are 10 to 20 nanometers.
Foregoing semiconductor device, in addition to：One second polysilicon layer；And a dielectric layer, the dielectric layer is arranged at this
On second polysilicon layer, wherein the barrier semiconductor layer is arranged on dielectric layer.
Foregoing semiconductor device, wherein first polysilicon layer are a control gate, and second polysilicon layer is a floating
Grid.
Foregoing semiconductor device, the wherein dielectric layer are an oxide layer.
Foregoing semiconductor device, the wherein dielectric layer are monoxide-Nitride Oxide lamination (oxide-
nitride-oxide laminated layer)。
Foregoing semiconductor device, wherein barrier semiconductor layer can include first and second dopant.First dopant
With the first concentration, the first polysilicon layer includes the first dopant of the second concentration.First concentration is less than the second concentration.
Foregoing semiconductor device, wherein first dopant are boron, and second dopant is carbon.
Foregoing semiconductor device, wherein the barrier semiconductor layer include the noncrystalline polysilicon (furnace of a boiler tube
Type amorphous polysilicon), a boiler tube crystallizing polysilicon (furnace type crystalline
Polysilicon), the noncrystalline polysilicon of a single-wafer (single wafer amorphous polysilicon) and a monocrystalline
One of circle crystallizing polysilicon (single wafer amorphous polysilicon).The purpose of the present invention and solution
Its technical problem is realized using following technical scheme again in addition.According to one kind proposed by the present invention to manufacture semiconductor device
Method.The method may comprise steps of.Barrier semiconductor layer is provided, barrier semiconductor layer includes first size scope
Crystal grain.Set one first polysilicon layer in barrier semiconductor layer, the first polysilicon layer has the crystal grain of the second size range.
Implant is implanted into semiconductor device.Barrier semiconductor layer can enter implant the second polysilicon layer of semiconductor device
Permeability is minimized.
The object of the invention to solve the technical problems can be also applied to the following technical measures to achieve further.
The foregoing method to manufacture semiconductor device, the wherein crystal grain of first size scope can be less than the second size
The crystal grain of scope.
The foregoing method to manufacture semiconductor device, wherein the first size scope are less than 5 nanometers, and second chi
Very little scope is 10 to 20 nanometers.
The boundary of the foregoing method to manufacture semiconductor device, wherein the barrier semiconductor layer and first polysilicon layer
Face is more the implant infiltration of second polysilicon layer to be minimized.
The foregoing method to manufacture semiconductor device, the wherein implant infiltrate into the concentration of second polysilicon layer
Substantially between 1E15 to 1E18atom/cm3In the range of.
The present invention has clear advantage and beneficial effect compared with prior art.By above-mentioned technical proposal, the present invention
Suppressing the mul-tiple layers of polysilicon of implant infiltration at least has following advantages and beneficial effect：The present invention can suppress implant infiltration
To the floating gate of semiconductor device.
In summary, a kind of method the invention relates to semiconductor device and to manufacture semiconductor device.Wherein
Semiconductor device has barrier semiconductor layer, and the amount of the semiconductor layer implant is infiltrated through below barrier semiconductor layer drops
It is extremely minimum.The crystal grain and/or the dopant of low concentration of relatively thin or reduced size can be had by obstructing semiconductor layer, will implantation
The amount for the semiconductor layer that thing is infiltrated through below barrier semiconductor layer is minimized.The present invention technically has significant progress, and
Really it is a new and innovative, progressive, practical new design with obvious good effect.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description of the drawings
Fig. 1 is the profile for illustrating the semiconductor device that the present invention is disclosed.
Fig. 2 is the profile for illustrating another semiconductor device that the present invention is disclosed.
Fig. 3 A, Fig. 3 B and Fig. 3 C are the schematic diagram for the not be the same as Example for illustrating the semiconductor device that the present invention is disclosed respectively.
Fig. 4 is the datagram for illustrating the boron infiltration that the present invention is disclosed.
100、200、300、320、340：Semiconductor device
102、202、302、322、342：Second polysilicon layer
103：Substrate
104：Second dielectric layer
105：First dielectric layer
106、206、326、346：Obstruct semiconductor layer
107：Interface
108、208、308、328、348：First polysilicon layer
204：ONO layer
304、324、344：Dielectric layer
310、330、350：Implant
400：Datagram
401、403、405：Relation curve
407：Curve
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to mul-tiple layers of polysilicon its embodiment according to suppression implant infiltration proposed by the present invention,
Structure, method, step, feature and its effect, are described in detail as after.
For the present invention foregoing and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Applying in the detailed description of example to clearly appear from.By the explanation of embodiment, it should can reach predetermined to the present invention
The technological means and effect that purpose is taken obtain one and more goed deep into and specific understanding, but institute's accompanying drawings are only to provide reference
With purposes of discussion, not for being any limitation as to the present invention.
Fig. 1 is the schematic diagram for illustrating the semiconductor device 100 that the present invention is disclosed.The semiconductor device 100 that the present invention is disclosed
A substrate 103, the first dielectric layer 105, the second polysilicon layer 102, the second dielectric layer 104, barrier semiconductor layer 106 can be included
And first polysilicon layer 108.In one embodiment, the first dielectric layer 105 can be an oxide layer.Grasped in semiconductor device 100
During work, charge pathway runs through oxide layer.First polysilicon layer 108 can be a control gate structure, and the second polysilicon layer 102 can
To be a floating gate structure.It can be a polysilicon layer to obstruct semiconductor layer 106.Second dielectric layer 104 can include an oxidation
Layer or an ONO laminations.Second dielectric layer 104 is arranged at the top of the second polysilicon layer 102, and barrier semiconductor layer 106 is arranged at the
The top of two dielectric layer 104.The permeability that barrier semiconductor layer 106 can make implant infiltrate into the second polysilicon layer 102 is down to
It is minimum.
In general, implant is minimized or substantially avoids implant from penetrating into half by barrier semiconductor layer 106
The lower section of the barrier semiconductor layer 106 of conductor device 100.Barrier semiconductor layer 106, which can be used in, should suppress implant diffusion
In any case, particularly when implant is the element with relatively small atomic weight, for example：Phosphorus or boron.For example,
When implant is implanted in control gate, the infiltration of implant can be minimized or substantially with barrier semiconductor layer 106
Avoid permeating in n- bits mnemon (n-bit memory cell).
Another embodiment, barrier semiconductor layer 106 can include number Rotating fields, can more be down to the infiltration of dopant most
Lower section that is low or avoiding penetrating into barrier semiconductor layer 106.
Barrier semiconductor layer 106 can be the polysilicon of different kenels.For example, barrier semiconductor layer 106 can be
The polysilicon of furnace-tube type (furnace-type) or single wafer type (single wafer).Such as another embodiment, barrier is partly led
Body layer 106 can be undoped with or the polysilicon of doped carbon.Such as another embodiment, barrier semiconductor layer 106 can be with right and wrong knot
Brilliant polysilicon or crystallizing polysilicon.Therefore, it is possible for the diverse combination of barrier semiconductor layer 106, including does not limit
In boiler tube undoped with noncrystalline polysilicon (furnace type, un-doped amorphous polysilicon), boiler tube not
Adulterate crystallizing polysilicon (furnace type, un-doped crystalline polysilicon), single wafer undoped with
Noncrystalline polysilicon (single wafer, un-doped amorphous polysilicon), single wafer are undoped with crystallization
Polysilicon (single wafer, un-doped crystalline polysilicon) and single wafer carbon doping are noncrystalline more
Crystal silicon (single wafer, carbon-doped amorphous polysilicon).
Boiler tube can be as made by the boiler tube of about 520 DEG C of temperature undoped with noncrystalline polysilicon.Boiler tube is undoped with crystallization
Polysilicon can be as made by the boiler tube of about 620 DEG C of temperature.
In one embodiment, barrier semiconductor layer 106 includes the first dopant and the second dopant.First dopant has
First concentration.First polysilicon layer 108 includes the first dopant of the second concentration.First concentration is approximately less than 1E17atom/
cm3.Second concentration is substantially between 1E17 to 1E22atom/cm3In the range of.
In one embodiment, barrier semiconductor layer 106 has aboutDepth, the first polysilicon layer 108 has big
AboutDepth, and the second dielectric layer 104 have aboutDepth.
In one embodiment, implant is boron, and boron penetrate into the floating gate of semiconductor device be between 1E15~
1E18atom/cm3In the range of.
An interface (interface) 107 is defined between the barrier polysilicon layer 108 of semiconductor layer 106 and first, it can be by
The boron for penetrating into the second polysilicon layer 102 of semiconductor device 100 is minimized.
Implant is minimized to or substantially avoids penetrating into the second polysilicon layer 102 of semiconductor device, is to be used to
Minimize or avoid the undesired critical voltage of semiconductor device 100 to offset.
In another embodiment, barrier semiconductor layer 106 has the polysilicon grain of first size scope, and the first polycrystalline
Silicon layer 108 has the polysilicon grain of the second size range.In one embodiment, the polysilicon grain of first size scope is about few
In 5 nanometers.About 10 to 20 nanometers of the polysilicon grain of first size scope.
In an exemplary embodiment, the polysilicon grain of first size scope is less than the second size range polycrystalline silicon wafer
Grain.The amount that so implant 110 can be allowed to infiltrate through floating gate 102 is minimized.In one embodiment, between barrier semiconductor
Interface between the polysilicon layer 108 of layer 106 and first can more minimize the implant for infiltrating through the second polysilicon layer 102.
In addition, the barrier semiconductor layer 106 of the crystal grain with first size scope can be such that polysilicon more completely fills out
Fill in the chase of semiconductor device 100, substantially to eliminate the space in chase.
In another embodiment, barrier semiconductor layer 106 can include the first dopant and the second dopant, and with the
The polysilicon grain of one size range.First dopant has the first concentration.First polysilicon layer 108 can have the second concentration
The first dopant, and with the second size range polysilicon grain.
Fig. 2 is the profile for illustrating another semiconductor device 200 that the present invention is disclosed.Another semiconductor that the present invention is disclosed
Device 200 includes the first polysilicon layer 208 and a barrier semiconductor layer 206.In one embodiment, the first polysilicon layer 208 is
One control gate structure.Semiconductor device 200 can also include the second polysilicon layer 202.Second polysilicon layer 202 can be floated
Grid structure.Barrier semiconductor layer 206, which can be used to implant (such as boron) infiltrating through the second polysilicon layer 202, to be minimized.Half
Conductor device 200 can also include ONO layer 204, and ONO layer 204 is arranged at the second polysilicon layer 202 and barrier semiconductor layer 206
Between.
Fig. 3 A, Fig. 3 B and Fig. 3 C are the different implementations for illustrating the semiconductor device 300,320,340 that the present invention is disclosed respectively
The schematic diagram of example.Referring initially to shown in Fig. 3 A, semiconductor device 300 include one second polysilicon layer 302, dielectric layer 304 and
First polysilicon layer 308.First polysilicon layer 308 has aboutDepth, dielectric layer 304 have about
Depth.Implant 310 is implanted in semiconductor device 300.
Referring now to shown in Fig. 3 B, semiconductor device 320 includes the second polysilicon layer 322, dielectric layer 324, barrier half
The polysilicon layer 328 of conductor layer 326 and first.In one embodiment, barrier semiconductor layer 326 is by two silicon ethane (Si2H6) and silane
(SiH4) made.First polysilicon layer 328 has aboutDepth, barrier semiconductor layer 326 have aboutDepth, dielectric layer 324 have aboutDepth.Therefore, the dielectric layer of semiconductor device 320 in figure 3b
324th, the total depth of the barrier polysilicon layer 328 of semiconductor layer 326 and first is than Jie for being intended to be semiconductor device 300 in figure 3 a
The total depth of the polysilicon layer 308 of electric layer 304 and first.Refer to again shown in Fig. 3 B, implant 330 is implanted in semiconductor device
In 320.
Referring now to shown in Fig. 3 C, semiconductor device 340 includes the second polysilicon layer 342, dielectric layer 344, barrier half
The polysilicon layer 348 of conductor layer 346 and first.In one embodiment, barrier semiconductor layer 346 is by two silicon ethane (Si2H6) and
C2H4-SiH4It is made.First polysilicon layer 348 has aboutDepth, barrier semiconductor layer 346 have aboutDepth, dielectric layer 344 have aboutDepth.Therefore, in 3C figures semiconductor device 340 dielectric
Layer 344, the total depth of the polysilicon layer 348 of semiconductor layer 346 and first is obstructed than being intended to be semiconductor device 300 in figure 3 a
The total depth of the polysilicon layer 308 of dielectric layer 304 and first, and the dielectric layer 324 of semiconductor device 320, barrier half in Fig. 3 B
The total depth of the polysilicon layer 328 of conductor layer 326 and first.Refer to again shown in Fig. 3 C, implant 350 is implanted in semiconductor device
In 340.
Fig. 4 be illustrate the present invention disclose boron infiltration datagram 400, its depict it is above-mentioned be related to Fig. 3 A, Fig. 3 B and
The infiltration of implant in Fig. 3 C embodiments.The implant used is boron.Concentration (the atoms/cm of implant3) it is with partly leading
The relation of the depth (nanometer) of body device, which is shown, to be come.As shown in Figure 3A, relation curve 401 (case 3) is filled corresponding to semiconductor
300 are put, it does not obstruct semiconductor layer.As shown in Figure 3 C, relation curve 403 (case 1) corresponds to semiconductor device 340.It is bent
Line 407 (case 1) also depicts the high point of concentration of carbon of the semiconductor device 340 in barrier semiconductor layer.As shown in Figure 3 B, close
It is that curve 405 (case 2) corresponds to semiconductor device 320.Depicted in Fig. 4 including barrier (such as Fig. 3 B of semiconductor layer 326,346
And it is depicted in Fig. 3 C) semiconductor device 320,340, semiconductor device 320,340 has substantially low in place of larger depth
The implant of concentration.Therefore, the infiltration of implant (such as boron) can be substantially by barrier semiconductor layer (such as Si2H6And
SiH4；Or Si2H6And C2H4-SiH4) obstructed.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when method and technology contents using the disclosure above make it is a little more
Equivalent embodiment that is dynamic or being modified to equivalent variations, as long as being the content without departing from technical solution of the present invention, according to the present invention's
Any simple modification, equivalent variations and modification that technical spirit is made to above example, still fall within technical solution of the present invention
In the range of.
Claims (23)
1. a kind of semiconductor device, it is characterised in that it includes：
One barrier semiconductor layer, the barrier semiconductor layer includes one first dopant and one second dopant of one first concentration,
The barrier semiconductor layer has the crystal grain of a first size scope；And
One first polysilicon layer, first polysilicon layer is arranged on the barrier semiconductor layer, and first polysilicon layer includes one
First dopant of second concentration, wherein first concentration are less than second concentration, and first polysilicon layer has one second
The crystal grain of size range；
Wherein the crystal grain of the first size scope is less than the crystal grain of second size range.
2. semiconductor device according to claim 1, it is characterised in that wherein first concentration is less than 1E17atom/cm3,
And wherein second concentration is between 1E17 to 1E22atom/cm3In the range of.
3. semiconductor device according to claim 1, it is characterised in that wherein the barrier semiconductor layer hasDepth
Degree, and first polysilicon layer haveDepth.
4. semiconductor device according to claim 1, it is characterised in that it also includes：
One second polysilicon layer；And
One dielectric layer, the dielectric layer is arranged on second polysilicon layer, and wherein the barrier semiconductor layer is arranged at the dielectric layer
On.
5. semiconductor device according to claim 4, it is characterised in that wherein first dopant infiltrate into this more than second
Concentration in crystal silicon layer is between 1E15~1E18atom/cm3In the range of.
6. semiconductor device according to claim 4, it is characterised in that wherein first polysilicon layer is a control gate, should
Second polysilicon layer is a floating gate.
7. semiconductor device according to claim 1, it is characterised in that wherein first dopant be boron and this second mix
Debris is carbon.
8. semiconductor device according to claim 4, it is characterised in that wherein the dielectric layer is an oxide layer.
9. semiconductor device according to claim 4, it is characterised in that wherein the dielectric layer be monoxide-nitride-
Oxide skin(coating).
10. a kind of semiconductor device, it is characterised in that it includes：
One barrier semiconductor layer, the barrier semiconductor layer includes the crystal grain of a first size scope；And
One first polysilicon layer, first polysilicon layer is arranged on the barrier semiconductor layer, and first polysilicon layer includes one
The crystal grain of second size range；
Wherein the crystal grain of the first size scope is less than the crystal grain of second size range.
11. semiconductor device according to claim 10, it is characterised in that wherein the first size scope is less than 5 nanometers.
12. semiconductor device according to claim 10, it is characterised in that wherein second size range is received for 10 to 20
Rice.
13. semiconductor device according to claim 10, it is characterised in that it also includes：
One second polysilicon layer；And
One dielectric layer, the dielectric layer is arranged on second polysilicon layer, and wherein the barrier semiconductor layer is arranged at dielectric layer
On.
14. semiconductor device according to claim 13, it is characterised in that wherein first polysilicon layer is a control gate,
Second polysilicon layer is a floating gate.
15. semiconductor device according to claim 13, it is characterised in that wherein the dielectric layer is an oxide layer.
16. semiconductor device according to claim 13, it is characterised in that wherein the dielectric layer is monoxide-nitridation
Thing-oxide stack.
17. semiconductor device according to claim 10, it is characterised in that wherein the barrier semiconductor layer includes one first
Dopant and one second dopant, first dopant have one first concentration, and first polysilicon layer includes one second concentration
First dopant, and first concentration be less than second concentration.
18. semiconductor device according to claim 17, it is characterised in that wherein first dopant is boron, this second is mixed
Debris is carbon.
19. semiconductor device according to claim 10, it is characterised in that wherein the barrier semiconductor layer includes a boiler tube
Noncrystalline polysilicon, a boiler tube crystallizing polysilicon, the noncrystalline polysilicon of a single-wafer and a single-wafer crystallizing polysilicon are wherein
One of.
20. a kind of method to manufacture semiconductor device, it is characterised in that it comprises the following steps：
There is provided one and obstruct semiconductor layer, the barrier semiconductor layer has the crystal grain of a first size scope；
Set one first polysilicon layer in the barrier semiconductor layer, first polysilicon layer has one second size range
Crystal grain；And
An implant is implanted into the semiconductor device, the wherein implant infiltrates into the concentration of one second polysilicon layer between 1E15
To 1E18atom/cm3In the range of so that the barrier semiconductor layer by the implant permeate in the semiconductor device this second
The permeability of polysilicon layer is minimized.
21. the method according to claim 20 to manufacture semiconductor device, it is characterised in that the wherein first size
The crystal grain of scope is less than the crystal grain of second size range.
22. the method according to claim 20 to manufacture semiconductor device, it is characterised in that the wherein first size
Scope is less than 5 nanometers, and second size range is 10 to 20 nanometers.
23. the method according to claim 20 to manufacture semiconductor device, it is characterised in that wherein the barrier is partly led
The interface of body layer and first polysilicon layer is more the implant infiltration of second polysilicon layer to be minimized.
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| CN1081832C (en) * | 1995-02-27 | 2002-03-27 | 现代电子产业株式会社 | Method for fabricating metal oxide semiconductor field |
| US5652166A (en) * | 1996-01-11 | 1997-07-29 | United Microelectronics Corporation | Process for fabricating dual-gate CMOS having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition |
| JPH1032313A (en) * | 1996-07-17 | 1998-02-03 | Toshiba Corp | Semiconductor device and its manufacture |
| US6380055B2 (en) * | 1998-10-22 | 2002-04-30 | Advanced Micro Devices, Inc. | Dopant diffusion-retarding barrier region formed within polysilicon gate layer |
| US6686637B1 (en) * | 2002-11-21 | 2004-02-03 | International Business Machines Corporation | Gate structure with independently tailored vertical doping profile |
| KR101675459B1 (en) * | 2010-07-02 | 2016-11-11 | 삼성전자 주식회사 | electrode structure and fabrication method thereof, and semiconductor device using the electrode structure |
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