CN103972225B - Has effects that the transistor arrangement of electrostatic discharge protective - Google Patents
Has effects that the transistor arrangement of electrostatic discharge protective Download PDFInfo
- Publication number
- CN103972225B CN103972225B CN201310043563.4A CN201310043563A CN103972225B CN 103972225 B CN103972225 B CN 103972225B CN 201310043563 A CN201310043563 A CN 201310043563A CN 103972225 B CN103972225 B CN 103972225B
- Authority
- CN
- China
- Prior art keywords
- doped region
- effects
- electrostatic discharge
- transistor arrangement
- discharge protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Have effects that the transistor arrangement of electrostatic discharge protective the invention discloses a kind of, includes a substrate, an impure well, one first doped region, one second doped region and a third doped region.Impure well is set in substrate, and has a first conductive type.First doped region is arranged in the substrate and is doped well encirclement, and has the first conductive type.Second doped region is set in substrate and is doped well encirclement, and has a second conductive type.Third doped region is set in substrate and is doped well encirclement, and has the second conductive type.There is a spacing between first doped region and the second doped region.
Description
Technical field
The present invention relates to a kind of transistor, especially for, be related to a kind of transistor arrangement with electrostatic protection effect.
Background technique
As the size of conductor integrated circuit device persistently reduces, in the complementary metal oxide semiconductor of secondary micron
In the technology of transistor (complementary metal oxide semiconductor, CMOS), shallower junction depth
The thickness of (junction depth), thinner grid oxic horizon (gate oxide), are added the drain electrode (light being lightly doped
Doped drain, LDD), shallow isolating trough (shallow trenchisolation, STI) and self-alignment metal silicide
Techniques such as (self-aligned silicide) have become standard technology.But above-mentioned technique but makes IC products
More easily by the damage of static discharge (electrostatic discharge, ESD), therefore electrostatic must be added in chip
The protection circuit of electric discharge designs to protect long-pending body element circuitry.
Referring to FIG. 1, depicted for the known circuit diagram with protecting component for electrostatic discharge.Under normal circumstances,
Internal circuit 104 can be performed various functions by the signal of input pad 100, if however encounter special circumstances, such as input pad
100 with human contact and generate static discharge current, excessive electric current may then damage internal circuit 104.It is thus known that skill
Art can also be provided with an electrostatic protection element 102, and when static discharge current generates, electrostatic protection element 102 can be appropriate
Unlatching makes ESD electric current by exporting to ground terminal Vss.
However, the problem that existing electrostatic protection element 102 often has starting voltage (triggering voltage) excessively high,
Namely want a degree of electrostatic induced current that could drive, which results in the reaction time of electrostatic protection element 102 is too long, significantly
Reduce the practicality.
Summary of the invention
In order to solve foregoing problems, the present invention is in having effects that the transistor junction of electrostatic discharge protective there is provided a kind of
Structure can have lower starting voltage.
According to one embodiment of present invention, the present invention has effects that the transistor arrangement of electrostatic discharge protective, includes
One substrate, an impure well, one first doped region, one second doped region and a third doped region.Impure well is set in substrate,
And there is a first conductive type.First doped region is arranged in the substrate and is doped well encirclement, and has the first conductive type.Second
Doped region is set in substrate and is doped well encirclement, and has a second conductive type.Third doped region be set in substrate and
It is doped well encirclement, and there is the second conductive type.There is a spacing between first doped region and the second doped region.
The present invention provides one kind can have effects that the transistor arrangement of electrostatic protection, with parasitic diode structure,
Therefore the starting voltage of electrostatic protection can be effectively reduced, to improve the sensitivity of electrostatic protection.
Detailed description of the invention
Fig. 1 is depicted for the known circuit diagram with protecting component for electrostatic discharge.
Fig. 2, Fig. 3 and Fig. 4 are depicted for a kind of crystal with static discahrge protection effect in first embodiment of the invention
The schematic diagram of pipe structure.
The depicted protection electrostatic effect schematic diagram for transistor arrangement of the present invention of Fig. 5.
Fig. 6, Fig. 7 and Fig. 8 are depicted for a kind of crystal with static discahrge protection effect in second embodiment of the invention
The schematic diagram of pipe structure.
Fig. 9 is depicted to be shown for a kind of transistor arrangement with static discahrge protection effect in further embodiment of this invention
It is intended to.
[symbol description]
The 4th doped region of 100 input pad 310
102 electrostatic protection element, 312 grid
104 internal circuit, 314 isolation structure
300 substrate 314a isolation structures
302 impure well, 316 parasitic diode
304 first doped region, 318 high potential source
304a 320 low potential source of the first doped region
306 second doped region, 322 grounded-grid N-type gold oxygen transistor
308 third doped region, 324 bipolar transistor
Specific embodiment
It is hereafter special to enumerate several preferred implementations of the invention to enable those skilled in the art to be further understood that the present invention
Example, and cooperates attached drawing, the constitution content that the present invention will be described in detail and it is to be reached the effect of.
Fig. 2, Fig. 3 and Fig. 4 are please referred to, it is depicted that there is static discahrge protection effect to be a kind of in first embodiment of the invention
Transistor arrangement schematic diagram, wherein Fig. 3 is the schematic diagram in Fig. 2 along AA ' tangent line, and Fig. 4 is electrostatic in Fig. 2 and Fig. 3
The equivalent circuit diagram of the transistor arrangement of electric discharge protection.As shown in Figure 2 and Figure 3, the present invention has static discahrge protection effect
The structure of transistor includes a substrate 300, an impure well 302, one first doped region 304, one second doped region 306,1
Three doped regions 308 and one the 4th doped region 310.Substrate 300 is, for example, silicon base (silicon substrate), epitaxy silicon
(epitaxial silicon substrate), silicon germanium semiconductor substrate (silicon germanium substrate), carbon
SiClx substrate or silicon-coated insulated (silicon-on-insulator, SOI) substrate, but not limited to this.The setting of impure well 302 exists
In substrate 300, and there is a first conductive type, e.g. p-type.Impure well 302 can preferably surround completely the first doped region 304,
Second doped region 306, third doped region 308 and the 4th doped region 310, that is to say, that the doping of the first doped region 304, second
Area 306, third doped region 308 and the 4th doped region 310 preferably will not directly be contacted with substrate 300.
First doped region 304 preferably has the first conductive type, such as p-type；Second doped region 306 preferably has one second to lead
Electric type, such as N-type；Third doped region 308 preferably has the second conductive type, such as N-type；4th doped region 310 preferably has the
One conductivity type, such as p-type.In one embodiment, the first doped region 304 is identical as the dopant concentration of the 4th doped region 310 and dense
Degree is greater than the concentration of impure well 302.In another embodiment, the dopant concentration phase of the second doped region 306 and third doped region 308
Together.
From the point of view of the top view of Fig. 2, the first doped region 304 can be surrounded completely by the second doped region 306, but the first doping
Can have a spacing L between area 304 and the second doped region 306, that is to say, that the first doped region 304 and the second doped region 308 it
Between be that have width be the impure well 302 of L, the first doped region 304 can't contact directly with the second doped region 306.In addition, the
There is above impure well 302 grid 312, e.g. polysilicon or metal between two doped regions 306 and third doped region 308
Gate structure separates the second doped region 306 and third doped region 308.Then there is an isolation in 308 periphery of third doped region
Structure 314 surrounds the first doped region 304, the second doped region 306 and third doped region 308.4th doped region 310 is then
Except isolation structure 314, isolation structure 314 is surrounded.As shown in figure 3, high potential source 318 is electrically connected the second doped region
306, low potential source 320 is electrically connected grid 312, third doped region 308 and the 4th doped region 310.In this way, impure well
302, the second doped region 306, grid 312 and third doped region 308 form " grounded-grid N-type gold oxygen transistor (a gate
Grounded NMOS, ggNMOS) 322 ", wherein the second doped region 306 is as drain electrode (drain), and third doped region 308 is
As source electrode (source), and impure well 302 is then as ontology (body).In one embodiment, these doped regions are for example
It is to insert the structure and 320 electrical connection of high potential source 318 or low potential source of fastening (contact plug) etc. by contacting.It is worth note
Meaning, the first doped region 304 of the invention are (floating) structures of floating, can't be defeated with other external signals
Out/input terminal connection, such as there is no insert to fasten connection with other contacts.In this way, which the first doped region 304, second adulterates
Area 306 and between impure well 302 just will form " parasitic diode (parasiticdiode) 316 " structure.Please together
With reference to the equivalent circuit diagram of Fig. 4, when high potential source 318 generates the very big static discharge current of a magnitude of current, this electric current can be held
Grounded-grid N-type gold oxygen transistor 322 is opened, and the finally inflow low potential of third doped region 308 that arrives via the second doped region 306
Main circuit is destroyed to avoid this static discharge current in source 320, e.g. a ground terminal.One is additionally configured with due to of the invention
For first doped region 304 to form a parasitic diode 316 with the second doped region 306, grid is can be effectively reduced in such configuration
It is grounded the starting voltage (triggering voltage) of N-type gold oxygen transistor 322, to improve the susceptibility of its electrostatic protection.
Referring to FIG. 5, depicted protection electrostatic effect schematic diagram for transistor arrangement of the present invention, wherein horizontal axis is voltage
(unit: volt), and the longitudinal axis is electric current (unit: ampere), the lines expression of black triangle is not provided with the first doping of floating
The structure in area 304, and the lines of open diamonds then indicate the structure of setting the first doped region 304 of floating.It can be understood by Fig. 5
Display has about 8.3 volts of starting voltage of the structure of the first doped region 304 of setting, hence it is evident that ratio is not provided with the first doped region 304
The small many of the starting voltage (about 13.2 volts) of structure, it was demonstrated that have the first doped region of setting 304 available relatively sensitive
Electrostatic protection effect.In an alternative embodiment of the invention, by further adjusting the first doped region 304 and the second doped region 306
Between spacing L size, can adjust starting voltage size, it might even be possible to drop between 1 to 8 volt.
In addition, another feature of the present embodiment is, the first doped region 304, which can be used, is compatible to existing production gold
The process compatible for belonging to oxide semi conductor transistor, without re-forming additional light shield.For example, the first doped region 304
Can be with the conductivity type having the same of the 4th doped region 310, such as p-type, and the dopant concentration of the two is identical, and with along with
Ion implanting processes are formed.If being additionally formed the different doped region of dopant concentration to reach the effect cost of drop low start voltage
It is higher, the present invention can it is fully compatible in technique now without additional light shield, cost of manufacture can be saved.
Fig. 6, Fig. 7 and Fig. 8 are please referred to, it is depicted to have effects that electrostatic protection to be a kind of in another embodiment of the present invention
Transistor arrangement schematic diagram, wherein Fig. 7 is the schematic diagram in Fig. 6 along BB ' tangent line, and Fig. 8 is to have electrostatic in Fig. 6 and Fig. 7
Protect the equivalent circuit diagram of the transistor of effect.The structure of the present embodiment and previous embodiment are substantially similar, the difference is that, it is preceding
Stating embodiment is the electrostatic protection element applied to grounded-grid N-type gold oxygen transistor, and the present embodiment is then applied to bipolar
Property transistor (bipolar transistor, BJT).Specifically, second doped region 306 and third doped region of the present embodiment
There is an isolation structure 314a between 308, make directly contact between the second doped region 306 and third doped region 308.One
In embodiment, isolation structure 314a and isolation structure 314 are formed together with same steps and technique.As illustrated in figs. 7 and 8,
In the present embodiment, the second doped region 306, third doped region 308 and impure well 302 then form bipolar transistor
324, wherein the second doped region 306 is as collector (collector), third doped region 308 is as emitter-base bandgap grading
(emitter), impure well 302 is then as base stage (base).Prevent likewise, this bipolar transistor 324 can be used as electrostatic
Protection circuit, and cooperate the first doped region 304 to float, the starting voltage of bipolar transistor 324 can be reduced.
Referring to FIG. 9, depicted is to have effects that showing for the transistor arrangement of electrostatic protection in further embodiment of this invention
It is intended to.As shown in figure 9, first doped region 304 of the present embodiment may include multiple time the first doped region 304a, each time first
Doped region 304a is separated and is doped well 302 each independently and the second doped region 306 is surrounded, and with the second doped region
There is spacing L between 306.It is connected with each other and presents the first doped region 304 of strip with previous embodiment, time the of the present embodiment
One doped region 304a can also provide good electrostatic protection effect.It is worth noting that, shown in Fig. 9 the first doped region
304a is with grounded-grid N-type gold oxygen transistor 322 for example (such as Fig. 2), and those skilled in the art should will be seen that, this
Time the first doped region 304a in embodiment can also be applied to the structure (as shown in Figure 6) with bipolar transistor 324.
In conclusion the present invention provides one kind there can be the transistor arrangement of electrostatic protection, there is parasitism two
Pole pipe structure, therefore the starting voltage of electrostatic protection can be effectively reduced, to improve the sensitivity of electrostatic protection.And it is understood that
, the first conductive type and the second conductive type above are only to represent different conduction types, and in other embodiments, he
Can be interchanged, such as the first conductive type can be N-type, and the second conductive type can be p-type.
Claims (19)
1. a kind of have effects that the transistor arrangement of electrostatic discharge protective, include:
One substrate；
One impure well is set in the substrate, and wherein the impure well has a first conductive type；
One first doped region is arranged in the substrate and is surrounded by the impure well, and wherein first doped region has first conduction
Type；
One second doped region is set in the substrate and is surrounded by the impure well, and wherein second doped region has one second conduction
Type has a spacing between first doped region and second doped region；And
One third doped region is set in the substrate and is surrounded by the impure well, and wherein the third doped region has second conduction
Type,
Wherein first doped region is to float (floating), and first doped region does not connect electrically with any plug or potential end
It connects.
2. have effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein first doped region and
Second doped region forms a parasitic diode (parasitic diode).
3. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein second doped region is connected
One signal input part.
4. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein the third doped region is low
Current potential.
5. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, also it is arranged comprising a grid at this
In substrate, and it is arranged between second doped region and the third doped region.
6. having effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 5, wherein the grid is low potential.
7. having effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 5, wherein the grid, second doping
Area and the third doped region form a transistor.
8. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, also it is arranged comprising an isolation structure
In the substrate, and it is arranged between second doped region and the third doped region.
9. have effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 8, wherein second doped region, this
Three doped regions and the impure well form bipolar transistor.
10. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, also set comprising one the 4th doped region
It sets in the substrate, and the 4th doped region is separated with the third doped region by an isolation structure.
11. having effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 10, wherein four doped region has
The first conductive type, and four doped region and the first doped region dopant concentration having the same.
12. having effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 10, wherein the 4th doped region is
Low potential.
13. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein first doped region includes
Multiple the first doped regions.
14. having effects that the transistor arrangement of electrostatic discharge protective as claimed in claim 13, wherein the multiple time first
Doped region is respectively dividually surrounded by second doped region.
15. have effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein from the point of view of top view this
One doped region is surrounded by second doped region completely.
16. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein second doped region is direct
And it is surrounded completely by the impure well.
17. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein the third doped region is direct
And it is surrounded completely by the impure well.
18. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein the first conductive type is P
Type conductivity type, and the second conductive type is N-type conductivity type.
19. having effects that the transistor arrangement of electrostatic discharge protective as described in claim 1, wherein the first conductive type is N
Type conductivity type, and the second conductive type is P-type conduction type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310043563.4A CN103972225B (en) | 2013-02-04 | 2013-02-04 | Has effects that the transistor arrangement of electrostatic discharge protective |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310043563.4A CN103972225B (en) | 2013-02-04 | 2013-02-04 | Has effects that the transistor arrangement of electrostatic discharge protective |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103972225A CN103972225A (en) | 2014-08-06 |
| CN103972225B true CN103972225B (en) | 2019-01-08 |
Family
ID=51241547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310043563.4A Active CN103972225B (en) | 2013-02-04 | 2013-02-04 | Has effects that the transistor arrangement of electrostatic discharge protective |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103972225B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437064B (en) * | 2021-07-20 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Voltage protection circuit |
| CN113725212A (en) * | 2021-08-30 | 2021-11-30 | 上海华力微电子有限公司 | Grid grounding NMOS (N-channel metal oxide semiconductor) ESD (electro-static discharge) device and implementation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4893157A (en) * | 1984-08-24 | 1990-01-09 | Hitachi, Ltd. | Semiconductor device |
| US6399990B1 (en) * | 2000-03-21 | 2002-06-04 | International Business Machines Corporation | Isolated well ESD device |
| US20030197246A1 (en) * | 2002-04-22 | 2003-10-23 | Ming-Dou Ker | ESD protection circuit sustaining high ESD stress |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5359614B2 (en) * | 2009-07-01 | 2013-12-04 | セイコーエプソン株式会社 | I / O interface circuit, integrated circuit device, and electronic equipment |
-
2013
- 2013-02-04 CN CN201310043563.4A patent/CN103972225B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4893157A (en) * | 1984-08-24 | 1990-01-09 | Hitachi, Ltd. | Semiconductor device |
| US6399990B1 (en) * | 2000-03-21 | 2002-06-04 | International Business Machines Corporation | Isolated well ESD device |
| US20030197246A1 (en) * | 2002-04-22 | 2003-10-23 | Ming-Dou Ker | ESD protection circuit sustaining high ESD stress |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103972225A (en) | 2014-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7282386B2 (en) | Schottky device and method of forming | |
| US9362420B2 (en) | Transistor structure for electrostatic discharge protection | |
| US7709896B2 (en) | ESD protection device and method | |
| US9018705B2 (en) | ESD transistor | |
| TWI515862B (en) | Esd protection circuit | |
| US20070181919A1 (en) | Novel Isolated LDMOS IC Technology | |
| KR20130085355A (en) | Esd protection circuit | |
| US10038082B2 (en) | Cascoded high voltage junction field effect transistor | |
| US8268697B2 (en) | Silicon-on-insulator devices with buried depletion shield layer | |
| US9640611B2 (en) | HV complementary bipolar transistors with lateral collectors on SOI with resurf regions under buried oxide | |
| TWI525793B (en) | Esd protection circuit | |
| KR20080073313A (en) | Semiconductor device and method for forming the same | |
| US9184257B2 (en) | Semiconductor device and related fabrication methods | |
| US9012955B2 (en) | MOS transistor on SOI protected against overvoltages | |
| CN102569292B (en) | ESD protection device with tunable design windows | |
| US9876006B2 (en) | Semiconductor device for electrostatic discharge protection | |
| CN103972225B (en) | Has effects that the transistor arrangement of electrostatic discharge protective | |
| TW201138053A (en) | Semiconductor device | |
| US20080283967A1 (en) | Semiconductor device | |
| TW201431070A (en) | Transistor structure for electrostatic discharge protection | |
| US9972615B1 (en) | Semiconductor device for electrostatic discharge protection | |
| JPH11289050A (en) | Semiconductor device | |
| CN111403379B (en) | Electrostatic discharge protection structure based on SOI technology | |
| CN102569382B (en) | Metallic-oxide semiconductor element and forming method thereof | |
| CN106206565B (en) | Diode and diode string circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |