CN103969892A - Array substrate, preparation method of array substrate and display panel - Google Patents
Array substrate, preparation method of array substrate and display panel Download PDFInfo
- Publication number
- CN103969892A CN103969892A CN201410169256.5A CN201410169256A CN103969892A CN 103969892 A CN103969892 A CN 103969892A CN 201410169256 A CN201410169256 A CN 201410169256A CN 103969892 A CN103969892 A CN 103969892A
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- chock insulator
- insulator matter
- bolster
- array base
- base palte
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Abstract
The invention discloses an array substrate, a preparation method of the array substrate and a display panel. The array substrate comprises a plurality of spacer pads for supporting spacers, wherein the supporting end of each spacer pad is provided with at least one concave portion. The array substrate is applied to the display panel, the array substrate is connected with a color film substrate, and the spacer pads correspond to the spacers in a one-to-one mode and are used for supporting the spacers; the supporting end of each spacer pad arranged on the array substrate is provided with one or more concave portions, and the size of the supporting end of each spacer pad can be increased, namely the spacers arranged on the color film substrate can move in a larger range on the spacer pads but the contact area of each spacer and the corresponding spacer pad cannot be increased; meanwhile, by means of the arrangement of the concave portions, friction force between the spacers and the spacer pads can be increased, the spacers can be prevented from deviating when the display panel bears external pressure, and the light leaking phenomenon of the display panel is reduced.
Description
Technical field
The present invention relates to display technology field, particularly the preparation method of a kind of array base palte, array base palte and display panel.
Background technology
Existing display panel mainly consists of polaroid, array base palte, color membrane substrates, liquid crystal layer etc.The systematicness of liquid crystal layer is arranged, and can realize colored demonstration.The penetrance that the thickness of liquid crystal layer drops into after liquid crystal panel light has impact, there will be and show inequality when penetrance is inconsistent, therefore for realizing the homogeneous of display panel, shows, guarantees that uniform thickness of liquid crystal layer (box is thick) is extremely important.
In the manufacture of display panels, as shown in Figure 1, Fig. 1 is the structural representation of display panel under prior art, conventionally adopts chock insulator matter 02 to be set on color membrane substrates 01 and chock insulator matter bolster 04 is set on array base palte 03 and guarantees that the box of homogeneous is thick.Chock insulator matter is divided into two large classes according to its shape: spherical chock insulator matter (Ball Space is called for short BS) and cylindrical spacer (Post Spacer is called for short PS).The shape of chock insulator matter bolster can be circle, rectangle, rhombus, ellipse etc.
Display panel is when low temperature, and because liquid crystal shrinks, if chock insulator matter can not synchronous, in the situation that guaranteeing thickness of liquid crystal box inconvenience, liquid crystal can not be full of whole liquid crystal cell, at this moment just there will be bubbles of vacuum that is low-temperature bubbles; Display panel is when high temperature, because liquid crystal expands, cause whole thickness of liquid crystal box to raise, if now chock insulator matter elasticity is inadequate, easily cause the inner liquid crystal of display panel to be piled up to the bottom of whole display panel, there is gravity Mura (problem is inhomogeneous, and when gravity Mura refers to high temperature, liquid crystal is to Panel flows under Action of Gravity Field, and LC skewness causes the picture disply inhomogeneous).In technological process, the permission amount of liquid crystal range of control of low-temperature bubbles and Gravity Problem does not occur, be called liquid crystal Margin (gauge).
The phenomenon that occurs low-temperature bubbles and gravity Mura for solving display panel, the general scope that improves liquid crystal Margin by reducing the contact area of chock insulator matter and chock insulator matter bolster in prior art.Conventional method is to reduce the area of chock insulator matter and chock insulator matter bolster contact jaw.But the words that the area of chock insulator matter and chock insulator matter bolster contact jaw is too small, there will be again new problem, as shown in Figure 2, Fig. 2 is the structural representation of display panel of the prior art while coming in contact problem, when panel surface is subject to ambient pressure F, can there is certain skew by relative array base palte 03 in color membrane substrates 01, when side-play amount surpasses certain distance, when chock insulator matter 02 skew arranging on color membrane substrates 01 surpasses the bearing edge of the chock insulator matter bolster 04 arranging on array base palte 03, after external force F disappears, due to poor the stopping of array base palte 03 wire segment, chock insulator matter can not or can not return to original position in time, will cause the generation of display panel light leakage phenomena, in technique, this bad phenomenon is called as pats picture abnormal (Touch Mura).
Summary of the invention
The invention provides preparation method and the display panel of a kind of array base palte, array base palte, guaranteeing under the prerequisite of liquid crystal Margin, increase the friction force between chock insulator matter bolster and chock insulator matter, reduced the generation of the display panel light leakage phenomena causing due to chock insulator matter skew.
For achieving the above object, the invention provides following technical scheme:
The invention provides a kind of array base palte, comprising: for supporting the chock insulator matter bolster of chock insulator matter, the support end of described chock insulator matter bolster is provided with at least one depressed part.
Array base palte provided by the invention is applied in display panel, array base palte is connected box with color membrane substrates, chock insulator matter bolster and chock insulator matter are corresponding and for supporting chock insulator matter one by one, one or more depressed parts that support end by the chock insulator matter bolster that arranges on array base palte is provided with, can increase the size of the support end of chock insulator matter bolster, be on color membrane substrates, arrange chock insulator matter on chock insulator matter bolster movably scope become large, but can not increase the contact area of chock insulator matter and chock insulator matter bolster, guaranteed liquid crystal Margin; Can increase the friction force between chock insulator matter and chock insulator matter bolster by the depressed part arranging again, while preventing that display panel is subject to ambient pressure, chock insulator matter skew surpasses the bearing edge of chock insulator matter bolster, reduces the generation of display panel light leakage phenomena simultaneously.
So array base palte provided by the invention, guaranteeing, under the prerequisite of liquid crystal Margin, to have increased the friction force between chock insulator matter bolster and chock insulator matter, has reduced the generation of the display panel light leakage phenomena causing due to chock insulator matter skew.
In some optional embodiments, described depressed part is bar-shaped trough.
In some optional embodiments, described depressed part is fold-line-shaped groove.
In some optional embodiments, the support end of described chock insulator matter bolster is provided with a plurality of described depressed parts, and a plurality of described depressed part is groove and/or hole.
In some optional embodiments, the support end of described chock insulator matter bolster is provided with a plurality of described depressed parts, and the xsect of the figure of a plurality of described depressed part formation is annular.
In some optional embodiments, described chock insulator matter bolster and described array base palte are integral type structure.
In some optional embodiments, described chock insulator matter bolster comprises: metal level is leaked in semiconductor layer and source.Visible chock insulator matter bolster provided by the invention does not need to increase new material in design process.
In some optional embodiments, the xsect of the support end of a plurality of described chock insulator matter bolsters is circle and/or rectangle and/or prismatic and/or ellipse.
The present invention also provides a kind of preparation method of array base palte, comprising:
To forming semiconductor layer and source, leak the base plate coating photoresist of metal level, and carry out etching for the first time, form chock insulator matter bolster;
Described chock insulator matter bolster is carried out to etching for the second time, form the depressed part on the support end of described chock insulator matter bolster.
The preparation method of array base palte provided by the invention, when forming semiconductor layer and source leakage metal level, form in the lump the chock insulator matter bolster that is provided with at least one groove, in preparation process, do not need to buy separately new mask plate, and do not need to increase new material yet, can not affect the display effect of display panel simultaneously yet.
The present invention also provides a kind of display panel, comprises color membrane substrates, also comprises the array base palte described in above-mentioned any one.
Accompanying drawing explanation
Fig. 1 is the structural representation of display panel under prior art;
Fig. 2 is the structural representation of display panel of the prior art while coming in contact problem;
The array base-plate structure schematic diagram that Fig. 3 provides for the embodiment of the present invention;
The display panel structure schematic diagram that Fig. 4 provides for the embodiment of the present invention;
The first structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 5 provides for the embodiment of the present invention;
The second structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 6 provides for the embodiment of the present invention;
The third structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 7 provides for the embodiment of the present invention;
Structural representation in the array base palte preparation process that Fig. 8 a～8i provides for the embodiment of the present invention.
Reference numeral:
01-color membrane substrates 02-chock insulator matter
03-array base palte 04-chock insulator matter bolster
1-array base palte 2-chock insulator matter bolster
21-depressed part 3-color membrane substrates
4-chock insulator matter 5-substrate
6-grid layer 7-protective seam
Metal level is leaked in 8-semiconductor layer 9-source
10-photoresist
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
The array base-plate structure schematic diagram that Fig. 3 provides for the embodiment of the present invention, as shown in Figure 3, the array base palte that the embodiment of the present invention provides, comprising: for supporting the chock insulator matter bolster 2 of chock insulator matter, the support end of chock insulator matter bolster 2 is provided with at least one depressed part 21.
The array base palte that the embodiment of the present invention provides is applied in display panel, as shown in Figure 4, the display panel structure schematic diagram that Fig. 4 provides for the embodiment of the present invention, 3 pairs of boxes of array base palte 1 and color membrane substrates are connected, chock insulator matter bolster 2 and chock insulator matter 4 are corresponding and for supporting chock insulator matter 4 one by one, one or more depressed parts 21 that support end by the chock insulator matter bolster 2 that arranges on array base palte 1 is provided with, can increase the support end size of chock insulator matter bolster 2, be that movably scope change is large on chock insulator matter bolster 2 for chock insulator matter 4, but can not increase the contact area of chock insulator matter 4 and chock insulator matter bolster 2, guaranteed liquid crystal Margin, the friction force that simultaneously can increase between chock insulator matter 4 and chock insulator matter bolster 2 by the depressed part 21 arranging again, while preventing that display panel is subject to ambient pressure, chock insulator matter 4 skews surpass the edge of chock insulator matter bolster 2, reduce the generation of display panel light leakage phenomena.
So the array base palte that the embodiment of the present invention provides, guaranteeing, under the prerequisite of liquid crystal Margin, to have increased the friction force between chock insulator matter bolster and chock insulator matter, has reduced the generation of the display panel light leakage phenomena causing due to chock insulator matter skew.
Optionally, as shown in Figure 5, the first structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 5 provides for the embodiment of the present invention, depressed part 21 (non-shaded portion in figure) is bar-shaped trough.A plurality of bar-shaped troughs can spaced set, also can be with non-equidistance setting.
Optionally, as shown in Figure 6, the second structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 6 provides for the embodiment of the present invention, depressed part 21 (non-shaded portion in figure) is fold-line-shaped groove.
Optionally, the support end of chock insulator matter bolster 2 is provided with a plurality of depressed parts 21, and a plurality of depressed part 21 is groove and/or hole.Being that depressed part 21 can be all groove, can be also all hole, or in a plurality of depressed part 21, existing groove be porose again.
Optionally, as shown in Figure 7, the third structural representation of the xsect of the support end of the chock insulator matter bolster in the array base palte that Fig. 7 provides for the embodiment of the present invention, the support end of chock insulator matter bolster 2 is provided with a plurality of depressed parts 21 (non-shaded portion in figure), and the xsect of the figure of a plurality of depressed part 21 (non-shaded portion in figure) formation is annular.Certainly, a plurality of annular can spaced set also can non-equidistance setting.
Preferably, chock insulator matter bolster 2 is integral type structure with array base palte 1.Simplified the preparation technology of chock insulator matter bolster.
In a kind of concrete embodiment, chock insulator matter bolster 2 comprises: metal level is leaked in semiconductor layer and source.Visible chock insulator matter bolster provided by the invention does not need to increase new material in design process.
Optionally, the xsect of the support end of a plurality of chock insulator matter bolsters 2 is circular and/or rectangle and/or prismatic and/or ellipse.The shape that is a plurality of chock insulator matter bolsters 2 can be identical, can be also the combination in any of above-mentioned several shapes.For example: in a plurality of chock insulator matter bolsters 2, can be circle, can be partly also circular, and part is rectangle etc., just repeats no longer one by one here.
Embodiment bis-
The embodiment of the present invention provides a kind of preparation method of array base palte, comprising:
To forming semiconductor layer and source, leak the base plate coating photoresist of metal level, and carry out etching for the first time, form chock insulator matter bolster;
Chock insulator matter bolster is carried out to etching for the second time, the depressed part on the support end of formation chock insulator matter bolster.
The preparation method of the array base palte that the embodiment of the present invention provides, when forming semiconductor layer and source leakage metal level, form in the lump the chock insulator matter bolster that is provided with at least one groove, in preparation process, do not need to buy separately new mask plate, and do not need to increase new material yet, can not affect the display effect of display panel simultaneously yet.
As shown in Fig. 8 a～Fig. 8 i, the structural representation in the array base palte preparation process that Fig. 8 a～8i provides for the embodiment of the present invention, the array base palte that the embodiment of the present invention provides is when making:
The protective seam 7 that forms grid layer 6 and grid layer 6 on substrate 5, the structure of formation is as shown in Figure 8 a;
Depositing semiconductor layers 8 on the substrate 5 that forms grid layer 6 and protective seam 7, the structure of formation is as shown in Figure 8 b;
On the substrate 5 that forms grid layer 6, protective seam 7 and semiconductor layer 8, sedimentary origin leaks metal level 9, and the structure of formation as shown in Figure 8 c;
Be coated with photoresist 10 forming to delete on the substrate 5 that utmost point layer 6, protective seam 7, semiconductor layer 8 and source leaks metal level 9, the structure of formation is as shown in Fig. 8 d;
Photoresist 10 is exposed and development treatment, and the structure of formation is as shown in Fig. 8 e;
Adopt etching (wet etching and dry quarter) technology for the first time, carve useless semiconductor layer 8 and source and leak metal level 9, the structure of formation is as shown in Fig. 8 f;
Photoresist 10 is carried out to ashing processing, form chock insulator matter bolster graph of a correspondence, and retain corresponding photoresist 10, the structure of formation is as shown in Fig. 8 g;
Adopt etching (wet etching and dry quarter) technology for the second time, carve useless semiconductor layer 8 and source and leak metal level 9, form the depressed part structure on chock insulator matter bolster, the structure of formation is as shown in Fig. 8 h;
Remaining photoresist 10 is peeled off, formed final chock insulator matter pillow structure, the structure of formation is as shown in Fig. 8 i.
From above-mentioned each step structure of preparing array base palte, can find out, in the method that the embodiment of the present invention provides, the chock insulator matter on array base palte is to form in the lump in preparing the process of array base palte, does not need to buy separately mask plate, and not needing increases new material, and preparation technology is simple.
Embodiment tri-
The embodiment of the present invention provides a kind of display panel, as shown in Figure 4, comprises color membrane substrates, also comprises the array base palte described in any one in above-described embodiment one.
Advantage based on above-mentioned array base palte, the display panel that the embodiment of the present invention provides has good display effect.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the embodiment of the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte, is characterized in that, comprising: for supporting the chock insulator matter bolster of chock insulator matter, the support end of described chock insulator matter bolster is provided with at least one depressed part.
2. array base palte according to claim 1, is characterized in that, described depressed part is bar-shaped trough.
3. array base palte according to claim 1, is characterized in that, described depressed part is fold-line-shaped groove.
4. array base palte according to claim 1, is characterized in that, the support end of described chock insulator matter bolster is provided with a plurality of described depressed parts, and a plurality of described depressed part is groove and/or hole.
5. array base palte according to claim 1, is characterized in that, the support end of described chock insulator matter bolster is provided with a plurality of described depressed parts, and the xsect of the figure of a plurality of described depressed part formation is annular.
6. array base palte according to claim 1, is characterized in that, described chock insulator matter bolster and described array base palte are integral type structure.
7. array base palte according to claim 6, is characterized in that, described chock insulator matter bolster comprises: metal level is leaked in semiconductor layer and source.
8. according to the array base palte described in claim 1～7 any one, it is characterized in that, the xsect of the support end of a plurality of described chock insulator matter bolsters is circle and/or rectangle and/or prismatic and/or ellipse.
9. a preparation method for array base palte, is characterized in that, comprising:
To forming semiconductor layer and source, leak the base plate coating photoresist of metal level, and carry out etching for the first time, form chock insulator matter bolster;
Described chock insulator matter bolster is carried out to etching for the second time, form the depressed part on the support end of described chock insulator matter bolster.
10. a display panel, is characterized in that, comprises color membrane substrates, also comprises the array base palte as described in claim 1～8 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410169256.5A CN103969892A (en) | 2014-04-24 | 2014-04-24 | Array substrate, preparation method of array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410169256.5A CN103969892A (en) | 2014-04-24 | 2014-04-24 | Array substrate, preparation method of array substrate and display panel |
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| CN103969892A true CN103969892A (en) | 2014-08-06 |
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| CN201410169256.5A Pending CN103969892A (en) | 2014-04-24 | 2014-04-24 | Array substrate, preparation method of array substrate and display panel |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104460118A (en) * | 2014-08-22 | 2015-03-25 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
| CN104656317A (en) * | 2015-03-06 | 2015-05-27 | 京东方科技集团股份有限公司 | Display device, array substrate and preparation method thereof |
| CN105093706A (en) * | 2015-08-13 | 2015-11-25 | 京东方科技集团股份有限公司 | Spacer, masking plate, display panel and display device |
| CN106502005A (en) * | 2017-01-03 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of display floater and preparation method thereof and display device |
| CN111308797A (en) * | 2020-03-31 | 2020-06-19 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2020124905A1 (en) * | 2018-12-19 | 2020-06-25 | 武汉华星光电技术有限公司 | Support column and display panel |
| US11152453B2 (en) | 2019-12-31 | 2021-10-19 | Xiamen Tianma Micro-Electronics Co., Ltd. | Touch display panel and display device |
| WO2022222192A1 (en) * | 2021-04-22 | 2022-10-27 | 武汉华星光电技术有限公司 | Liquid crystal display panel and display device |
| WO2023184240A1 (en) * | 2022-03-30 | 2023-10-05 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| CN104460118A (en) * | 2014-08-22 | 2015-03-25 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display device |
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| US11502159B2 (en) | 2019-12-31 | 2022-11-15 | Xiamen Tianma Micro-Electronics Co., Ltd. | Touch display panel and display device |
| CN111308797A (en) * | 2020-03-31 | 2020-06-19 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2022222192A1 (en) * | 2021-04-22 | 2022-10-27 | 武汉华星光电技术有限公司 | Liquid crystal display panel and display device |
| WO2023184240A1 (en) * | 2022-03-30 | 2023-10-05 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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