CN103969494A - High-precision current detecting circuit and current-limiting device applying same - Google Patents
High-precision current detecting circuit and current-limiting device applying same Download PDFInfo
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- CN103969494A CN103969494A CN201410182909.3A CN201410182909A CN103969494A CN 103969494 A CN103969494 A CN 103969494A CN 201410182909 A CN201410182909 A CN 201410182909A CN 103969494 A CN103969494 A CN 103969494A
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Abstract
The invention discloses a high-precision current detecting circuit and a current-limiting device applying the same. The high-precision current detecting circuit comprises a device to be detected, an amplifier and a load, the precision can be effectively improved, and a response speed can be greatly improved. A power amplifier current-limiting device and a switching power current-limiting device can effectively achieve an overcurrent protecting function. The structure is simple, element cost can be effectively saved, the implement mode is simple, and a designer can use the high-precision current detecting circuit and the current-limiting device flexibly and conveniently. The high-precision current detecting circuit and the current-limiting device applying the same can be widely applied to current detecting products.
Description
Technical field
The present invention relates to electronic circuit field, relate in particular to a kind of high precision electro current detection circuit and apply the current-limiting apparatus of this circuit.
Background technology
Adopt current detection circuit to monitor in real time the working current of power-supply management system, electric machine control system, high power device or equipment; both can find in time the over current fault that system causes because of the reason such as short circuit, overload; and make corresponding protection and move; can also be undertaken System Implementation dynamic management by the running status of real-time monitoring system, be conducive to improve the reliability of system and extend its serviceable life.
Now, realize current detecting and had a variety of implementations by detecting the resistance load current of sampling, be broadly divided into two large classes: the voltage that one, detects the foundation of resistance two ends directly accesses voltage comparator and predetermined threshold value compares; Two, first use operational amplifier to amplify detecting ohmically voltage, then access voltage comparator and compare.
Be illustrated in figure 1 the schematic diagram of last class implementation: this system voltage VCC can directly be provided by dc-battery, also can be provided by other voltage sources.Its principle is: current reference source from system voltage Absorption Current, and is set up reference voltage V ref=Iref*Rref at resistance two ends by resistance, for comparer provides threshold voltage.Meanwhile, load from system voltage Absorption Current, is set up voltage Vsense=Iload*Rsense at resistance two ends by resistance, and is input to the in-phase input end of comparer.When load current hour, because voltage Vsense is less than threshold voltage Vref, comparer output high level (instruction load current is normal); In the time that load current Iload is greater than Vref/Rsense, because voltage Vsense is greater than threshold voltage Vref, comparer output low level (instruction load current is excessive, i.e. overcurrent).Because resistance can cause thermal losses, thereby reduce the efficiency of system, therefore resistance will select as far as possible littlely (general selection principle is: the value of Iload_max*Rsense is at 20mV to about 100mV, and wherein Iload_max allows the maximum load current passed through).Due to Iload_max*Rsense=Iref*Rref, therefore the value of Vsense also arrives 100mV left and right at 20mV.Brought difficulty with regard to the circuit design of giving comparer and reference source like this, this is because the precision of threshold voltage and the precision of comparer have determined the accuracy of detection of this current detection circuit jointly.Systematic error and stochastic error by introducings such as technique, temperature, supply voltages will make current detection circuit be difficult to accomplish high precision under certain cost constraint.
Be illustrated in figure 2 the schematic diagram of Equations of The Second Kind implementation, this implementation is compared front a kind of implementation, detect voltage first process amplification before delivering to comparer, detecting the voltage Iload*Rsense setting up on resistance first amplifies through the in-phase amplifier being made up of resistance and operational amplifier, thereby the difficulty of a kind of conceptual design precision voltage reference and precision comparator before having solved, but also introduce another shortcoming simultaneously.Because the Bandwidth-Constrained of operational amplifier, the current detection circuit response speed of this scheme is slower.
Chinese invention patent CN103412180A is the slow problem of a kind of implementation response speed after solving, a kind of over-current detection current circuit has been proposed, improve the response speed that detects over current fault, but it has the following disadvantages: only have over-current detection function, can not be used for current detecting, and its precision is lower, and can not carry out in time Current limited Control.
Summary of the invention
In order to solve the problems of the technologies described above, to the object of this invention is to provide one and can there is high precision, and can promote a kind of high precision electro current detection circuit of response speed and apply the current-limiting apparatus of this circuit.
First technical scheme of the present invention is:
A kind of high precision electro current detection circuit, comprise device under test, amplifier and load, described amplifier comprises the first resistance, the second resistance, the 3rd resistance, the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the first bias current sources, the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with ground by load, the in-phase input end access supply voltage of described amplifier, the inverting input of described amplifier is connected with the source electrode of a PMOS pipe by the first resistance, the grid of a described PMOS pipe is connected with the grid of the 2nd PMOS pipe and the drain electrode of the 2nd PMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 2nd PMOS pipe by the second resistance, the source electrode of described the 2nd PMOS pipe is connected with the source electrode of the 3rd PMOS pipe, the drain electrode of a described PMOS pipe is connected with the drain electrode of the 2nd NMOS pipe and the grid of the 3rd PMOS pipe respectively, the drain electrode of described the 3rd PMOS pipe is connected with ground by the 3rd resistance, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of the 3rd NMOS pipe, the output terminal of described the first bias current sources respectively with the drain electrode of a NMOS pipe, the grid of the one NMOS pipe, the grid of the 2nd NMOS pipe is connected with the grid of the 3rd NMOS pipe, the source electrode of a described NMOS pipe, the source electrode of the source electrode of the 2nd NMOS pipe and the 3rd NMOS pipe is all connected with ground, the drain electrode of described the 3rd PMOS pipe is connected to the output terminal of amplifier.
Second technical scheme of the present invention is:
A kind of high precision electro current detection circuit, comprise device under test, amplifier and load, described amplifier comprises the 4th resistance, the 5th resistance, the 6th resistance, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the second bias current sources, the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with supply voltage by load, the in-phase input end of described amplifier is connected with ground, the inverting input of described amplifier is connected with the source electrode of the 4th NMOS pipe by the 4th resistance, the grid of described the 4th NMOS pipe is connected with the grid of the 5th NMOS pipe and the drain electrode of the 5th NMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 5th NMOS pipe by the 5th resistance, the source electrode of described the 5th NMOS pipe is connected with the source electrode of the 6th NMOS pipe, the drain electrode of described the 4th NMOS pipe is connected with the drain electrode of the 5th PMOS pipe and the grid of the 6th NMOS pipe respectively, the drain electrode of described the 6th NMOS pipe is connected with supply voltage by the 6th resistance, the drain electrode of described the 5th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the input end of described the second bias current sources respectively with the drain electrode of the 4th PMOS pipe, the grid of the 4th PMOS pipe, the grid of the 5th PMOS pipe is connected with the grid of the 6th PMOS pipe, the source electrode of described the 4th PMOS, the source electrode of the source electrode of the 5th PMOS pipe and the 6th PMOS pipe is all connected with supply voltage, the drain electrode of described the 6th NMOS pipe is connected to the output terminal of amplifier.
The 3rd technical scheme of the present invention is:
A kind of current-limiting apparatus of power amplifier, comprise amplifier, bonding line parallel-connection structure, pcb board dead resistance, radio-frequency choke, power amplifier, biasing circuit, reference voltage source and comparer, the in-phase input end access supply voltage of described amplifier, the in-phase input end of described amplifier is connected with pcb board dead resistance and then with the inverting input of amplifier by bonding line parallel-connection structure successively, the inverting input of described amplifier is connected with the power end of power amplifier by radio-frequency choke, the output terminal of described amplifier is connected to the in-phase input end of comparer, the output terminal of described reference voltage source is connected to the inverting input of comparer, the output terminal of described comparer is connected with the first input end of power amplifier by biasing circuit, the second input end access radio-frequency input signals of described power amplifier.
Further, described amplifier comprises the first resistance, the second resistance, the 3rd resistance, the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the first bias current sources, the inverting input of described amplifier is connected with the source electrode of a PMOS pipe by the first resistance, the grid of a described PMOS pipe is connected with the grid of the 2nd PMOS pipe and the drain electrode of the 2nd PMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 2nd PMOS pipe by the second resistance, the source electrode of described the 2nd PMOS pipe is connected with the source electrode of the 3rd PMOS pipe, the drain electrode of a described PMOS pipe is connected with the drain electrode of the 2nd NMOS pipe and the grid of the 3rd PMOS pipe respectively, the drain electrode of described the 3rd PMOS pipe is connected with ground by the 3rd resistance, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of the 3rd NMOS pipe, the output terminal of described the first bias current sources respectively with the drain electrode of a NMOS pipe, the grid of the one NMOS pipe, the grid of the 2nd NMOS pipe is connected with the grid of the 3rd NMOS pipe, the source electrode of a described NMOS pipe, the source electrode of the source electrode of the 2nd NMOS pipe and the 3rd NMOS pipe is all connected with ground, the drain electrode of described the 3rd PMOS pipe is connected to the output terminal of amplifier.
Further, described amplifier comprises the 4th resistance, the 5th resistance, the 6th resistance, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the second bias current sources, the inverting input of described amplifier is connected with the source electrode of the 4th NMOS pipe by the 4th resistance, the grid of described the 4th NMOS pipe is connected with the grid of the 5th NMOS pipe and the drain electrode of the 5th NMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 5th NMOS pipe by the 5th resistance, the source electrode of described the 5th NMOS pipe is connected with the source electrode of the 6th NMOS pipe, the drain electrode of described the 4th NMOS pipe is connected with the drain electrode of the 5th PMOS pipe and the grid of the 6th NMOS pipe respectively, the drain electrode of described the 6th NMOS pipe is connected with supply voltage by the 6th resistance, the drain electrode of described the 5th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the input end of described the second bias current sources respectively with the drain electrode of the 4th PMOS pipe, the grid of the 4th PMOS pipe, the grid of the 5th PMOS pipe is connected with the grid of the 6th PMOS pipe, the source electrode of described the 4th PMOS, the source electrode of the source electrode of the 5th PMOS pipe and the 6th PMOS pipe is all connected with supply voltage, the drain electrode of described the 6th NMOS pipe is connected to the output terminal of amplifier.
Further, described reference voltage source includes temperature-compensation circuit.
The 4th technical scheme of the present invention is:
A kind of current-limiting apparatus of Switching Power Supply, comprise amplifier, reference voltage source, comparer, logic sum gate, rest-set flip-flop, clock signal generator, PMOS switching tube, nmos switch pipe, inductance, electric capacity and device load, the in-phase input end access supply voltage of described amplifier, the in-phase input end of described amplifier is connected with the source electrode of PMOS switching tube, the inverting input of described amplifier is connected with the drain electrode of PMOS switching tube and the drain electrode of nmos switch pipe respectively, described electric capacity is attempted by between the drain electrode and source electrode of nmos switch pipe with connecting with inductance after device load parallel connection again, the output terminal of described amplifier is connected with the in-phase input end of comparer, the output terminal of described reference voltage source is connected with the inverting input of comparer, the output terminal of described comparer is connected with the first input end of logic sum gate, the second input end access pulse-width signal of described logic sum gate, the output terminal of described logic sum gate is connected with the R of rest-set flip-flop end, the output terminal of described clock signal generator is connected with the S of rest-set flip-flop end, described rest-set flip-flop
end is connected with the grid of nmos switch pipe, described rest-set flip-flop
end is connected with the grid of PMOS switching tube.
Further, described amplifier comprises the first resistance, the second resistance, the 3rd resistance, the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the first bias current sources, the inverting input of described amplifier is connected with the source electrode of a PMOS pipe by the first resistance, the grid of a described PMOS pipe is connected with the grid of the 2nd PMOS pipe and the drain electrode of the 2nd PMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 2nd PMOS pipe by the second resistance, the source electrode of described the 2nd PMOS pipe is connected with the source electrode of the 3rd PMOS pipe, the drain electrode of a described PMOS pipe is connected with the drain electrode of the 2nd NMOS pipe and the grid of the 3rd PMOS pipe respectively, the drain electrode of described the 3rd PMOS pipe is connected with ground by the 3rd resistance, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of the 3rd NMOS pipe, the output terminal of described the first bias current sources respectively with the drain electrode of a NMOS pipe, the grid of the one NMOS pipe, the grid of the 2nd NMOS pipe is connected with the grid of the 3rd NMOS pipe, the source electrode of a described NMOS pipe, the source electrode of the source electrode of the 2nd NMOS pipe and the 3rd NMOS pipe is all connected with ground, the drain electrode of described the 3rd PMOS pipe is connected to the output terminal of amplifier.
Further, described amplifier comprises the 4th resistance, the 5th resistance, the 6th resistance, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the second bias current sources, the inverting input of described amplifier is connected with the source electrode of the 4th NMOS pipe by the 4th resistance, the grid of described the 4th NMOS pipe is connected with the grid of the 5th NMOS pipe and the drain electrode of the 5th NMOS pipe respectively, the in-phase input end of described amplifier is connected with the source electrode of the 5th NMOS pipe by the 5th resistance, the source electrode of described the 5th NMOS pipe is connected with the source electrode of the 6th NMOS pipe, the drain electrode of described the 4th NMOS pipe is connected with the drain electrode of the 5th PMOS pipe and the grid of the 6th NMOS pipe respectively, the drain electrode of described the 6th NMOS pipe is connected with supply voltage by the 6th resistance, the drain electrode of described the 5th NMOS pipe is connected with the drain electrode of the 6th PMOS pipe, the input end of described the second bias current sources respectively with the drain electrode of the 4th PMOS pipe, the grid of the 4th PMOS pipe, the grid of the 5th PMOS pipe is connected with the grid of the 6th PMOS pipe, the source electrode of described the 4th PMOS, the source electrode of the source electrode of the 5th PMOS pipe and the 6th PMOS pipe is all connected with supply voltage, the drain electrode of described the 6th NMOS pipe is connected to the output terminal of amplifier.
Further, described reference voltage source includes the compensating circuit for supplementing the PMOS switching tube conducting resistance changing with temperature, operating voltage and process deviation.
The invention has the beneficial effects as follows:
A kind of high precision electro current detection circuit in the present invention's the first and second technical schemes can effectively improve precision and greatly promote response speed, and the present invention is simple in structure, can effectively save element cost, and implementation is simple, facilitates designer's flexible Application.
The current-limiting apparatus of a kind of power amplifier of the present invention can effectively improve precision and greatly promote response speed; realize overcurrent protection function; and; the present invention is by adopting bonding line as detecting resistance; and be aided with the temperature-compensation circuit in reference voltage source; can effectively reduce the temperature of dead resistance and float impact, and the present invention is simple in structure, can effectively save production cost.
The current-limiting apparatus of a kind of Switching Power Supply of the present invention is the amplification to voltage by amplifier; can effectively promote accuracy of detection and greatly promote response speed; overcurrent protection function is provided; and; the present invention compensates the conducting resistance of PMOS switching tube by the compensating circuit in reference voltage source; can effectively reduce the impact that come by temperature, technique isogonic difference band, and the present invention is simple in structure, greatly saves production cost.
Brief description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is the circuit theory diagrams of first kind current detection circuit in prior art of the present invention;
Fig. 2 is the circuit theory diagrams of Equations of The Second Kind current detection circuit in prior art of the present invention;
Fig. 3 is the circuit theory diagrams of a kind of high precision electro current detection circuit of the present invention;
Fig. 4 is another circuit theory diagrams of a kind of high precision electro current detection circuit of the present invention;
Fig. 5 is the principle schematic of the current-limiting apparatus of a kind of power amplifier of the present invention;
Fig. 6 is the principle schematic of the current-limiting apparatus of a kind of Switching Power Supply of the present invention.
Embodiment
With reference to figure 3, a kind of high precision electro current detection circuit of the present invention, comprise device under test, amplifier and load, described amplifier comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the first bias current sources IB1, the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with ground by load, the in-phase input end access supply voltage of described amplifier, the inverting input of described amplifier is connected with the source electrode of a PMOS pipe MP1 by the first resistance R 1, the grid of a described PMOS pipe MP1 is connected with the grid of the 2nd PMOS pipe MP2 and the drain electrode of the 2nd PMOS pipe MP2 respectively, the in-phase input end of described amplifier is connected with the source electrode of the 2nd PMOS pipe MP2 by the second resistance R 2, the source electrode of described the 2nd PMOS pipe MP2 is connected with the source electrode of the 3rd PMOS pipe MP3, the drain electrode of a described PMOS pipe MP1 is connected with the drain electrode of the 2nd NMOS pipe MN2 and the grid of the 3rd PMOS pipe MP3 respectively, the drain electrode of described the 3rd PMOS pipe MP3 is connected with ground by the 3rd resistance R 3, the drain electrode of described the 2nd PMOS pipe MP2 is connected with the drain electrode of the 3rd NMOS pipe MN3, the output terminal of described the first bias current sources IB1 is managed respectively the drain electrode of MN1 with a NMOS, the grid of the one NMOS pipe MN1, the grid of the 2nd NMOS pipe MN2 is connected with the grid of the 3rd NMOS pipe MN3, the source electrode of a described NMOS pipe MN1, the source electrode of the 2nd NMOS pipe MN2 is all connected with ground with the source electrode of the 3rd NMOS pipe MN3, the drain electrode of described the 3rd PMOS pipe MP3 is connected to the output terminal of amplifier.
Wherein, the one NMOS pipe MN1, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 form current mirror, the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 2nd NMOS pipe MN2 and the 3rd NMOS pipe MN3 form voltage comparator, the output of the voltage comparator forming is connected to respectively the grid of a PMOS pipe MP1 and the grid of the 2nd PMOS pipe MP2 forms feedback loop, thereby make the source voltage approximately equal of a PMOS pipe MP1 and the 2nd PMOS pipe MP2.And the 3rd PMOS pipe MP3 Absorption Current inject the 3rd resistance R 3, set up Voltage-output at the 3rd resistance R 3 two ends.
With reference to figure 4, a kind of high precision electro current detection circuit, comprise device under test, amplifier and load, described amplifier comprises the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6 and the second bias current sources IB2, the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with supply voltage by load, the in-phase input end of described amplifier is connected with ground, the inverting input of described amplifier is connected with the source electrode of the 4th NMOS pipe MN4 by the 4th resistance R 4, the grid of described the 4th NMOS pipe MN4 is connected with the grid of the 5th NMOS pipe MN5 and the drain electrode of the 5th NMOS pipe MN5 respectively, the in-phase input end of described amplifier is connected with the source electrode of the 5th NMOS pipe MN5 by the 5th resistance R 5, the source electrode of described the 5th NMOS pipe MN5 is connected with the source electrode of the 6th NMOS pipe MN6, the drain electrode of described the 4th NMOS pipe MN4 is connected with the drain electrode of the 5th PMOS pipe MP5 and the grid of the 6th NMOS pipe MN6 respectively, the drain electrode of described the 6th NMOS pipe MN6 is connected with supply voltage by the 6th resistance R 6, the drain electrode of described the 5th NMOS pipe MN5 is connected with the drain electrode of the 6th PMOS pipe MP6, the input end of described the second bias current sources IB2 is managed respectively the drain electrode of MP4 with the 4th PMOS, the grid of the 4th PMOS pipe MP4, the grid of the 5th PMOS pipe MP5 is connected with the grid of the 6th PMOS pipe MP6, the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe MP5 is all connected with supply voltage with the source electrode of the 6th PMOS pipe MP6, the drain electrode of described the 6th NMOS pipe MN6 is connected to the output terminal of amplifier.
Wherein, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5 and the 6th PMOS pipe MP6 form current mirror, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 5th PMOS pipe MP5 and the 6th PMOS pipe MP6 form voltage comparator, the output of the voltage comparator forming is connected to respectively the grid of the 4th NMOS pipe MN4 and the grid of the 5th NMOS pipe MN5 forms feedback loop, thereby make the source voltage approximately equal of the 4th NMOS pipe MN4 and the 5th NMOS pipe MN5.And the 6th NMOS pipe MN6 Absorption Current inject the 6th resistance R 6, set up Voltage-output at the 6th resistance R 6 two ends.
With reference to figure 5, a kind of current-limiting apparatus of power amplifier, comprise amplifier AMP1, bonding line parallel-connection structure RS, pcb board dead resistance RP, radio-frequency choke RFC, power amplifier PA, biasing circuit BIAS, reference voltage source VF1 and comparator C OM1, the in-phase input end access supply voltage of described amplifier AMP1, the in-phase input end of described amplifier AMP1 is connected with pcb board dead resistance RP and then with the inverting input of amplifier AMP1 by bonding line parallel-connection structure RS successively, the inverting input of described amplifier AMP1 is connected with the power end of power amplifier PA by radio-frequency choke RFC, the output terminal of described amplifier AMP1 is connected to the in-phase input end of comparator C OM1, the output terminal of described reference voltage source VF1 is connected to the inverting input of comparator C OM1, the output terminal of described comparator C OM1 is connected with the first input end of power amplifier PA by biasing circuit BIAS, the second input end access radio-frequency input signals of described power amplifier PA.
Be further used as preferred embodiment, described amplifier AMP1 comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the first bias current sources IB1, the inverting input of described amplifier AMP1 is connected with the source electrode of a PMOS pipe MP1 by the first resistance R 1, the grid of a described PMOS pipe MP1 is connected with the grid of the 2nd PMOS pipe MP2 and the drain electrode of the 2nd PMOS pipe MP2 respectively, the in-phase input end of described amplifier AMP1 is connected with the source electrode of the 2nd PMOS pipe MP2 by the second resistance R 2, the source electrode of described the 2nd PMOS pipe MP2 is connected with the source electrode of the 3rd PMOS pipe MP3, the drain electrode of a described PMOS pipe MP1 is connected with the drain electrode of the 2nd NMOS pipe MN2 and the grid of the 3rd PMOS pipe MP3 respectively, the drain electrode of described the 3rd PMOS pipe MP3 is connected with ground by the 3rd resistance R 3, the drain electrode of described the 2nd PMOS pipe MP2 is connected with the drain electrode of the 3rd NMOS pipe MN3, the output terminal of described the first bias current sources IB1 is managed respectively the drain electrode of MN1 with a NMOS, the grid of the one NMOS pipe MN1, the grid of the 2nd NMOS pipe MN2 is connected with the grid of the 3rd NMOS pipe MN3, the source electrode of a described NMOS pipe MN1, the source electrode of the 2nd NMOS pipe MN2 is all connected with ground with the source electrode of the 3rd NMOS pipe MN3, the drain electrode of described the 3rd PMOS pipe MP3 is connected to the output terminal of amplifier AMP1.
Be further used as preferred embodiment, described amplifier AMP1 comprises the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6 and the second bias current sources IB2, the inverting input of described amplifier AMP1 is connected with the source electrode of the 4th NMOS pipe MN4 by the 4th resistance R 4, the grid of described the 4th NMOS pipe MN4 is connected with the grid of the 5th NMOS pipe MN5 and the drain electrode of the 5th NMOS pipe MN5 respectively, the in-phase input end of described amplifier AMP1 is connected with the source electrode of the 5th NMOS pipe MN5 by the 5th resistance R 5, the source electrode of described the 5th NMOS pipe MN5 is connected with the source electrode of the 6th NMOS pipe MN6, the drain electrode of described the 4th NMOS pipe MN4 is connected with the drain electrode of the 5th PMOS pipe MP5 and the grid of the 6th NMOS pipe MN6 respectively, the drain electrode of described the 6th NMOS pipe MN6 is connected with supply voltage by the 6th resistance R 6, the drain electrode of described the 5th NMOS pipe MN5 is connected with the drain electrode of the 6th PMOS pipe MP6, the input end of described the second bias current sources IB2 is managed respectively the drain electrode of MP4 with the 4th PMOS, the grid of the 4th PMOS pipe MP4, the grid of the 5th PMOS pipe MP5 is connected with the grid of the 6th PMOS pipe MP6, the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe MP5 is all connected with supply voltage with the source electrode of the 6th PMOS pipe MP6, the drain electrode of described the 6th NMOS pipe MN6 is connected to the output terminal of amplifier AMP1.
Be further used as preferred embodiment, described reference voltage source VF1 includes temperature-compensation circuit.
Wherein, reference voltage source VF1 provides predetermined threshold value voltage for comparator C OM1, and the output terminal of comparator C OM1 is connected to biasing circuit BIAS, and for biasing circuit, BIAS provides control signal.Bonding line parallel-connection structure RS in the present invention, for replacing traditional SMT precision resistance, is conducive to reduce element cost.
Because the temperature coefficient of the wire on pcb board and pad material dead resistance is also in 3.3kppm left and right, adopt bonding line as detecting resistance and be aided with compared with the current detection circuit of temperature-compensation circuit and traditional use Low Drift Temperature SMT precision resistance, the temperature that can greatly reduce dead resistance is floated impact.This is because the impact of dead resistance be can not ignore under large load current, and temperature-compensation circuit had both compensated the temperature of bonding line resistance and floats, and the temperature that can also compensate dead resistance is floated.General dead resistance is 3 m Ω～5m Ω, if bonding line resistive arrangement value is 30m Ω, dead resistance can account for 10%～16.7% of total resistance so.
Power amplifier PA uses GaAs technology to manufacture whole circuit and can be encapsulated on the pcb board of multilayer in the mode of SiP.The power amplifier PA here generally comprises multistage, i.e. one or more levels driving stage and a power output stage.Power amplifier PA electric current flows through resistance and the dead resistance of bonding line parallel-connection structure RS, and sets up voltage Vsense1 at the input end of amplifier AMP1, and after amplifying, voltage is the in-phase input end that A*Vsense1 outputs to comparator C OM1.Threshold voltage is provided by reference voltage source VF1, for the intrinsic temperature drift of compensation bonding line parallel-connection structure RS resistance, the threshold voltage of reference voltage source VF1 output can be expressed as Vref1=(k*IPTAT+IBG) * Rref, wherein IPTAT represents the reference current with positive temperature coefficient (PTC), IBG represents the reference current of zero-temperature coefficient, Rref represents to set up the resistance of threshold voltage, and k is coefficient.In the time that voltage A*Vsense1 is greater than Vref1, comparator C OM1 can export the control electric current of non-zero, when receiving this electric current, biasing circuit BIAS can reduce the collector voltage of the driving stage that outputs to power amplifier PA, thereby reduce to output to the RF input power of afterbody, thereby made the collector current clamper of afterbody on the preset value being determined by threshold voltage.
The collector current Iload1 of power amplifier PA afterbody, sets up detection voltage Vsense1 by detecting resistance, is input to amplifier AMP1 and becomes A*Vsense1 after amplifying, then deliver to the in-phase input end of comparator C OM1.Baseline threshold voltage Vref1, floats electric current by built-in resistor Rref with the positive temperature that flows through this resistance and determines, delivers to the inverting input of comparator C OM1.If load current Iload1, in nominal value range, detects voltage A*Vsense1 less than threshold voltage Vref1, the mistake current control electric current of comparator C OM1 output is 0, and the now biasing of power amplifier PA can not be affected.If load current Iload1 is excessive, now detect voltage A*Vsense1 larger than threshold voltage Vref1, the mistake current control electric current of comparator C OM1 output non-zero, will be worked by the control loop of biasing circuit BIAS and power amplifier PA the electric circuit constitute.The mistake current control electric current of non-zero can make biasing circuit BIAS reduce to output to the collector voltage of power amplifier PA driving stage, thereby the collector current of power amplifier PA afterbody is maintained near default current threshold.At this moment detecting voltage A*Vsense1 will equate with threshold voltage Vref1.
With reference to figure 6, a kind of current-limiting apparatus of Switching Power Supply, comprise amplifier AMP2, reference voltage source VF2, comparator C OM2, logic sum gate OR, rest-set flip-flop RST, clock signal generator CLK, PMOS switching tube PM, nmos switch pipe NM, inductance L, capacitor C and device load RL, the in-phase input end access supply voltage of described amplifier AMP2, the in-phase input end of described amplifier AMP2 is connected with the source electrode of PMOS switching tube PM, the inverting input of described amplifier AMP2 is connected with the drain electrode of PMOS switching tube PM and the drain electrode of nmos switch pipe NM respectively, described capacitor C is attempted by between the drain electrode and source electrode of nmos switch pipe NM with connecting with inductance L after device load RL parallel connection again, the output terminal of described amplifier AMP2 is connected with the in-phase input end of comparator C OM2, the output terminal of described reference voltage source VF2 is connected with the inverting input of comparator C OM2, the output terminal of described comparator C OM2 is connected with the first input end of logic sum gate OR, the second input end access pulse-width signal of described logic sum gate OR, the output terminal of described logic sum gate OR is connected with the R end of rest-set flip-flop RST, the output terminal of described clock signal generator CLK is connected with the S end of rest-set flip-flop RST, described rest-set flip-flop RST's
end is connected with the grid of nmos switch pipe NM, described rest-set flip-flop RST's
end is connected with the grid of PMOS switching tube PM.
Be further used as preferred embodiment, described amplifier AMP2 comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the first bias current sources IB1, the inverting input of described amplifier AMP2 is connected with the source electrode of a PMOS pipe MP1 by the first resistance R 1, the grid of a described PMOS pipe MP1 is connected with the grid of the 2nd PMOS pipe MP2 and the drain electrode of the 2nd PMOS pipe MP2 respectively, the in-phase input end of described amplifier AMP2 is connected with the source electrode of the 2nd PMOS pipe MP2 by the second resistance R 2, the source electrode of described the 2nd PMOS pipe MP2 is connected with the source electrode of the 3rd PMOS pipe MP3, the drain electrode of a described PMOS pipe MP1 is connected with the drain electrode of the 2nd NMOS pipe MN2 and the grid of the 3rd PMOS pipe MP3 respectively, the drain electrode of described the 3rd PMOS pipe MP3 is connected with ground by the 3rd resistance R 3, the drain electrode of described the 2nd PMOS pipe MP2 is connected with the drain electrode of the 3rd NMOS pipe MN3, the output terminal of described the first bias current sources IB1 is managed respectively the drain electrode of MN1 with a NMOS, the grid of the one NMOS pipe MN1, the grid of the 2nd NMOS pipe MN2 is connected with the grid of the 3rd NMOS pipe MN3, the source electrode of a described NMOS pipe MN1, the source electrode of the 2nd NMOS pipe MN2 is all connected with ground with the source electrode of the 3rd NMOS pipe MN3, the drain electrode of described the 3rd PMOS pipe MP3 is connected to the output terminal of amplifier AMP2.
Be further used as preferred embodiment, described amplifier AMP2 comprises the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6 and the second bias current sources IB2, the inverting input of described amplifier AMP2 is connected with the source electrode of the 4th NMOS pipe MN4 by the 4th resistance R 4, the grid of described the 4th NMOS pipe MN4 is connected with the grid of the 5th NMOS pipe MN5 and the drain electrode of the 5th NMOS pipe MN5 respectively, the in-phase input end of described amplifier AMP2 is connected with the source electrode of the 5th NMOS pipe MN5 by the 5th resistance R 5, the source electrode of described the 5th NMOS pipe MN5 is connected with the source electrode of the 6th NMOS pipe MN6, the drain electrode of described the 4th NMOS pipe MN4 is connected with the drain electrode of the 5th PMOS pipe MP5 and the grid of the 6th NMOS pipe MN6 respectively, the drain electrode of described the 6th NMOS pipe MN6 is connected with supply voltage by the 6th resistance R 6, the drain electrode of described the 5th NMOS pipe MN5 is connected with the drain electrode of the 6th PMOS pipe MP6, the input end of described the second bias current sources IB2 is managed respectively the drain electrode of MP4 with the 4th PMOS, the grid of the 4th PMOS pipe MP4, the grid of the 5th PMOS pipe MP5 is connected with the grid of the 6th PMOS pipe MP6, the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe MP5 is all connected with supply voltage with the source electrode of the 6th PMOS pipe MP6, the drain electrode of described the 6th NMOS pipe MN6 is connected to the output terminal of amplifier AMP2.
Be further used as preferred embodiment, described reference voltage source VF2 includes the compensating circuit for supplementing the PMOS switching tube PM conducting resistance changing with temperature, operating voltage and process deviation.
In the current-limiting apparatus of a kind of Switching Power Supply of the present invention, amplifier AMP2 is by detecting the source-drain electrode voltage difference of PMOS switching tube PM, be designated as Vsense2, detect the electric current that flows through PMOS switching tube PM, and after amplifier AMP2 amplifies, be designated as A*Vsense2, send into the in-phase input end of comparator C OM2, the predetermined voltage threshold of comparator C OM2 is provided by reference voltage source VF2, is designated as Vref2.After relatively, output logic level Voc is to logic sum gate OR, and control the R end of rest-set flip-flop RST after doing exclusive disjunction with pulse-width signal VPWM, and then control unlatching and the shutoff of PMOS switching tube PM and nmos switch pipe NM, thus regulation output voltage Vout.In the time that pulse-width signal VPWM is low level, if flow through the electric current I load2 of device load RL in nominal value range, the voltage difference Vsense2=Iload2*Ron detecting at the source-drain electrode of PMOS switching tube PM, wherein Ron is the equivalent conducting resistance of PMOS switching tube PM, after amplifier AMP2 amplifies, voltage A*Vsense2 is less than the predetermined threshold value voltage Vref2 of comparator C OM2, now the output Voc of comparator C OM2 is low level, and the unlatching of PMOS switching tube PM and nmos switch pipe NM and shutoff are only subject to the control of pulse-width signal VPWM.
In the time that pulse-width signal VPWM is low level, if load current Iload2 is excessive, the voltage difference Vsense2=Iload2*Ron detecting at the source-drain electrode of PMOS switching tube PM voltage A*Vsense2 after amplifier AMP2 amplifies is greater than the predetermined threshold value voltage Vref2 of comparator C OM2, the output Voc of comparator C OM2 is high level, and the control loop being now made up of amplifier AMP2, comparator C OM2, logic sum gate OR, rest-set flip-flop RST, PMOS switching tube PM will work.Comparator C OM2 output Voc is high level, represents overcurrent, and the R end of rest-set flip-flop RST is set by logic sum gate OR, rest-set flip-flop RST's
end output low level signal, rest-set flip-flop RST's
end output high level signal, and then PMOS switching tube PM shutoff, nmos switch pipe NM are opened, thus reduce the dutycycle of the DC-DC Switching Power Supply of Buck structure, reduce output voltage V out, thereby limited the size of load current.
In the time that pulse-width signal VPWM is high level, now PMOS switching tube PM shutoff, nmos switch pipe NM open, amplifier AMP2 and comparator C OM2 still work, and export wrong current detecting result to logic sum gate OR, but logic sum gate OR can shield this current detecting loop, the now unlatching of PMOS switching tube PM and nmos switch pipe NM and shutoff are still only subject to the control of pulse-width signal VPWM.
The load current when current-limiting apparatus of a kind of Switching Power Supply of the present invention can not only detector switch power supply enters normal operating conditions also provides overcurrent protection function; can also trace into the electric current that flows through PMOS switching tube PM in DC-DC Switching Power Supply start-up course, can coordinate pulse-width signal VPWM and reference voltage source VF2 to realize the soft start of power supply.Because the source-drain electrode voltage difference of PMOS switching tube PM is amplified through amplifier AMP2, therefore voltage detecting precision is promoted greatly.In reference voltage source VF2, introduce compensating circuit the conducting resistance Ron of PMOS switching tube PM is compensated, this current detection circuit can obtain higher current detection accuracy.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and the distortion that these are equal to or replacement are all included in the application's claim limited range.
Claims (10)
1. a high precision electro current detection circuit, it is characterized in that: comprise device under test, amplifier and load, described amplifier comprises the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the one PMOS pipe (MP1), the 2nd PMOS pipe (MP2), the 3rd PMOS pipe (MP3), the one NMOS pipe (MN1), the 2nd NMOS pipe (MN2), the 3rd NMOS pipe (MN3) and the first bias current sources (IB1), the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with ground by load, the in-phase input end access supply voltage of described amplifier, the inverting input of described amplifier is connected with the source electrode that a PMOS manages (MP1) by the first resistance (R1), the grid of a described PMOS pipe (MP1) is connected with the grid of the 2nd PMOS pipe (MP2) and the drain electrode of the 2nd PMOS pipe (MP2) respectively, the in-phase input end of described amplifier is connected with the source electrode that the 2nd PMOS manages (MP2) by the second resistance (R2), the source electrode of described the 2nd PMOS pipe (MP2) is connected with the source electrode that the 3rd PMOS manages (MP3), the drain electrode of a described PMOS pipe (MP1) is connected with the drain electrode of the 2nd NMOS pipe (MN2) and the grid of the 3rd PMOS pipe (MP3) respectively, the drain electrode of described the 3rd PMOS pipe (MP3) is connected with ground by the 3rd resistance (R3), the drain electrode of described the 2nd PMOS pipe (MP2) is connected with the drain electrode that the 3rd NMOS manages (MN3), the output terminal of described the first bias current sources (IB1) is managed respectively the drain electrode of (MN1) with a NMOS, the grid of the one NMOS pipe (MN1), the grid of the 2nd NMOS pipe (MN2) is connected with the grid that the 3rd NMOS manages (MN3), the source electrode of a described NMOS pipe (MN1), the source electrode of the 2nd NMOS pipe (MN2) is all connected with ground with the source electrode that the 3rd NMOS manages (MN3), the drain electrode of described the 3rd PMOS pipe (MP3) is connected to the output terminal of amplifier.
2. a high precision electro current detection circuit, it is characterized in that: comprise device under test, amplifier and load, described amplifier comprises the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5), the 6th NMOS pipe (MN6), the 4th PMOS pipe (MP4), the 5th PMOS pipe (MP5), the 6th PMOS pipe (MP6) and the second bias current sources (IB2), the in-phase input end of described amplifier is connected with the inverting input of amplifier by device under test, the inverting input of described amplifier is connected with supply voltage by load, the in-phase input end of described amplifier is connected with ground, the inverting input of described amplifier is connected with the source electrode that the 4th NMOS manages (MN4) by the 4th resistance (R4), the grid of described the 4th NMOS pipe (MN4) is connected with the grid of the 5th NMOS pipe (MN5) and the drain electrode of the 5th NMOS pipe (MN5) respectively, the in-phase input end of described amplifier is connected with the source electrode that the 5th NMOS manages (MN5) by the 5th resistance (R5), the source electrode of described the 5th NMOS pipe (MN5) is connected with the source electrode that the 6th NMOS manages (MN6), the drain electrode of described the 4th NMOS pipe (MN4) is connected with the drain electrode of the 5th PMOS pipe (MP5) and the grid of the 6th NMOS pipe (MN6) respectively, the drain electrode of described the 6th NMOS pipe (MN6) is connected with supply voltage by the 6th resistance (R6), the drain electrode of described the 5th NMOS pipe (MN5) is connected with the drain electrode that the 6th PMOS manages (MP6), the input end of described the second bias current sources (IB2) is managed respectively the drain electrode of (MP4) with the 4th PMOS, the grid of the 4th PMOS pipe (MP4), the grid of the 5th PMOS pipe (MP5) is connected with the grid that the 6th PMOS manages (MP6), the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe (MP5) is all connected with supply voltage with the source electrode that the 6th PMOS manages (MP6), the drain electrode of described the 6th NMOS pipe (MN6) is connected to the output terminal of amplifier.
3. the current-limiting apparatus of a power amplifier, it is characterized in that: comprise amplifier (AMP1), bonding line parallel-connection structure (RS), pcb board dead resistance (RP), radio-frequency choke (RFC), power amplifier (PA), biasing circuit (BIAS), reference voltage source (VF1) and comparer (COM1), the in-phase input end access supply voltage of described amplifier (AMP1), the in-phase input end of described amplifier (AMP1) is connected with pcb board dead resistance (RP) and then with the inverting input of amplifier (AMP1) by bonding line parallel-connection structure (RS) successively, the inverting input of described amplifier (AMP1) is connected with the power end of power amplifier (PA) by radio-frequency choke (RFC), the output terminal of described amplifier (AMP1) is connected to the in-phase input end of comparer (COM1), the output terminal of described reference voltage source (VF1) is connected to the inverting input of comparer (COM1), the output terminal of described comparer (COM1) is connected with the first input end of power amplifier (PA) by biasing circuit (BIAS), the second input end access radio-frequency input signals of described power amplifier (PA).
4. the current-limiting apparatus of a kind of power amplifier according to claim 3, it is characterized in that: described amplifier (AMP1) comprises the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the one PMOS pipe (MP1), the 2nd PMOS pipe (MP2), the 3rd PMOS pipe (MP3), the one NMOS pipe (MN1), the 2nd NMOS pipe (MN2), the 3rd NMOS pipe (MN3) and the first bias current sources (IB1), the inverting input of described amplifier (AMP1) is connected with the source electrode that a PMOS manages (MP1) by the first resistance (R1), the grid of a described PMOS pipe (MP1) is connected with the grid of the 2nd PMOS pipe (MP2) and the drain electrode of the 2nd PMOS pipe (MP2) respectively, the in-phase input end of described amplifier (AMP1) is connected with the source electrode that the 2nd PMOS manages (MP2) by the second resistance (R2), the source electrode of described the 2nd PMOS pipe (MP2) is connected with the source electrode that the 3rd PMOS manages (MP3), the drain electrode of a described PMOS pipe (MP1) is connected with the drain electrode of the 2nd NMOS pipe (MN2) and the grid of the 3rd PMOS pipe (MP3) respectively, the drain electrode of described the 3rd PMOS pipe (MP3) is connected with ground by the 3rd resistance (R3), the drain electrode of described the 2nd PMOS pipe (MP2) is connected with the drain electrode that the 3rd NMOS manages (MN3), the output terminal of described the first bias current sources (IB1) is managed respectively the drain electrode of (MN1) with a NMOS, the grid of the one NMOS pipe (MN1), the grid of the 2nd NMOS pipe (MN2) is connected with the grid that the 3rd NMOS manages (MN3), the source electrode of a described NMOS pipe (MN1), the source electrode of the 2nd NMOS pipe (MN2) is all connected with ground with the source electrode that the 3rd NMOS manages (MN3), the drain electrode of described the 3rd PMOS pipe (MP3) is connected to the output terminal of amplifier (AMP1).
5. the current-limiting apparatus of a kind of power amplifier according to claim 3, it is characterized in that: described amplifier (AMP1) comprises the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5), the 6th NMOS pipe (MN6), the 4th PMOS pipe (MP4), the 5th PMOS pipe (MP5), the 6th PMOS pipe (MP6) and the second bias current sources (IB2), the inverting input of described amplifier (AMP1) is connected with the source electrode that the 4th NMOS manages (MN4) by the 4th resistance (R4), the grid of described the 4th NMOS pipe (MN4) is connected with the grid of the 5th NMOS pipe (MN5) and the drain electrode of the 5th NMOS pipe (MN5) respectively, the in-phase input end of described amplifier (AMP1) is connected with the source electrode that the 5th NMOS manages (MN5) by the 5th resistance (R5), the source electrode of described the 5th NMOS pipe (MN5) is connected with the source electrode that the 6th NMOS manages (MN6), the drain electrode of described the 4th NMOS pipe (MN4) is connected with the drain electrode of the 5th PMOS pipe (MP5) and the grid of the 6th NMOS pipe (MN6) respectively, the drain electrode of described the 6th NMOS pipe (MN6) is connected with supply voltage by the 6th resistance (R6), the drain electrode of described the 5th NMOS pipe (MN5) is connected with the drain electrode that the 6th PMOS manages (MP6), the input end of described the second bias current sources (IB2) is managed respectively the drain electrode of (MP4) with the 4th PMOS, the grid of the 4th PMOS pipe (MP4), the grid of the 5th PMOS pipe (MP5) is connected with the grid that the 6th PMOS manages (MP6), the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe (MP5) is all connected with supply voltage with the source electrode that the 6th PMOS manages (MP6), the drain electrode of described the 6th NMOS pipe (MN6) is connected to the output terminal of amplifier (AMP1).
6. the current-limiting apparatus of a kind of power amplifier according to claim 3, is characterized in that: described reference voltage source (VF1) includes temperature-compensation circuit.
7. the current-limiting apparatus of a Switching Power Supply, it is characterized in that: comprise amplifier (AMP2), reference voltage source (VF2), comparer (COM2), logic sum gate (OR), rest-set flip-flop (RST), clock signal generator (CLK), PMOS switching tube (PM), nmos switch pipe (NM), inductance (L), electric capacity (C) and device load (RL), the in-phase input end access supply voltage of described amplifier (AMP2), the in-phase input end of described amplifier (AMP2) is connected with the source electrode of PMOS switching tube (PM), the inverting input of described amplifier (AMP2) is connected with the drain electrode of PMOS switching tube (PM) and the drain electrode of nmos switch pipe (NM) respectively, described electric capacity (C) is connected and is attempted by between the drain electrode and source electrode of nmos switch pipe (NM) with inductance (L) again with after device load (RL) parallel connection, the output terminal of described amplifier (AMP2) is connected with the in-phase input end of comparer (COM2), the output terminal of described reference voltage source (VF2) is connected with the inverting input of comparer (COM2), the output terminal of described comparer (COM2) is connected with the first input end of logic sum gate (OR), the second input end access pulse-width signal of described logic sum gate (OR), the output terminal of described logic sum gate (OR) is connected with the R end of rest-set flip-flop (RST), the output terminal of described clock signal generator (CLK) is connected with the S end of rest-set flip-flop (RST), described rest-set flip-flop (RST)
end is connected with the grid of nmos switch pipe (NM), described rest-set flip-flop (RST)
end is connected with the grid of PMOS switching tube (PM).
8. the current-limiting apparatus of a kind of Switching Power Supply according to claim 7, it is characterized in that: described amplifier (AMP2) comprises the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the one PMOS pipe (MP1), the 2nd PMOS pipe (MP2), the 3rd PMOS pipe (MP3), the one NMOS pipe (MN1), the 2nd NMOS pipe (MN2), the 3rd NMOS pipe (MN3) and the first bias current sources (IB1), the inverting input of described amplifier (AMP2) is connected with the source electrode that a PMOS manages (MP1) by the first resistance (R1), the grid of a described PMOS pipe (MP1) is connected with the grid of the 2nd PMOS pipe (MP2) and the drain electrode of the 2nd PMOS pipe (MP2) respectively, the in-phase input end of described amplifier (AMP2) is connected with the source electrode that the 2nd PMOS manages (MP2) by the second resistance (R2), the source electrode of described the 2nd PMOS pipe (MP2) is connected with the source electrode that the 3rd PMOS manages (MP3), the drain electrode of a described PMOS pipe (MP1) is connected with the drain electrode of the 2nd NMOS pipe (MN2) and the grid of the 3rd PMOS pipe (MP3) respectively, the drain electrode of described the 3rd PMOS pipe (MP3) is connected with ground by the 3rd resistance (R3), the drain electrode of described the 2nd PMOS pipe (MP2) is connected with the drain electrode that the 3rd NMOS manages (MN3), the output terminal of described the first bias current sources (IB1) is managed respectively the drain electrode of (MN1) with a NMOS, the grid of the one NMOS pipe (MN1), the grid of the 2nd NMOS pipe (MN2) is connected with the grid that the 3rd NMOS manages (MN3), the source electrode of a described NMOS pipe (MN1), the source electrode of the 2nd NMOS pipe (MN2) is all connected with ground with the source electrode that the 3rd NMOS manages (MN3), the drain electrode of described the 3rd PMOS pipe (MP3) is connected to the output terminal of amplifier (AMP2).
9. the current-limiting apparatus of a kind of Switching Power Supply according to claim 7, it is characterized in that: described amplifier (AMP2) comprises the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 4th NMOS pipe (MN4), the 5th NMOS pipe (MN5), the 6th NMOS pipe (MN6), the 4th PMOS pipe (MP4), the 5th PMOS pipe (MP5), the 6th PMOS pipe (MP6) and the second bias current sources (IB2), the inverting input of described amplifier (AMP2) is connected with the source electrode that the 4th NMOS manages (MN4) by the 4th resistance (R4), the grid of described the 4th NMOS pipe (MN4) is connected with the grid of the 5th NMOS pipe (MN5) and the drain electrode of the 5th NMOS pipe (MN5) respectively, the in-phase input end of described amplifier (AMP2) is connected with the source electrode that the 5th NMOS manages (MN5) by the 5th resistance (R5), the source electrode of described the 5th NMOS pipe (MN5) is connected with the source electrode that the 6th NMOS manages (MN6), the drain electrode of described the 4th NMOS pipe (MN4) is connected with the drain electrode of the 5th PMOS pipe (MP5) and the grid of the 6th NMOS pipe (MN6) respectively, the drain electrode of described the 6th NMOS pipe (MN6) is connected with supply voltage by the 6th resistance (R6), the drain electrode of described the 5th NMOS pipe (MN5) is connected with the drain electrode that the 6th PMOS manages (MP6), the input end of described the second bias current sources (IB2) is managed respectively the drain electrode of (MP4) with the 4th PMOS, the grid of the 4th PMOS pipe (MP4), the grid of the 5th PMOS pipe (MP5) is connected with the grid that the 6th PMOS manages (MP6), the source electrode of described the 4th PMOS, the source electrode of the 5th PMOS pipe (MP5) is all connected with supply voltage with the source electrode that the 6th PMOS manages (MP6), the drain electrode of described the 6th NMOS pipe (MN6) is connected to the output terminal of amplifier (AMP2).
10. the current-limiting apparatus of a kind of Switching Power Supply according to claim 7, is characterized in that: described reference voltage source (VF2) includes the compensating circuit for supplementing PMOS switching tube (PM) conducting resistance changing with temperature, operating voltage and process deviation.
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| CN104897943A (en) * | 2015-04-30 | 2015-09-09 | 中国电子科技集团公司第五十八研究所 | High-sensitivity low-power current detection circuit |
| CN107852012A (en) * | 2015-08-10 | 2018-03-27 | 德克萨斯仪器股份有限公司 | Reverse-current protection circuit |
| CN107852012B (en) * | 2015-08-10 | 2021-05-04 | 德克萨斯仪器股份有限公司 | Reverse current protection circuit |
| CN105375764A (en) * | 2015-11-11 | 2016-03-02 | 矽力杰半导体技术(杭州)有限公司 | Switch tube control circuit |
| CN105375764B (en) * | 2015-11-11 | 2018-05-29 | 矽力杰半导体技术(杭州)有限公司 | Switch controlled circuit |
| CN105846493A (en) * | 2016-04-19 | 2016-08-10 | 无锡中感微电子股份有限公司 | Overcurrent detection circuit, overcurrent protection circuit and battery |
| CN105846493B (en) * | 2016-04-19 | 2018-08-28 | 无锡中感微电子股份有限公司 | Over-current detection, protection circuit and battery |
| CN108572273A (en) * | 2017-03-10 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Low current measuring circuit and its measurement method |
| WO2019109363A1 (en) * | 2017-12-09 | 2019-06-13 | Dongguan Bang Bang Tang Electronic Technologies Co., Ltd. | Current sensor for biomedical measurements |
| CN111448464A (en) * | 2017-12-09 | 2020-07-24 | 深圳市丹砂科技有限公司 | Current sensor for biomedical measurements |
| CN108153367A (en) * | 2017-12-28 | 2018-06-12 | 广州慧智微电子有限公司 | A kind of tc compensation circuit of bonding semiconductor line |
| CN108306269A (en) * | 2018-01-12 | 2018-07-20 | 矽力杰半导体技术(杭州)有限公司 | Current-limiting circuit |
| CN108306269B (en) * | 2018-01-12 | 2019-09-10 | 矽力杰半导体技术(杭州)有限公司 | Current-limiting circuit |
| CN108957334A (en) * | 2018-05-18 | 2018-12-07 | 华润矽威科技（上海）有限公司 | battery sampling system |
| CN108957334B (en) * | 2018-05-18 | 2024-03-08 | 华润微集成电路(无锡)有限公司 | Battery sampling system |
| CN109039071A (en) * | 2018-08-20 | 2018-12-18 | 无锡麟力科技有限公司 | A kind of switching-on and switching-off state detection circuit |
| CN109039071B (en) * | 2018-08-20 | 2023-12-01 | 无锡麟力科技有限公司 | Power switch state detection circuit |
| CN109521254A (en) * | 2018-12-27 | 2019-03-26 | 南京睿赫电子有限公司 | Current detection circuit and power supply device with the current detection circuit |
| CN114167125A (en) * | 2021-07-29 | 2022-03-11 | 沈阳工业大学 | Current detection circuit |
| CN114167125B (en) * | 2021-07-29 | 2023-12-12 | 沈阳工业大学 | Current detection circuit |
| CN114089226A (en) * | 2022-01-18 | 2022-02-25 | 成都市安比科技有限公司 | Active load detection circuit with anti-static damage and controllable overcurrent protection functions |
| CN116203304A (en) * | 2023-04-28 | 2023-06-02 | 苏州贝克微电子股份有限公司 | Current detection circuit with low temperature drift |
| CN116566021A (en) * | 2023-07-07 | 2023-08-08 | 苏州贝克微电子股份有限公司 | Zero temperature coefficient circuit structure |
| CN116566021B (en) * | 2023-07-07 | 2023-09-22 | 苏州贝克微电子股份有限公司 | Zero temperature coefficient circuit structure |
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