CN103955434B - Data writing-in method, memory controller and memory storage device - Google Patents
Data writing-in method, memory controller and memory storage device Download PDFInfo
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Abstract
The invention provides a data writing-in method, a memory controller and a memory storage device. The data writing-in method comprises the following steps: grouping a plurality of entity blocks into a plurality of entity units, grouping the entity units into data zones and idle zones at least, and configuring a plurality of logic units so as to map the entity units belonging to the data zones. The data writing-in method further comprises the following steps: extracting one entity unit from the entity units belonging to the idle zones, writing at least one data which belongs to at least one logic unit of the logic units in the extracted entity unit, writing an ending mark in the extracted entity unit, and connecting the ending mark behind the data belonging to the logic unit in the extracted entity unit. Therefore, the entity units can be effectively used, and the service life of the memory storage device can be prolonged.
Description
The application is Application No. 201010504333.X that on October 8th, 2010 submits, entitled data write
The divisional application of method, Memory Controller and memorizer memory devices.
Technical field
The present invention relates to a kind of method for writing data, more particularly to a kind of data for nonvolatile memory module are write
Enter method and the Memory Controller and memorizer memory devices using the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in development over the years so that the storage of consumer's logarithm digital content
Demand also rapidly increases.Because flash memory (Flash Memory) has data non-volatile, power saving, small volume and mechanical structure
Deng characteristic, suitable user carry with as digital document transmission and the store media for exchanging.
Traditionally, the purposes of flash memory mainly stores user data.For example, user can use Portable disk
To store digital document, or using memory card as the portable apparatus such as digital camera, MP3 player store media, this
(for example, data volume is the number of 64Kb or more than 128Kb to the larger digital data of class flash memory major storage data volume
According to).
With the development of flash memory technology so that the storage volume of flash memory is increasing and cost is more and more lower,
Therefore many computermakers start to use the solid state hard disc (Solid State Drive, SSD) using flash memory as store media
As the main magnetic disc of computer system.By computer system operating system can regularly in main magnetic disc repeatedly write with
The less data of the amount of updating the data (for example, data volume is 4Kb or 8Kb data below).
Based on the physical characteristics of flash memory, it is only capable of carrying out unidirectional sequencing (that is, the bit in memory cell in flash memory memory cell
Must first will be previously stored in memory cell when being only capable of from 1 program turning to 0), therefore writing data in the memory cell of flash memory
Data can re-write new data after erasing.
In the design of flash memory system, in general, the flash memory physical blocks of flash memory system can be grouped into many
Individual solid element (that is, each solid element is made up of one or more physical blocks), has at least in the solid element
One flash memory cell (flash memory cell), each cell is made up of an at least electric crystal, such as MOSFET or other electricity
Crystal or logic circuit, respectively the cell can store at least one bit, and these solid elements can be grouped into data field (data
Area) with idle area (free area).Classify as can store in the solid element of data field by write instruction write it is effective
Data, and the solid element in idle area is to the solid element in the replacement data area when write instruction is performed.It is concrete next
Say, when flash memory system receives the write instruction of main frame and is intended to write the solid element of data field, flash memory storage
Deposit system can extract a solid element and by the effective old number in the solid element to be write within a data area from idle area
According to the new data to be write write to from idle area extract solid element and by written into the solid element of new data
It is associated as data field, and the solid element of the former data field is erased and idle area is associated as.In order to allow main frame
The solid element that data are stored in the mode of rotating can be successfully accessed, flash memory system can provide logical block to map this
A little solid elements.Specifically, change to corresponding logic the logic access address that flash memory system can be accessed in main frame
Unit, and by logical block-solid element mapping table (logical unit-physical unit mapping
Table the enantiomorphic relationship between logical block and the solid element of data field is recorded and updated in) to reflect the wheel of solid element
Replace, so main frame only needs to enter line access according to logic access address, and flash memory system can be according to logical block-solid element
Mapping table carries out the reading or write of data to the solid element of institute's mapping.
Under operational architecture based on above-mentioned flash memory system, using flash memory system application as computer system master
During hard disk, because computer system can repeatedly write and the less data of the amount of updating the data regularly, so flash memory storage system
The solid element of system can continually be carried out erasing action to write the data that computer system is updated in the above-mentioned mode of rotating.So
And, the number of times of erasing for constituting the physical blocks of solid element is that limited (such as physical blocks are erased and will damage after 10,000 times
It is bad), therefore will significantly shorten the life-span of flash memory when solid element is continually erased.
The content of the invention
The present invention provides a kind of method for writing data and Memory Controller, and it can reduce erasing for solid element, by
This effectively increases the efficiency of memorizer memory devices and extends the life-span of memorizer memory devices.
Additionally, the present invention provides a kind of memorizer memory devices, it has longer service life with preferably write effect
Energy.
Exemplary embodiment of the present invention provides a kind of method for writing data, for writing data to multiple physical blocks.The number
Include for these physical blocks being grouped into multiple solid elements according to wiring method, these solid elements are at least grouped into into data field
With idle area, and multiple logical blocks are configured to map the solid element for belonging to data field.The method for writing data also includes
One solid element of extraction among the solid element in idle area is subordinated to, at least logic among these logical blocks will be belonged to
An at least data of unit are write into the solid element for being extracted, and write one terminates mark in the solid element for being extracted
Note, wherein this end mark is connected in after the data for belonging to this logical block in the solid element for being extracted.
Exemplary embodiment of the present invention proposes a kind of method for writing data, for writing data to multiple physical blocks.The number
Include for these physical blocks being grouped into multiple solid elements according to wiring method, these solid elements are at least grouped into into data field
With idle area, and multiple logical blocks are configured to map the solid element for belonging to data field.The method for writing data also includes
Reception belongs to the first data of the first logical block among these logical blocks, wherein the first logical unit mappings belong to data
First instance unit among the solid element in area.The method for writing data also includes that judging whether the first logical block enters mixes
Random write state, and when the first logical block enters chaotic write state, the method for writing data also includes being subordinated to the spare time
The 3rd solid element of extraction among the solid element in area is put, and the first data are write in order into the 3rd solid element.
The method for writing data also includes receiving the second data for belonging to the second logical block among these logical blocks, wherein this
Two logical unit mappings belong to the second instance unit among the solid element of data field.The method for writing data also includes judging
Whether this second logical block enters chaotic write state, and when the second logical block enters chaotic write state, the number
Also include in order writing the second data into the 3rd solid element according to wiring method.The method for writing data is also included to
One logical block performs a data consolidation procedure with the second logical block, and to the first logical block and the second logical block
After performing data consolidation procedure, end mark is write in the 3rd solid element, wherein this terminates in the 3rd solid element
Labelling is connected in after the first data and the second data.
Exemplary embodiment of the present invention provides a kind of storage arrangement, for managing non-volatile memory module, wherein this
Nonvolatile memory module has multiple physical blocks.This Memory Controller includes HPI, memory interface and deposits
Reservoir manages circuit.HPI is electrically connected to host computer system, and memory interface be electrically connected to it is non-easily
The property lost memory module.Memory management circuitry is electrically connected with so far HPI and this memory interface, and to perform
Above-mentioned method for writing data.
Exemplary embodiment of the present invention proposes a kind of memory storage system, and it includes adapter, nonvolatile memory mould
Group and Memory Controller.Nonvolatile memory module has multiple physical blocks.Memory Controller is electrically connected with so far
Nonvolatile memory module and this adapter, and to perform above-mentioned method for writing data.
Based on above-mentioned, the method for writing data of exemplary embodiment of the present invention can effectively extend with Memory Controller to be deposited
The life-span of reservoir storage device.Also, configure using the memory storage dress of the Memory Controller of above-mentioned method for writing data
Put with longer service life.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Description of the drawings
Figure 1A is the host computer system and memorizer memory devices according to exemplary embodiment of the present invention.
Figure 1B is computer according to exemplary embodiment of the present invention, input/output device and memorizer memory devices
Schematic diagram.
Fig. 1 C are the schematic diagrams of the host computer system according to another exemplary embodiment of the invention and memorizer memory devices.
Fig. 2 is the schematic block diagram of the memorizer memory devices shown in Figure 1A.
Fig. 3 is the schematic block diagram of the Memory Controller according to exemplary embodiment of the present invention.
Fig. 4 is the schematic block diagram of the nonvolatile memory module according to an exemplary embodiment of the invention.
Fig. 5 and Fig. 6 is the schematic diagram of the management entity unit according to exemplary embodiment of the present invention.
Fig. 7～Fig. 9 be according to exemplary embodiment of the present invention write data to general write mode it is non-volatile
The example of memory module.
Figure 10 A～10B is that the example for writing data with chaotic write mode according to exemplary embodiment of the present invention shows
It is intended to.
Figure 10 C are that the data to being write with chaotic write mode according to exemplary embodiment of the present invention perform data
The example schematic of consolidation procedure.
Figure 11 is that the example for writing data with chaotic write mode according to another exemplary embodiment of the invention is illustrated
Figure.
Figure 12 is the example schematic of the chaotic solid element according to another exemplary embodiment of the invention.
Figure 13 is the flow chart of the method for writing data according to exemplary embodiment of the present invention.
Main Reference Numerals explanation：
1000：Host computer system； 1100：Computer；
1102：Microprocessor； 1104：Random access memory；
1106：Input/output device； 1108：System bus；
1110：Data transmission interface； 1202：Mouse；
1204：Keyboard； 1206：Display；
1208：Printer； 1212：Portable disk；
1214：Memory card； 1216：Solid state hard disc；
1310：Digital camera； 1312：SD card；
1314：Mmc card； 1316：Memory stick；
1318：CF cards； 1320：Embedded storage device；
100：Memorizer memory devices； 102：Adapter；
104：Memory Controller； 106：Nonvolatile memory module；
202：Memory management circuitry； 204：HPI；
206：Memory interface； 252：Buffer storage；
254：Electric power management circuit； 256：Error checking and correcting circuit；
410：First memory submodule group； 420：Second memory submodule group；
430：3rd memorizer submodule group； 440：4th memorizer submodule group；
410 (0)～410 (R), 420 (0)～420 (R), 430 (0)～430 (R), 440 (0)～440 (R)：Physical blocks；
D：Data bit element area； R：Redundancy bit area；
310 (0)～310 (R)：Solid element； 502：Data field；
504：Idle area； 506：System area；
508：Replace area；510 (0)～510 (H)：Logical block；
S1301、S1303、S1305、S1307、S1309、S1311、S1313、S1315、S1317、S1319、S1321：Number
According to the step of write.
Specific embodiment
In general, memorizer memory devices (also known as, memory storage system) include nonvolatile memory module with
Controller (also known as, control circuit).Being commonly stored device storage device is used together with host computer system, so that host computer system can be by
Data write to memorizer memory devices or read from memorizer memory devices data.
Figure 1A is according to exemplary embodiment host computer system of the present invention and memorizer memory devices.
Figure 1A is refer to, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/O)
Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM)
1104th, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes the mouse 1202, key such as Figure 1B
Disk 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Figure 1B
1106, input/output device 1106 can also include other devices.
In embodiments of the present invention, memorizer memory devices 100 are by data transmission interface 1110 and host computer system
1000 other elements are electrically connected with.By microprocessor 1102, random access memory 1104 and input/output device 1106
Running can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, deposit
Reservoir storage device 100 can be Portable disk 1212 as shown in Figure 1B, memory card 1214 or solid state hard disc (Solid State
Drive, SSD) 1216 grades non-volatile memory storage device.
In general, host computer system 1000 can be substantially any system that can store data.Although implementing in this example
In example, host computer system 1000 is explained with computer system, however, the host computer system in another exemplary embodiment of the invention
1000 can be the systems such as digital camera, camera, communicator, music player or video signal player.For example, in main frame system
Unite for digital camera (camera) 1310 when, non-volatile memory storage device is then SD card 1312, mmc card that it is used
1314th, memory stick (memory stick) 1316, CF cards 1318 or embedded storage device 1320 (as shown in Figure 1 C).It is embedded
Storage device 1320 includes embedded multi-media card (Embedded MMC, eMMC).It is noted that embedded multi-media card
It is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram of the memorizer memory devices shown in Figure 1A.
Fig. 2 is refer to, memorizer memory devices 100 include that adapter 102, Memory Controller 104 are deposited with non-volatile
Reservoir module 106.
In this exemplary embodiment, adapter 102 connects for USB (universal serial bus) (Universal Serial Bus, USB)
Connect device.However, it is necessary to be appreciated that, the invention is not restricted to this, adapter 102 can also be Institute of Electrical and Electric Engineers
(Institute of Electrical and Electronic Engineers, IEEE) 1394 adapters, external components are mutual
Even standard interface (Peripheral Component Interconnect Express, PCI Express) adapter, serial
Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) adapter, safe digital
(Secure Digital, SD) interface connector, memory stick (Memory Stick, MS) interface connector, Multi Media Card
(Multi Media Card, MMC) interface connector, compact flash (Compact Flash, CF) interface connector, integrated set
Standby circuit interface (Integrated Device Electronics, IDE) adapter or other suitable adapters.
Memory Controller 104 refers to the multiple gates or control performed with hardware pattern or firmware pattern implementation
Order, and the write of data is carried out in nonvolatile memory module 106 according to the instruction of host computer system 1000, is read and is smeared
Operate except waiting.In this exemplary embodiment, Memory Controller 104 is to the data write side according to exemplary embodiment of the present invention
Method carrys out managing non-volatile memory module 106 with storage management method.Write according to the data of exemplary embodiment of the present invention
Method will elaborate with storage management method in following cooperation accompanying drawing.
Nonvolatile memory module 106 is electrically connected to Memory Controller 104, and to store host computer system
1000 data for being write.In this exemplary embodiment, nonvolatile memory module 106 is duplicative non-volatile memories
Device module.For example, nonvolatile memory module 106 is multistage memory cell (Multi Level Cell, MLC) nand flash memory mould
Group.However, the invention is not restricted to this, nonvolatile memory module 106 may also be single-order memory cell (Single Level
Cell, SLC) nand flash memory module, other flash memory modules or other there is the memory module of identical characteristics.
Fig. 3 is the schematic block diagram of the Memory Controller according to exemplary embodiment of the present invention.
Fig. 3 is refer to, Memory Controller 104 includes that memory management circuitry 202, HPI 204 connect with memorizer
Mouth 206.
Memory management circuitry 202 to control memory controller 104 overall operation.Specifically, memorizer pipe
Reason circuit 202 has multiple control instructions, and when memorizer memory devices 100 are operated, these control instructions can be performed
With according to the method for writing data of this exemplary embodiment and storage management method come managing non-volatile memory module 106.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.For example,
Memory management circuitry 202 has microprocessor unit (not shown) and read only memory (not shown), and these controls refer to
Order is by imprinting so far read only memory.When memorizer memory devices 100 are operated, these control instructions can be by microprocessor
Unit is performing method for writing data and storage management method to complete according to exemplary embodiment of the present invention.
In another exemplary embodiment of the invention, the control instruction of memory management circuitry 202 can also procedure code pattern
(storage system data for example, are exclusively used in memory module is to be stored in the specific region of nonvolatile memory module 106
System area) in.Additionally, memory management circuitry 202 have microprocessor unit (not shown), read only memory (not shown) and with
Machine access memorizer (not shown).Particularly, this read only memory has driving code section, and when the quilt of Memory Controller 104
During enable, microprocessor unit can first carry out the control that this drives code section to be stored in nonvolatile memory module 106
Instruction is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate, and these are controlled
Instruct to perform the method for writing data and storage management method of the first exemplary embodiment of the invention.Additionally, of the invention another
In one exemplary embodiment, the control instruction of memory management circuitry 202 can also a hardware pattern carry out implementation.
HPI 204 is electrically connected to memory management circuitry 202 and to receive and identification host computer system
1000 instructions for being transmitted and data.That is, the instruction that host computer system 1000 is transmitted can pass through HPI with data
204 being sent to memory management circuitry 202.In this exemplary embodiment, it is USB that HPI 204 is correspondence adapter 102
Interface.The invention is not restricted to this however, it is necessary to be appreciated that, HPI 204 can also be that PATA interfaces, IEEE1394 connect
Mouth, PCI Express interfaces, SATA interface, SD interface, MS interfaces, MMC interfaces, CF interfaces, ide interface or other are suitable
Data transmission interface.
Memory interface 206 is electrically connected to memory management circuitry 202 and to access nonvolatile memory
Module 106.That is, be intended to write to the data of nonvolatile memory module 106 can be converted to via memory interface 206
The receptible form of the institute of nonvolatile memory module 106.
In an exemplary embodiment of the invention, Memory Controller 104 also includes buffer storage 252.Buffer storage
252 be electrically connected to memory management circuitry 202 and being configured to temporarily store come from the data of host computer system 1000 and instruction or
Come from the data of nonvolatile memory module 106.
In an exemplary embodiment of the invention, Memory Controller 104 also includes electric power management circuit 254.Power management
Circuit 254 is electrically connected to memory management circuitry 202 and to the power supply of control memory storage device 100.
In an exemplary embodiment of the invention, Memory Controller 104 also includes error checking and correcting circuit 256.It is wrong
Flase drop is looked into and is electrically connected to memory management circuitry 202 and to perform error checking with correction journey with correcting circuit 256
Sequence is guaranteeing the correctness of data.Specifically, refer to when memory management circuitry 202 receives write from host computer system 1000
When making, error checking produces corresponding error checking and correcting code with the data that correcting circuit 256 can be corresponding this write instruction
(Error Checking and Correcting Code, ECC Code), and memory management circuitry 202 can correspond to this
The data of write instruction are write into nonvolatile memory module 106 with corresponding error checking and correcting code.Afterwards, when depositing
Reservoir management circuit 202 can simultaneously read the corresponding mistake of this data when data are read from nonvolatile memory module 106
Check and correcting code, and the data that error checking and correcting circuit 256 can be according to this error checking and correcting codes to being read
Perform error checking and correction program.
Fig. 4 is the schematic block diagram of the nonvolatile memory module according to exemplary embodiment of the present invention.
Fig. 4 is refer to, nonvolatile memory module 106 includes first memory submodule group 410, second memory submodule
The 420, the 3rd memorizer submodule group 430 of group and the 4th memorizer submodule group 440, wherein first memory submodule group 410 have real
Body block 410 (0)～410 (R)；Second memory submodule group 420 has physical blocks 420 (0)～420 (R)；3rd memorizer
Submodule group 430 has physical blocks 430 (0)～430 (R)；And the 4th memorizer submodule group 440 there are physical blocks 440 (0)
～440 (R).For example, first memory submodule group 410, second memory submodule group 420, the 3rd memorizer submodule group 430 and
Four memorizer submodule groups 440 are to be electrically connected to Memory Controller 104 separately by independent data/address bus.However, must
It will be appreciated that in another exemplary embodiment of the invention, first memory submodule group 410, second memory submodule group 420,
3rd memorizer submodule group 430 can also pass through 1 data/address bus or 2 data/address bus and deposit with the 4th memorizer submodule group 440
Memory controller 104 is electrically connected with.First memory submodule group 410, second memory submodule group 420, the 3rd memorizer submodule
Each physical blocks in the memorizer submodule group 440 of group 430 and the 4th have respectively a plurality of physical pages, wherein belonging to same
The physical page of individual physical blocks can be written independently and simultaneously be erased.For example, each physical blocks are by 128 realities
The body page is constituted.However, it is necessary to be appreciated that, the invention is not restricted to this, each physical blocks be can by 64 physical pages,
256 physical pages or other arbitrarily physical pages are constituted.
In more detail, physical blocks are the least unit erased.That is, each physical blocks contain the one of minimal amount
And the memory cell being erased.Physical page is the least unit of sequencing.That is, physical page is the least unit for writing data.
However, it is necessary to be appreciated that, in another exemplary embodiment of the invention, the least unit for writing data can also be sector
Or other sizes (Sector).Each physical page generally includes data bit element area D and redundancy bit area R.Data bit element area D is used
To store the data of user, and redundancy bit area R is to the data (for example, error checking and correcting code) of stocking system.
Additionally, first memory submodule group 410, second memory submodule group 420, the 3rd memorizer submodule group 430 and
The physical blocks of four memorizer submodule groups 440 can generally also be grouped into several regions (zone), be come with each independent region
Management entity block 410 (0)～410 (R), physical blocks 420 (0)～420 (R), physical blocks 430 (0)～430 (R) and reality
Body block 440 (0)～440 (R) can increase the parallel degree of operation execution and the complexity of streamlining management.
Although it is noted that exemplary embodiment of the present invention is with including non-volatile the depositing of 4 memorizer submodule groups
Describe as a example by reservoir module 106, but the invention is not restricted to this.
In this exemplary embodiment, the memory management circuitry 202 of Memory Controller 104 can be by physical blocks 410 (0)
～410 (R), physical blocks 420 (0)～420 (R), physical blocks 430 (0)～430 (R) and physical blocks 440 (0)～440
(R) solid element 310 (0)～310 (R) is grouped into, and carrys out managing non-volatile memory in units of each solid element
Module 106.If that is, when each physical blocks has 128 physical pages, each solid element can include 512
Individual physical page, and memory management circuitry 202 can carry out managing non-volatile memory mould in units of 512 physical pages
Group 106.
Fig. 5 and Fig. 6 is the schematic diagram of the management entity unit according to exemplary embodiment of the present invention.
Fig. 5 is refer to, the memory management circuitry 202 of Memory Controller 104 can be by solid element 310 (0)～310
(R) data field 502, idle area 504, system area 506 are logically grouped into and replace area 508.
It is to store to come from host computer system 1000 that data field 502 is logically belonged to the solid element in idle area 504
Data.Specifically, data field 502 is the solid element for having stored data, and the solid element in idle area 504 is to replace
Change the solid element of data field 502.Therefore, the solid element in area 504 of leaving unused is solid element that is empty or can using, i.e. no record
Data are labeled as invalid data useless.That is, the solid element in idle area 504 has been performed fortune of erasing
Make, or the solid element extracted before the solid element in idle area 504 is extracted for storing data can be performed
Erase running.Therefore, the solid element in idle area 504 is the solid element that can be used.
The solid element for logically belonging to system area 506 is that, to record system data, wherein this system data includes closing
In the manufacturer and model, the physical blocks number of nonvolatile memory module, each entity area of nonvolatile memory module
Physical page number of block etc..
Logically belong to replace the solid element in area 508 to be to substitute solid element.For example, nonvolatile memory module
106 can reserve 4% solid element when dispatching from the factory uses as replacing.That is, when data field 502, idle area 504 and being
When solid element in system area 506 is damaged, it is to replacing damaged entity list to reserve in the solid element in area 508 is replaced
Unit.Therefore, if still have normal solid element in replacement area 508 and solid element damage occurs, memory management electricity
Road 202 can extract normal solid element to change the solid element of damage from replacing in area 508.If replacing nothing in area 508
When normal solid element and generation solid element damage, then memory management circuitry 202 can be by whole memory storage device
100 are declared as write protection (write protect) state, and cannot again write data.
Particularly, the quantity of data field 502, idle area 504, system area 506 and the solid element for replacing area 508 can foundation
Different memorizer specification and it is different.Further, it is necessary to be appreciated that, in the running of memorizer memory devices 100, entity
Unit is associated to data field 502, idle area 504, system area 506 can dynamically be changed with the packet relation for replacing area 508.Example
Such as, when the solid element in idle area 504 is damaged and the solid element in substituted area replaces, then the reality in area 508 is replaced originally
Body unit can be associated to idle area 504.
Fig. 6 is refer to, as described above, data field 502 is to store master in the mode of rotating with the solid element in idle area 504
The data that machine system 1000 is write.In this exemplary embodiment, memory management circuitry 202 can configuration logic unit 510 (0)
～510 (H) rotate mode storing the solid element of data to map with above-mentioned, and by logical block 510 (0)～510 (H)
The logic access address that host computer system 1000 is accessed is mapped to, data are accessed with sharp host computer system 1000.
For example, logical block 510 (0)～510 (H) initially can be mapped to data field 502 by memory management circuitry 202
Solid element.Specifically, when memorizer memory devices 100 are done manufacture, logical block 510 (0)～510 (H) point
Do not map to the solid element 310 (0)～310 (D) of data field 502.That is, a logical block can map data field
A solid element in 502.Here, memory management circuitry 202 can set up logical block-solid element mapping table
(logical unit-physical unit mapping table), to record the mapping between logical block and solid element
Relation.That is, the meeting of the memory management circuitry 202 logic access address to be accessed host computer system 1000 is converted into correspondence
Logical block, data are accessed in physical address from there through logical block-solid element mapping table.
Fig. 7～Fig. 9 be according to exemplary embodiment of the present invention write data to general write mode it is non-volatile
The example of memory module.
It is to map to the mapping of solid element 310 (0) in logical block 510 (0) for example referring to Fig. 7～Fig. 9
Under state, it is intended to write data to belong to logic when Memory Controller 104 receives write instruction from host computer system 1000
During the logic access address of unit 510 (0), memory management circuitry 202 can be according to logical block-solid element mapping table identification
Logical block 510 (0) is currently to map to solid element 310 (0) and extraction solid element 310 (D+1) from idle area 504
As replacement solid element come solid element 310 (0) of rotating.However, when memory management circuitry 202 is write new data into reality
While body unit 310 (D+1), memory management circuitry 202 will not at once by all significant figures in solid element 310 (0)
According to moving to solid element 310 (D+1) solid element 310 (0) of erasing.Specifically, memory management circuitry 202 can be by reality
Valid data in body unit 310 (0) before physical page to be write (that is, the 0th physical page of solid element 310 (0) and the
Data in 1 physical page) it is copied in the 0th physical page of solid element 310 (D+1) and the 1st physical page (such as Fig. 7 institutes
Show), and write new data into into the 2nd physical page and the 3rd physical page of solid element 310 (D+1) (such as Fig. 8 institutes
Show).Now, memory management circuitry 202 completes the running for writing.Can because the valid data in solid element 310 (0) have
Can become invalid in next operation (for example, write instruction), therefore at once remove the valid data in solid element 310 (0)
Move to solid element 310 (D+1) and be likely to result in meaningless moving.Additionally, data must be write in order to solid element
Physical page, therefore, memory management circuitry 202 only can first move the valid data before physical page to be write.
In this exemplary embodiment, these mother and sons' transient state relation (that is, solid element 310 (0) and entity lists are temporarily maintained
310 (D+1) of unit) running referred to as open (open) mother and sons' unit, and former solid element is referred to as female solid element and replaces reality
Body unit is referred to as sporophore unit.
Afterwards, when needing for solid element 310 (0) to merge (merge) with the content of solid element 310 (D+1), storage
Device management circuit 202 just can be whole and to a solid element by the data of solid element 310 (0) and solid element 310 (D+1),
Thus the service efficiency of solid element is lifted.Here, the running for merging mother and sons' unit is referred to as data consolidation procedure or closing
(close) mother and sons' unit.For example, as shown in figure 9, when carrying out closing mother and sons' unit, memory management circuitry 202 can be by entity
Remaining valid data are (that is, in the 4th physical page～the (K) physical page of solid element 310 (0) in unit 310 (0)
Data) be copied to replace solid element 310 (D+1) the 4th physical page～the (K) physical page in, then by solid element
310 (0) erase and associate to idle area 504, meanwhile, solid element 310 (D+1) is associated to data field 502.That is,
Memory management circuitry 202 can remap logical block 510 (0) to entity in logical block-solid element mapping table
Unit 310 (D+1).Additionally, in this exemplary embodiment, memory management circuitry 202 can set up idle area's solid element table (not
Diagram) recording the solid element for being associated to idle area at present.It is noted that in idle area 504 solid element number
Mesh be it is limited, base this, memorizer memory devices 100 operate during, the group number of mother and sons' unit of unlatching also can be restricted.
Therefore, when memorizer memory devices 100 receive the write instruction for coming from host computer system 1000, if having turned on mother and sons' list
The group number of unit is when reaching the upper limit, and memory management circuitry 202 need to close mother and sons' unit that least one set has turned at present and (that is, hold
Go and close mother and sons' cell operation) to perform this write instruction.Here, the write running shown in Fig. 7～Fig. 9 is referred to as general write mould
Formula.
In this exemplary embodiment, the memory management circuitry 202 of Memory Controller 104 is above-mentioned general except performing
Outside write mode, also data are write to perform chaotic write mode (Random Writing Mode).
Specifically, because the sequencing code requirement of nonvolatile memory module must be from each physical blocks
Beginning physical page start write to last physical page and each bit be only capable of program once (i.e. by be only capable of " 1 " become
For " 0 ") under conditions of, the physical page once physical blocks is written into after data, if be intended to update written into data it is just necessary
Extract a physical blocks from idle area 504 to re-start the step shown in Fig. 7～9.Therefore, when physical blocks are not being carried out
Before closing mother and child blocks running shown in Fig. 9 (i.e. in the transient state shown in Fig. 8), and occur that the data just moved must be updated
When (such as the data in the 0th physical page and the 1st physical page shown in Fig. 7), then the legacy data moved just must be removed again
Move once.Particularly, memorizer memory devices 100 as host computer system 1000 system disk (that is, installation exercise system
Hard disk) when, host computer system 1000 can access a small amount of data on identity logic access address.For example, the meeting of host computer system 1000
Continually change file configuration table (File Allocation Table, FAT).Now, memory management circuitry 202 can be by this
Logical block is considered as into chaotic write state, and with chaotic write mode by the data of this logical block write to it is non-easily
In the property lost memory module 106.For example, when with chaotic write mode to write data, memory management circuitry 202 can be from the spare time
Put and extract in area 504 solid element as chaotic solid element and directly from the initial physical page of the solid element for being extracted
Face starts to write new data and do not carry out the action shown in Fig. 7 (that is, replicating the action of valid data).Also, when chaotic write
State extracts again another solid element to carry out data consolidation procedure after terminating from idle area 504, will corresponding this logic list
All valid data of unit are arranged into the solid element for being extracted.
Particularly, in this exemplary embodiment, memory management circuitry 202 will can enter one of chaotic write state or
The data of multiple logical blocks are write into same chaotic solid element.For example, in this exemplary embodiment, memory management
Circuit 202 can write the data for entering 2 logical blocks of chaotic write state into same chaotic solid element.
Figure 10 A～10B is that the example for writing data with chaotic write mode according to exemplary embodiment of the present invention shows
It is intended to, it belongs to the first logical block (that is, logical block 510 with chaotic write mode by come from host computer system 1000
(0) data (also referred to as the first data)) are with the data for belonging to the second logical block (that is, logical block 510 (4)) (also referred to as
Second data) write to the example of chaotic solid element, wherein assuming that logical block 510 (0) is to map to first instance unit
(that is, solid element 310 (0)) and logical block 510 (4) are to map to second instance unit (that is, solid element 310 (4)).
Figure 10 A are refer to, when the 3rd logical page (LPAGE) for being intended to belong to logical block 510 (0) with the write of chaotic write mode
During data (that is, updating the 3rd physical page of solid element 310 (0)), memory management circuitry 202 can be from idle area 504
The 3rd solid element (that is, solid element 310 (D+1)) is extracted as chaotic solid element, and this data is write to entity
In 0th physical page of unit 310 (D+1).
Afterwards, when being intended to write the data of the 2nd logical page (LPAGE) for belonging to logical block 510 (4) with chaotic write mode
When (that is, updating the 2nd physical page of solid element 310 (4)), memory management circuitry 202 can will belong to logical block 510
(4) data of the 2nd logical page (LPAGE) are write into the 1st physical page of solid element 310 (D+1).
Figure 10 B are refer to, in the state of shown in Figure 10 A, when being intended to write the 2nd logic for belonging to logical block 510 (0)
During data (that is, the updating the 2nd physical page of solid element 310 (0)) of the page, memory management circuitry 202 will can belong to
The data of the 2nd logical page (LPAGE) of logical block 510 (0) are write into the 2nd physical page of solid element 310 (D+1).Class
As, afterwards, when the data for being intended to write the 1st logical page (LPAGE) for belonging to logical block 510 (4) (that is, update solid element 310
(4) the 1st physical page) when, memory management circuitry 202 can belong to the 1st logical page (LPAGE) of logical block 510 (4)
Data write into the 3rd physical page of solid element 310 (D+1).
Based on above-mentioned, as shown in Figure 10 A and Figure 10 B, in chaotic write mode, data will not as shown in Fig. 7～Fig. 9 according to
Write according to corresponding physical page, therefore, can save the time of moving data, improve access speed.
It is noted that the number of solid element is limited in idle area 504, therefore, in memorizer memory devices
During 100 runnings, also be able to can be restricted as the number of the solid element of chaotic solid element.For example, when have been used as
The number of the solid element of chaotic solid element is more than predetermined threshold level and needs to extract an entity list from idle area 504
During the chaotic solid element of first logical block as corresponding to next write instruction, Memory Controller 104 can perform number
Valid data are arranged according to consolidation procedure, thus the solid element for all storing invalid data is associated to idle area 504.Or,
At the end of chaotic write mode, Memory Controller 104 can also perform data consolidation procedure to arrange valid data, thus
The solid element for all storing invalid data is associated to idle area 504.
Figure 10 C are that the data to being write with chaotic write mode according to exemplary embodiment of the present invention perform data
The example schematic of consolidation procedure, it performs the model of data consolidation procedure to logical block 510 (0) and logical block 510 (4)
Example.
Figure 10 C are refer to, memory management circuitry 202 can extract the 4th solid element (that is, entity from idle area 504
Unit 310 (D+2)) and the 5th solid element (that is, solid element 310 (D+3)).Also, memory management circuitry 202 can be by reality
The valid data for belonging to logical block 510 (0) in body unit 310 (0) and solid element 310 (D+1) are moved to solid element 310
(D+2) and in logical block-solid element mapping table logical block 510 (0) is mapped to into (or claiming association extremely) entity list
310 (D+2) of unit.Additionally, memory management circuitry 202 can be patrolled belonging in solid element 310 (4) and solid element 310 (D+1)
The valid data for collecting unit 510 (4) are moved to solid element 310 (D+3) and incited somebody to action in logical block-solid element mapping table
Logical block 510 (4) maps to (or claiming association extremely) solid element 310 (D+3).
Particularly, in this exemplary embodiment, memory management circuitry 202 can be write in chaotic solid element 310 (D+1)
Enter end mark EM.For example, end mark can be recorded in the redundancy of the next physical page of used physical page
In bit area (as illustrated in figure 10 c).That is, in chaotic solid element 310 (D+1), end mark EM can be connected in category
It is recorded after data of the logical block 510 (0) with logical block 510 (4), to represent the data before end mark EM
Data consolidation procedure had been performed.Base this, need to be with chaotic write if there is logical block to enter chaotic write state afterwards
Writing during data, the storage area of below end mark EM can be used to again write this data pattern, to be efficiently used reality
Body unit.In this exemplary embodiment, end mark EM can be any word or any character.
Specifically, as described above, the data write in chaotic write mode are generally a small amount of data, therefore,
Still there are other storage areas to be not used by chaotic solid element 310 (D+1).If being continuing with not written in chaotic solid element
Enter the space of data, until all spaces of chaotic solid element all to this chaotic solid element are performed fortune of erasing again using after
Make, the number of times of erasing of solid element will can be greatly decreased, extend the life-span of memorizer memory devices 100.
Figure 11 is that the example for writing data with chaotic write mode according to another exemplary embodiment of the invention is illustrated
Figure, it belongs to the 3rd logic list with chaotic write mode in the state of tying up to shown in Figure 10 C by come from host computer system 1000
The data (also referred to as the 3rd data) of first (that is, logical block 510 (6)) with belong to the 4th logical block (that is, logical block 510
(2) data (also referred to as the 4th data)) are write to the example of chaotic solid element, wherein assuming that logical block 510 (6) is to reflect
It is incident upon the 6th solid element (that is, solid element 310 (6)) and logical block 510 (2) is to map to the 7th solid element (i.e.,
Solid element 310 (2)).
Figure 11 is refer to, when the 1st logical page (LPAGE) for being intended to belong to logical block 510 (6) with the write of chaotic write mode
During data (that is, updating the 1st physical page of solid element 310 (6)), memory management circuitry 202 can will belong to logic list
The data of the 1st logical page (LPAGE) of unit 510 (6) are write into the 5th physical page of solid element 310 (D+1).Similarly,
Afterwards, when the data for being intended to write the 0th logical page (LPAGE) for belonging to logical block 510 (2) (that is, update solid element 310 (2)
0th physical page) when, memory management circuitry 202 can will belong to the data of the 0th logical page (LPAGE) of logical block 510 (2)
Write into the 6th physical page of solid element 310 (D+1).
Similarly, if memory management circuitry 202 performs data to logical block 510 (6) and logical block 510 (2)
After consolidation procedure, another end mark EM can be connected in the data for belonging to logical block 510 (6) and logical block 510 (2)
It is recorded in afterwards in chaotic solid element 310 (D+1) (as shown in figure 12), to have represented the data before end mark EM
It was performed data consolidation procedure.
If it is noted that having logical block to be to enter chaotic write state simultaneously in memorizer memory devices 100
And when there is abnormal power-off, the memory management circuitry 202 of Memory Controller 104 can be according in chaotic solid element
End mark has completed data consolidation procedure recognizing which data.For example, memory management circuitry 202 can be from chaotic entity list
Last physical page of unit starts to search end mark forward, and identification record terminates mark in first for being searched
Data after note are the data for not completing data consolidation procedure.
Figure 13 is the flow chart of the method for writing data according to exemplary embodiment of the present invention.
Figure 13 is refer to, in step S1301, Memory Controller 104 can receive write instruction from host computer system 1000
And corresponding logic access address and data.
Then, in step S1303, Memory Controller 104 can judge the logical block of this logic access address of correspondence
Whether chaotic write state is entered.
If the logical block for corresponding to this logic access address is introduced into chaotic write state, then in step S1305,
Memory Controller 104 can be write data into into the physical page of corresponding solid element with general write mode.With general
The mode of write mode write data has coordinated Fig. 7～Fig. 9 to describe as above, here not repeated description.
If the logical block for corresponding to this logic access address enters chaotic write state, then in step S1307, deposit
Memory controller 104 determines whether there is the chaotic solid element for being set this logical block of correspondence.
If have the chaotic solid element for being set corresponding this logical block, then in step S1309, memorizer
Controller 104 can in order be write data into corresponding chaotic solid element with chaotic write mode.
If do not have the chaotic solid element for being set corresponding this logical block, then in step S1311, storage
Device controller 104 determines whether to set one of current chaotic solid element gives this logical block.For example, exist
In this exemplary embodiment, Memory Controller 104 can store the number of 2 logical blocks of correspondence using a chaotic solid element
According to.Therefore, if there is any one chaotic solid element only to store 1 logical block of correspondence among current chaotic solid element
During data, then this chaotic solid element can concurrently set and give another logical block.
If judging to set one of current chaotic solid element in step S1311 gives this logic list
Unit, then in step S1313, Memory Controller 104 can set one of confusion solid element to this logical block simultaneously
And in order write data into set chaotic solid element.
If judging to set any one of current chaotic solid element in step S1311 gives this logic list
When first, then in step S1315, Memory Controller 104 can judge whether the number of the chaotic solid element for being used reaches
To predetermined threshold level.
If the number of the chaotic solid element for being used reaches predetermined threshold level, then in step S1317, storage
Device controller 104 can select one of them chaotic solid element for having used to perform data consolidation procedure and selected mixed
End mark is added in random solid element.Perform data consolidation procedure and coordinate Figure 10 C to describe with the mode for adding end mark
As above, here not repeated description.
Afterwards, in step S1319, selected chaotic solid element is set and gives this logical block, and by data according to
Write to sequence into set chaotic solid element.
If the number of the chaotic solid element for being used is not up to predetermined threshold level, then store in step S1321
Device controller 104 can extract a solid element as the chaotic solid element of this logical block of correspondence from idle area 504, and
And in order write data into set chaotic solid element.
In sum, the method for writing data of exemplary embodiment of the present invention and the Memory Controller of the method is made with storage
Device storage device can effectively utilize the storage area of chaotic solid element, reduce the number of times of erasing of solid element, extend non-
The life-span of volatile memory module.
Although the present invention is disclosed as above with embodiment, it is not limited to the present invention, any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make arbitrarily to change and equivalent, therefore protection scope of the present invention should be with
The scope of the claims in the present invention is defined.
Claims (15)
1. a kind of method for writing data, for writing data to multiple physical blocks, the method for writing data includes：
The physical blocks are grouped into into multiple solid elements；
The solid element is at least grouped into into a data field with an idle area；
Configure multiple logical blocks to map the solid element for belonging to the data field；
Reception belongs to one first data of one first logical block among the logical block, and wherein first logical block is reflected
The first instance unit penetrated among the solid element for belonging to the data field；
Judge whether first logical block enters a chaotic write state, the wherein chaotic write state is more than a predetermined frequency
Update the data in the same logical block of rate DIYU；
When first logical block enters the chaotic write state, it is subordinated among the solid element in the idle area and extracts one the
Three solid elements, and first data are write in order into the 3rd solid element；
Reception belongs to one second data of one second logical block among the logical block, and wherein second logical block is reflected
The second instance unit penetrated among the solid element for belonging to the data field；
Judge whether second logical block enters the chaotic write state；
When second logical block enters the chaotic write state, second data are write in order to the 3rd entity list
In unit；
One data consolidation procedure is performed to first logical block and second logical block；And
After the data consolidation procedure is performed to first logical block and second logical block, in the 3rd solid element
One end mark of middle write, wherein the end mark is to be connected in first data with second number in the 3rd solid element
According to after.
2. method for writing data according to claim 1, wherein holding with second logical block to first logical block
The step of row data consolidation procedure, includes：
It is subordinated to one the 4th solid element of extraction among the solid element in the idle area；
Valid data in the first instance unit and first data are write into the 4th solid element；
It is subordinated to one the 5th solid element of extraction among the solid element in the idle area；
Valid data in the second instance unit and second data are write into the 5th solid element；
By first logical unit mappings to the 4th solid element and by second logical unit mappings to the 5th entity
Unit；And
Erase the first instance unit and the second instance unit, and the first instance unit and the second instance unit are closed
It is coupled to the idle area.
3. method for writing data according to claim 1, also includes：
Reception belongs to one the 3rd data of one the 3rd logical block among the logical block, and wherein the 3rd logical block is reflected
One the 6th solid element penetrated among the solid element for belonging to the data field；
Judge whether the 3rd logical block enters the chaotic write state；
When the 3rd logical block enters the chaotic write state, the 3rd data are write in order to the 3rd entity list
In unit；
Reception belongs to one the 4th data of one the 4th logical block among the logical block, and wherein the 4th logical block is reflected
One the 7th solid element penetrated among the solid element for belonging to the data field；
Judge whether the 4th logical block enters the chaotic write state；And
When the 4th logical block enters the chaotic write state, the 4th data are write in order to the 3rd entity list
In unit,
The 3rd data and the 4th data are connected in after the end mark wherein in the 3rd solid element.
4. method for writing data according to claim 3, also includes：
The data consolidation procedure is performed to the 3rd logical block and the 4th logical block；And
After the data consolidation procedure is performed to the 3rd logical block and the 4th logical block, in the 3rd solid element
It is middle write one another end mark, wherein in the 3rd solid element another end mark be connected in the 3rd data with
After 4th data.
5. method for writing data according to claim 3, solid element described in each of which has multiple physical pages simultaneously
And each physical page has a data bit element area and a redundancy bit area,
The step of wherein writing the end mark in the 3rd solid element includes：
This is write in the redundancy bit area of a physical page among the physical page of the 3rd solid element to terminate
Labelling.
6. a kind of Memory Controller, for managing a nonvolatile memory module, wherein the nonvolatile memory module
With multiple physical blocks, the Memory Controller includes：
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to the nonvolatile memory module；And
One memory management circuitry, is electrically connected to the HPI and the memory interface,
Wherein the memory management circuitry by the physical blocks to be grouped into multiple solid elements；By the solid element extremely
A data field is grouped into less with an idle area and configures multiple logical blocks to map the solid element for belonging to the data field,
Wherein the memory management circuitry also belongs to one of one first logical block among the logical block receiving
One data, wherein first logical unit mappings belong to the first instance unit among the solid element of the data field；
Wherein the memory management circuitry wherein should also to judge whether first logical block enters a chaotic write state
Chaotic write state be more than updating the data in the same logical block of a preset frequency DIYU,
Wherein the memory management circuitry is also when first logical block enters the chaotic write state, to be subordinated to the spare time
One the 3rd solid element of extraction among the solid element in area is put, and first data are write in order to the 3rd entity list
In unit,
Wherein the memory management circuitry also belongs to one of one second logical block among the logical block receiving
Two data, wherein second logical unit mappings belong to the second instance unit among the solid element of the data field,
Wherein whether the memory management circuitry also enters the chaotic write state to judge second logical block,
Wherein the memory management circuitry also to second logical block enter the chaotic write state when, by this second number
According to writing in order into the 3rd solid element,
Wherein the memory management circuitry also merges to perform a data to first logical block and second logical block
Program, and after the data consolidation procedure is performed to first logical block and second logical block, the memorizer pipe
Circuit is managed also to write an end mark in the 3rd solid element,
The end mark is connected in after first data and second data wherein in the 3rd solid element.
7. Memory Controller according to claim 6, wherein to first logical block and second logical block
In the performed data consolidation procedure, among the memory management circuitry is to be subordinated to the solid element in the idle area
One the 4th solid element is extracted, the valid data in the first instance unit and first data are write to the 4th entity list
In unit, one the 5th solid element of extraction among the solid element in the idle area is subordinated to, by the second instance unit
Valid data are write into the 5th solid element with second data, by first logical unit mappings to the 4th entity list
Unit, by second logical unit mappings to the 5th solid element, erase the first instance unit and the second instance unit, and
And the first instance unit is associated to the idle area with the second instance unit.
8. Memory Controller according to claim 6,
Wherein the memory management circuitry also belongs to one of one the 3rd logical block among the logical block receiving
Three data, wherein the 3rd logical unit mappings belong to one the 6th solid element among the solid element of the data field,
Wherein whether the memory management circuitry also enters the chaotic write state to judge the 3rd logical block,
Wherein the memory management circuitry is also when the 3rd logical block enters the chaotic write state, the 3rd to be counted
According to writing in order into the 3rd solid element,
Wherein the memory management circuitry also belongs to one of one the 4th logical block among the logical block receiving
Four data, wherein the 4th logical unit mappings belong to one the 7th solid element among the solid element of the data field,
Wherein whether the memory management circuitry also enters the chaotic write state to judge the 4th logical block,
Wherein the memory management circuitry is also when the 4th logical block enters the chaotic write state, the 4th to be counted
According to writing in order into the 3rd solid element,
The 3rd data and the 4th data are connected in after the end mark wherein in the 3rd solid element.
9. Memory Controller according to claim 8,
Wherein the memory management circuitry also merges to perform the data with the 4th logical block to the 3rd logical block
Program,
Wherein after the data consolidation procedure is performed to the 3rd logical block and the 4th logical block, the memory management
Circuit also in the 3rd solid element write an another end mark,
Another end mark is connected in after the 3rd data and the 4th data wherein in the 3rd solid element.
10. Memory Controller according to claim 6, solid element described in each of which has multiple physical pages simultaneously
And each physical page has a data bit element area and a redundancy bit area,
Wherein the memory management circuitry is also to the physical page among the physical page of the 3rd solid element
The redundancy bit area in write the end mark.
A kind of 11. memorizer memory devices, including：
A connector, is electrically connected to a host computer system；
One nonvolatile memory module, with multiple physical blocks；And
One Memory Controller, is electrically connected to the adapter and the nonvolatile memory module,
The wherein Memory Controller the physical blocks are grouped into into multiple solid elements, by the solid element at least
A data field is grouped into an idle area and multiple logical blocks is configured to map the solid element for belonging to the data field,
Wherein the Memory Controller also belongs to one first of one first logical block among the logical block receiving
Data, wherein first logical unit mappings belong to the first instance unit among the solid element of the data field；
Wherein also to judge whether first logical block enters a chaotic write state, wherein this is mixed the Memory Controller
Random write state be more than updating the data in the same logical block of a preset frequency DIYU,
Wherein the Memory Controller is also when first logical block enters the chaotic write state, to be subordinated to this and leave unused
One the 3rd solid element is extracted among the solid element in area, and first data are write in order to the 3rd solid element
In,
Wherein the Memory Controller also belongs to one second of one second logical block among the logical block receiving
Data, wherein second logical unit mappings belong to the second instance unit among the solid element of the data field,
Wherein whether the Memory Controller also enters the chaotic write state to judge second logical block,
Wherein the Memory Controller also to second logical block enter the chaotic write state when, by second data
Write in order into the 3rd solid element,
Wherein the Memory Controller also merges journey to perform a data to first logical block and second logical block
Sequence, and after the data consolidation procedure is performed to first logical block and second logical block, the memorizer control
Device also to write an end mark in the 3rd solid element,
The end mark is connected in after first data and second data wherein in the 3rd solid element.
12. memorizer memory devices according to claim 11, wherein to first logical block and second logic
In the data consolidation procedure performed by unit, the Memory Controller to be subordinated to the idle area the solid element it
One the 4th solid element of middle extraction, the valid data in the first instance unit and first data are write to the 4th entity
In unit, one the 5th solid element of extraction among the solid element in the idle area is subordinated to, by the second instance unit
Valid data and second data write into the 5th solid element, by first logical unit mappings to the 4th entity
Unit, by second logical unit mappings to the 5th solid element, erase the first instance unit and the second instance unit,
And the first instance unit is associated to the idle area with the second instance unit.
13. memorizer memory devices according to claim 11,
Wherein the Memory Controller also belongs to one the 3rd of one the 3rd logical block among the logical block receiving
Data, wherein the 3rd logical unit mappings belong to one the 6th solid element among the solid element of the data field,
Wherein whether the Memory Controller also enters the chaotic write state to judge the 3rd logical block,
Wherein the Memory Controller also to the 3rd logical block enter the chaotic write state when, by the 3rd data
Write in order into the 3rd solid element,
Wherein the Memory Controller also belongs to one the 4th of one the 4th logical block among the logical block receiving
Data, wherein the 4th logical unit mappings belong to one the 7th solid element among the solid element of the data field,
Wherein whether the Memory Controller also enters the chaotic write state to judge the 4th logical block,
Wherein the Memory Controller also to the 4th logical block enter the chaotic write state when, by the 4th data
Write in order into the 3rd solid element,
The 3rd data and the 4th data are connected in after the end mark wherein in the 3rd solid element.
14. memorizer memory devices according to claim 13,
Wherein the Memory Controller also merges journey to perform the data with the 4th logical block to the 3rd logical block
Sequence,
Wherein after the data consolidation procedure is performed to the 3rd logical block and the 4th logical block, the memorizer control
Device also in the 3rd solid element write an another end mark,
Another end mark is connected in after the 3rd data and the 4th data wherein in the 3rd solid element.
15. memorizer memory devices according to claim 11, solid element described in each of which has multiple physical pages
Face and each physical page have a data bit element area and a redundancy bit area,
Wherein the Memory Controller is also to the physical page among the physical page of the 3rd solid element
The end mark is write in the redundancy bit area.
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| CN1300711C (en) * | 2003-04-30 | 2007-02-14 | 日商.萩原科技股份有限公司 | Usb storage device and program |
| CN101571832A (en) * | 2008-04-29 | 2009-11-04 | 群联电子股份有限公司 | Data writing method, quick flashing memory system using same and a controller thereof |
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| CN101571832A (en) * | 2008-04-29 | 2009-11-04 | 群联电子股份有限公司 | Data writing method, quick flashing memory system using same and a controller thereof |
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