CN103943512B - A kind of method reducing Graphene and Electrodes - Google Patents
A kind of method reducing Graphene and Electrodes Download PDFInfo
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 137
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- 238000000034 method Methods 0.000 title claims abstract description 56
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 57
- 229910052759 nickel Inorganic materials 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
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- 229910052681 coesite Inorganic materials 0.000 claims description 8
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- 229910052682 stishovite Inorganic materials 0.000 claims description 8
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- 238000001259 photo etching Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
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- 239000010931 gold Substances 0.000 claims description 5
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The present invention provides a kind of method reducing Graphene and Electrodes, including step: first, it is provided that substrate, forms Graphene over the substrate；Then, the BN thin film at the edge exposing Graphene two ends is formed at described graphenic surface；Then, define source, drain regions, form metal catalytic layer, and be annealed in hydrogen atmosphere, making described metal catalytic layer agglomerate into catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN, forms the hole of laciniation at Graphene and BN surface；Formation source, leakage metal electrode, gate dielectric layer and grid.The present invention adopts metal catalytic layer etching Graphene, in the process annealed under an atmosphere of hydrogen, metal catalytic layer agglomerates into little granule, hydrogen is along the etching edge BN/ graphenic surface of granule, form the hole with Zigzag marginal texture, and extremely strong chemical bond can be formed with the source deposited subsequently, leakage metal electrode, make metal electrode contact better with Graphene.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of method reducing Graphene and Electrodes.
Background technology
Graphene is since coming out, and the electron mobility that the electrology characteristic of its excellence is such as high, heat conductivity is strong, and conductivity is high, Stability Analysis of Structures, and electron transfer rate is fast, causes the extensive concern of people, is expected to be used to manufacture a new generation's high-performance electronic device.But, based in the research of graphene device, it has been found that the electric property that test obtains and theoretical value differ greatly.Wherein Graphene-metal contact resistance becomes the most important factor affecting grapheme transistor performance.At present, have been reported the Electrodes reducing between Graphene and metal with various diverse ways, most common method is for Graphene carried out after annealing process before metallizing, although research shows that annealing can remove the pollution of graphenic surface, the impact of Electrodes is also little.Or adopt atomic force scan process, the methods such as UV/ozone (UVO) processes, Cement Composite Treated by Plasma, but these methods are not only time-consuming but also can destroy graphene-structured.It is demonstrated experimentally that can not effectively reduce the contact resistance of Graphene metal only by the residual light photoresist removing graphenic surface.And by the method that electron beam exposure or oxygen plasma process re-annealing, can in Graphene edge defect, deposit metal subsequently, formed " contactless " Graphene metal contact interface, can effectively reduce the contact resistance of graphene device.If but unannealed, can form the structure of unordered amorphous along the edge that Graphene is etched, the contact area of Graphene and metal also will diminish.
And the Electrodes that a kind of easier method will be adopted to effectively reduce graphene device herein, namely metal catalytic etching Graphene is adopted, in atmosphere of hydrogen, graphite aggregate alkene can be formed subsequently and there is Zigzag border hole, then deposit metal and can obtain less Graphene metal contact resistance.The present invention is compatible with CMOS manufacturing process, it is possible to is applied to the making of graphene nano electronic device and and is hopeful to be applied in graphene-based integrated circuit.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of method reducing Graphene and Electrodes, the problem big for solving in prior art contact resistance between Graphene and metal electrode.
For achieving the above object and other relevant purposes, the present invention provides a kind of method reducing Graphene and Electrodes, and described method at least comprises the following steps:
1) substrate is provided, forms Graphene over the substrate；
2) forming BN thin film at described graphenic surface, described BN thin film exposes the edge at Graphene two ends；
3) graphic definition comprises graphene edge and the source of part BN thin film, the drain regions of exposure, in described source, drain regions formation of deposits metal catalytic layer, and be annealed in hydrogen atmosphere, described metal catalytic layer is made to agglomerate into catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN thin film, forms the hole of laciniation at Graphene and BN film surface；
4) in described source, drain regions area deposition metal formed source, leakage metal electrode, described source, leakage metal electrode fills and covers in described hole, with described Graphene formation contact；
5) between described metal electrode, Graphene and BN thin film form gate dielectric layer, and on described gate dielectric layer, form grid.
Preferably, described step 1) in backing material be Si, SiO2、SiO2Any one in/Si, GaAs or GaN.
Preferably, described step 1) the middle method acquisition graphene film adopting mechanical stripping or chemical vapor deposition growth transfer, adopt photoetching or electron beam exposure definition Graphene etched features again, finally adopt reactive ion beam etching (RIBE) method by oxygen plasma etch graphene film forming step 1) in required banding Graphene.
Preferably, described step 2) in BN thin film be that mechanical stripping obtains, transfer to step 1) described in structure on；The thickness of described BN thin film is 10～30nm.
Preferably, described step 2) in the graphene edge width that exposes be 1～2 atomic layer degree of depth.
Preferably, described step 3) in the thickness of metal catalytic layer of formation of deposits be 1～10nm.
Preferably, described metal catalytic layer is any one in nickel, gold, chromium, copper, platinum.
Preferably, described step 3) annealing process in also include passing into argon, adopt the argon hydrogen mixed atmosphere of 150～250sccm flow to be annealed, wherein, Ar and H2Flow-rate ratio is 1.8:1～2:1, and annealing temperature is 200～600 DEG C, and annealing time ranges for 10～30min.
Preferably, described step 4) in source, leakage metal electrode thickness be 30～100nm.
Preferably, described source, leakage metal electrode material are nickel.
Preferably, described step 5) the middle method growth described gate dielectric layer of formation adopting ald.
Preferably, the described gate dielectric layer of formation is Al2O3, the thickness of gate dielectric layer is 10～50nm.
Preferably, in described step 5) after, also include the step forming contact electrode respectively on described source, leakage metal electrode and gate electrode.
As it has been described above, the method reducing Graphene and Electrodes of the present invention, including step: first, it is provided that a substrate, form Graphene over the substrate；Then, forming BN thin film at described graphenic surface, described BN thin film exposes the edge at Graphene two ends；Then, graphic definition includes the graphene edge and the source of part BN thin film, the drain regions that expose, in described source, drain regions formation of deposits metal catalytic layer, and be annealed in hydrogen atmosphere, described metal catalytic layer is made to agglomerate into catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN thin film, forms the hole of laciniation at Graphene and BN film surface；Then in described source, drain regions formation of deposits source, leakage metal electrode；Finally between described metal electrode, Graphene and BN thin film form gate dielectric layer, and on described gate dielectric layer, form grid.The present invention adopts metal catalytic layer etching Graphene: in the process annealed under an atmosphere of hydrogen, metal catalytic layer agglomerates into little granule, hydrogen starts to etch BN/ graphenic surface along the edge of nickel granule, is formed and has the triangle of Zigzag marginal texture or hexagonal hole.And the pore quantity that BN/ Graphene is etched depends on the thickness of the thin layer nickel thin film deposited, nickel thickness is more thin, and the Graphene hole that etching is formed is more many.Metal catalytic layer etching technics makes the flawless hole edge with Zigzag structure that graphenic surface is formed, and can form extremely strong chemical bond with the source deposited subsequently, leakage metal electrode so that metal electrode contacts better with Graphene.The obtained metal electrode of the present invention is without other re-annealing, and Graphene metal contact resistance also will reduce greatly, it is possible to obtains higher carrier mobility.
Accompanying drawing explanation
The present invention that is shown as Fig. 1 reduces the method flow schematic diagram of Graphene and Electrodes.
Fig. 2 a is the substrate schematic perspective view of the present invention.
Fig. 2 b is the substrate sectional view of the present invention.
Fig. 3 a is the structural upright schematic diagram forming Graphene on substrate.
Fig. 3 b is the structure sectional view forming Graphene on substrate.
Fig. 4 a is the structural upright schematic diagram that Graphene is etched.
Fig. 4 b is the structure sectional view that Graphene is etched.
Fig. 5 a is the structural upright schematic diagram forming BN thin film on substrate.
Fig. 5 b is the sectional view forming BN thin film on substrate.
Fig. 6 a is the structural upright schematic diagram after etching BN thin film.
Fig. 6 b is the structure sectional view after etching BN thin film.
Fig. 7 a forms the structure top view of sheet metal Catalytic Layer in S/D region.
Fig. 7 b forms the sectional view of sheet metal Catalytic Layer in S/D region.
Fig. 8 is structure top view after substrat structure annealing.
Fig. 9 is the structure top view of S/D area deposition thick layer of metal nickel electrode.
Figure 10 is the ALD structure top view growing gate dielectric layer.
Figure 11 is the structure top view growing gate electrode on gate dielectric layer.
Figure 12 is the structure top view that etching gate medium exposes source, leakage metal electrode.
Figure 13 is the structure top view forming S/D/G electrode contact.
Element numbers explanation
S1～S5 step
1 substrate
2 Graphenes
3BN thin film
4 metal catalytic nickel thin layers
5 sources, leakage metal electrode
6 gate dielectric layers
7 grids
8 contact electrodes
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art the content disclosed by this specification can understand other advantages and effect of the present invention easily.The present invention can also be carried out by additionally different detailed description of the invention or apply, and the every details in this specification based on different viewpoints and application, can also carry out various modification or change under the spirit without departing from the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, then assembly that in graphic, only display is relevant with the present invention but not component count when implementing according to reality, shape and size drafting, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
The present invention provides a kind of method lowering Graphene and Electrodes, as it is shown in figure 1, described method at least comprises the following steps:
S1 a, it is provided that substrate, forms Graphene over the substrate；
S2, forms BN thin film at described graphenic surface, and described BN thin film exposes the edge at Graphene two ends；
S3, graphic definition includes the graphene edge and the source of part BN thin film, the drain regions that expose, in described source, drain regions formation of deposits metal catalytic layer, and be annealed in hydrogen atmosphere, described metal catalytic layer is made to agglomerate into catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN thin film, forms the hole of zigzag (zigzag) structure at Graphene and BN film surface；
S4, in described source, drain regions formation of deposits source, leakage metal electrode, described source, leakage metal electrode be filled in described hole, with described Graphene formed contact；
S5, forms gate dielectric layer on Graphene and BN thin film between described metal electrode, and forms grid on described gate dielectric layer.
Below in conjunction with concrete accompanying drawing, the method reducing Graphene and Electrodes of the present invention is done detailed introduction.
Step S1 is first carried out, it is provided that a substrate, forms Graphene over the substrate.
Referring to accompanying drawing 2a and Fig. 2 b, for substrate 1 provided by the invention, described substrate 1 includes but not limited to Si, SiO2、SiO2/ Si, GaAs, GaN etc., in the present embodiment, it is preferred to SiO2/ Si substrate.Also include the cleaning step of substrate 1 in this step, the present embodiment adopts standard RCA technique clean described SiO2/ Si substrate.
Refer to accompanying drawing 3a and Fig. 3 b, for forming Graphene 2 thin film on described substrate 1 surface.Wherein, Graphene 2 thin film can pass through chemical vapour deposition (CVD) (CVD) growth transfer on described substrate 1 obtain, it is also possible to be that the method either directly through mechanical stripping obtains.The present embodiment is preferably and adopts CVD growth transfer to obtain.
Refer to accompanying drawing 4a and Fig. 4 b, for forming required Graphene 2 by described Graphene 2 thin film of etching.Detailed process is: is defined the etched features of Graphene 2 by photoetching or electron beam exposure, and adopts reactive ion etching (RIE) to form the Graphene 2 of banded structure by oxygen plasma etch graphene film.
Performing step S2 afterwards, form BN thin film at described graphenic surface, described BN thin film exposes the edge at Graphene two ends.
Can adopt mechanical stripping method, after obtaining BN thin film, the BN thin film of acquisition is transferred to described substrate, thus forming the BN thin film 3 covering described Graphene 2 on described substrate 1, as shown in figure 5a and 5b.The THICKNESS CONTROL of described BN thin film 3 is within the scope of 10～30nm.
The structure formed for the BN thin film in etching Fig. 5 a and 5b as shown in figure 6 a and 6b, so that described BN thin film 3 exposes the edge at Graphene 2 two ends, Graphene 2 border width of exposure is 1～2 atomic layer degree of depth.Concrete forming process is: successively Fig. 5 a and 5b obtain structure on formed 90nmPMMA and 90nm hydrogen-based siloxanes HSQ electron beam adhesive as etch mask layer, after electron beam exposure, adopt ICP to etch BN thin film and obtain such as BN thin film 3 structure of Fig. 6 a and 6b.Owing to BN thin film 3 lattice is approximate with Graphene 2 and surface is comparatively smooth, it it is good insulant, graphenic surface can be completely cut off contact with the direct of metal electrode so that the Graphene Zigzag edge formation metal that metal electrode is obtained with etching by the hole formed after subsequent metal catalysis etching BN/ Graphene contacts.
Then step S3 is performed, graphic definition comprises graphene edge and the source of part BN thin film, the drain regions of exposure, in described source, drain regions formation of deposits metal catalytic layer, and be annealed in hydrogen atmosphere, described metal catalytic layer is made to agglomerate into catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN, forms the hole of laciniation at Graphene table and BN face.
The metal catalytic nickel thin layer 4 formed is as illustrated in figs. 7 a and 7b.Specifically, adopt photoetching or electron beam exposure definition source, drain regions stringer metal catalytic nickel thin film 4, peel off subsequently and remove photoresist.Described source, drain regions comprise Graphene 2 edge and the part BN thin film 3 of exposure, and therefore, the metal catalytic nickel thin film 4 of deposition covers Graphene 2 edge and part BN thin film 3.Can adopting sputtering or electron-beam evaporation metal catalytic nickel thin film 4, the thickness of this sheet metal catalytic nickel thin film 4 is 1～10nm.In the present embodiment, metal catalytic nickel thin film 4 is preferably about 2nm.
The structure of Fig. 7 a and 7b is annealed in the argon hydrogen mixed atmosphere that flow is 200sccm, wherein, Ar and H2Flow-rate ratio is 2:1.Annealing temperature is arranged within the scope of 200～600 DEG C, and annealing time is 10～30min.In the process of hydrogen annealing, sheet metal catalytic nickel thin film 4 agglomerates into little granule, hydrogen starts to etch Graphene 2 and BN thin film 3 surface along the edge of these nickel granules, BN/ graphenic surface being formed and has the triangle of zigzag (Zigzag) marginal texture or hexagonal hole, the structure after annealing is as shown in Figure 8.Wherein the mechanism of nickel catalysis etching is: under the catalytic action of nickel, and Graphene 2 and hydrogen react: C (solid)+2H2(gas)——CH4(gas)；BN thin film 3 and hydrogen react: BN (solid)+H2(gas)——BxHy(Gas)+NH3(gas).Nickle atom group ultimately forms the island being embedded in Graphene 2 and BN thin film 3, and the pore quantity that Graphene is etched depends on the thickness of the thin layer nickel catalytic film deposited, and nickel thickness is more thin, and the Graphene hole that etching is formed is more many.Nickel catalysis etching technics makes the flawless hole edge with Zigzag structure that graphenic surface is formed, and can form extremely strong chemical bond with the thick-layer nickel thin film deposited subsequently.Obtained electrode is without other re-annealing, and Graphene metal contact resistance also will reduce greatly.Described metal catalytic material can be nickel, gold, chromium, titanium, copper, platinum etc..In the present embodiment, it is preferred to use nickel is as metal catalytic material.
Then perform step S4, in described source, drain regions formation of deposits source, leakage metal electrode, described source, leakage metal electrode be filled in described hole, with described Graphene formed contact.
Specifically, the step of definition source, drain regions in step S3 is repeated.In the source of definition, drain regions, deposition thick-layer nickel thin film is as metal electrode material, stripping is removed photoresist and is obtained source, leakage metal electrode 5, being illustrated in figure 9 top view, this source, leakage metal electrode 5 cover in Graphene 2, BN thin film 3 surface and hole, are formed with described Graphene 2 and contact.
Due to the catalysis corrasion of sheet metal nickel Catalytic Layer in step S3, before deposition thick-layer metallic nickel electrode, BN/ graphenic surface has been etched and has defined the triangle with Zigzag marginal texture or hexagonal hole, therefore, extremely strong chemical bond can be formed by orbital hybridization, so that the Graphene metal electrode contact resistance obtained effectively reduces between Graphene 2 and metal electrode 4.Graphene 2 edge of 1～2 the atom width simultaneously exposed in step S2 can be etched equally and form Zigzag structure, it is possible to directly contacts with metal and forms good approximate one-dimensional electrode contact structure.Its medium bed source, leakage metal electrode 4 nickel thin film thickness be 30～100nm.
Perform step S5 again, between described metal electrode, Graphene and BN thin film form gate dielectric layer, and on described gate dielectric layer, form grid.
Referring to accompanying drawing 10, first adopt the method for ald (ALD) at the gate dielectric layer 6 that whole substrate surface growth thickness is 10～50nm, the body structure surface that step S4 obtains all is covered by this gate dielectric layer 6, and this gate dielectric layer 6 can be Al2O3。
Referring to accompanying drawing 11, then adopt photoetching or electron beam exposure (EBL) graphic definition gate electrode figure, deposition metal Ti/Au forms gate electrode 7 on the gate dielectric layer between source, leakage metal electrode 4.
Refer to accompanying drawing 12, adopt the etched features of photoetching or electron beam exposure (EBL) graphic definition gate dielectric layer, etching gate dielectric layer 6 to expose source, leakage metal electrode 4.
Refer to accompanying drawing 13, after formation source, leakage metal electrode 4 and gate electrode 7, adopt photoetching or electron beam exposure (EBL) graphic definition S/D/G electrode contact figure, deposit metal Ti/Au, peeling off removes photoresist forms the contact electrode 8 of S/D/G, it is simple to subsequent device performance test.
In sum, the present invention provides a kind of method reducing Graphene and Electrodes, adopts the method for metal catalytic etching Graphene that Graphene is processed, and depositing metal films forms the contact of Graphene metal electrode subsequently.When Graphene is annealed by the method under an atmosphere of hydrogen, metal material meeting catalysis etching Graphene defines the hole of perfect Zigzag structure, therefore can effectively reduce the Graphene metal contact resistance of graphene device so that carrier mobility improves 1.5 times.Simultaneously device technology can re-annealing further after completing.Preparation method provided by the invention is compatible with traditional cmos manufacturing process, is applied to nano electron device for Graphene and graphene-based integrated circuit provides good solution.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment is illustrative principles of the invention and effect thereof only, not for the restriction present invention.Above-described embodiment all under the spirit and category of the present invention, can be modified or change by any those skilled in the art.Therefore, art has usually intellectual such as modifying without departing from all equivalences completed under disclosed spirit and technological thought or change, must be contained by the claim of the present invention.
Claims (14)
1. the method reducing Graphene and Electrodes, it is characterised in that the method for described reduction Graphene and Electrodes at least includes step:
1) substrate is provided, forms Graphene over the substrate；
2) forming BN thin film at described graphenic surface, described BN thin film exposes the edge at Graphene two ends；
3) graphic definition comprises graphene edge and the source of part BN thin film, the drain regions of exposure, in described source, drain regions formation of deposits metal catalytic layer, and be annealed in hydrogen atmosphere, described metal catalytic layer is made to agglomerate into catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts along the edge of described catalysed particulate with Graphene and BN thin film, forms the hole of laciniation at Graphene and BN film surface；
4) in described source, drain regions formation of deposits source, leakage metal electrode, described source, leakage metal electrode fills and covers in described hole, with described Graphene formation contact；
5) on described source, the Graphene leaked between metal electrode and BN thin film, form gate dielectric layer, and on described gate dielectric layer, form grid.
2. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 1) in backing material be Si, SiO2、SiO2Any one in/Si, GaAs or GaN.
3. the method for reduction Graphene according to claim 1 and Electrodes, it is characterized in that: described step 1) the middle method acquisition graphene film adopting mechanical stripping or chemical vapor deposition growth transfer, adopt photoetching or electron beam exposure definition Graphene etched features again, finally adopt reactive ion beam etching (RIBE) method by oxygen plasma etch graphene film forming step 1) in required banding Graphene.
4. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 2) in BN thin film be that mechanical stripping obtains, transfer to step 1) described in structure on；The thickness of described BN thin film is 10～30nm.
5. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 2) in the graphene edge width that exposes be 1～2 atomic layer degree of depth.
6. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 3) in the thickness of metal catalytic layer of formation of deposits be 1～10nm.
7. the method for reduction Graphene according to claim 6 and Electrodes, it is characterised in that: described metal catalytic layer is any one in nickel, gold, chromium, copper, platinum.
8. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 3) in the hole of laciniation be triangle or hexagon.
9. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 3) annealing process in also include passing into argon, adopt the argon hydrogen mixed atmosphere of 150～250sccm flow to be annealed, wherein, Ar and H2Flow-rate ratio is 1.8:1～2:1, and annealing temperature is 200～600 DEG C, and annealing time ranges for 10～30min.
10. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 4) in source, leakage metal electrode thickness be 30～100nm.
11. the method for reduction Graphene according to claim 10 and Electrodes, it is characterised in that: described source, leakage metal electrode material are nickel.
12. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: described step 5) the middle method growth described gate dielectric layer of formation adopting ald.
13. the method for reduction Graphene according to claim 12 and Electrodes, it is characterised in that: the described gate dielectric layer of formation is Al2O3, the thickness of gate dielectric layer is 10～50nm.
14. the method for reduction Graphene according to claim 1 and Electrodes, it is characterised in that: in described step 5) after, also include the step forming contact electrode respectively on described source, leakage metal electrode and grid.
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| CN104992905B (en) * | 2015-06-05 | 2018-02-13 | 中国科学院上海微系统与信息技术研究所 | A kind of boron nitride substrate surface step lithographic method |
| FR3052593B1 (en) | 2016-06-13 | 2018-06-15 | Commissariat Energie Atomique | METHOD FOR PRODUCING AN ELECTRICAL CONTACT ON A STRUCTURE |
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